1 |
2 |
alfik |
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
2 |
|
|
<html xmlns="http://www.w3.org/1999/xhtml">
|
3 |
|
|
<head>
|
4 |
|
|
<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
|
5 |
|
|
<title>aoOCS: Architecture</title>
|
6 |
|
|
<link href="tabs.css" rel="stylesheet" type="text/css"/>
|
7 |
|
|
<link href="doxygen.css" rel="stylesheet" type="text/css"/>
|
8 |
|
|
</head>
|
9 |
|
|
<body>
|
10 |
|
|
<!-- Generated by Doxygen 1.7.2 -->
|
11 |
|
|
<div class="navigation" id="top">
|
12 |
|
|
<div class="tabs">
|
13 |
|
|
<ul class="tablist">
|
14 |
|
|
<li><a href="index.html"><span>Main Page</span></a></li>
|
15 |
|
|
<li><a href="annotated.html"><span>Design Unit List</span></a></li>
|
16 |
|
|
<li><a href="files.html"><span>Files</span></a></li>
|
17 |
|
|
</ul>
|
18 |
|
|
</div>
|
19 |
|
|
<div class="navpath">
|
20 |
|
|
<ul>
|
21 |
|
|
<li><a class="el" href="index.html">index</a> </li>
|
22 |
|
|
</ul>
|
23 |
|
|
</div>
|
24 |
|
|
</div>
|
25 |
|
|
<div class="header">
|
26 |
|
|
<div class="headertitle">
|
27 |
|
|
<h1>Architecture </h1> </div>
|
28 |
|
|
</div>
|
29 |
|
|
<div class="contents">
|
30 |
|
|
<table border="0" align="center">
|
31 |
|
|
<caption align="bottom"><b>Figure 1:</b> <a class="el" href="classaoOCS.html" title="aoOCS top-level module for the Terasic DE2-70 board. ">aoOCS</a> structure. </caption>
|
32 |
|
|
<tr>
|
33 |
|
|
<td><div align="center">
|
34 |
|
|
<img src="structure.png" alt="structure.png"/>
|
35 |
|
|
</div>
|
36 |
|
|
</td></tr>
|
37 |
|
|
</table>
|
38 |
|
|
<h1><a class="el" href="classcontrol__osd.html" title="On-Screen-Display and overall system management. ">control_osd</a></h1>
|
39 |
|
|
<p>On-Screen-Display and overall system management. </p>
|
40 |
|
|
<h1><a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a></h1>
|
41 |
|
|
<p><a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a> top level module. </p>
|
42 |
|
|
<p>This module contains only instantiations of sub-modules and wire declarations. </p>
|
43 |
|
|
<h1><a class="el" href="classocs__control.html" title="OCS system control implementation with WISHBONE slave interface. ">ocs_control</a></h1>
|
44 |
|
|
<p>OCS system control implementation with WISHBONE slave interface. </p>
|
45 |
|
|
<p>List of system control registers: </p>
|
46 |
|
|
<div class="fragment"><pre class="fragment">
|
47 |
|
|
Implemented:
|
48 |
|
|
[DDFSTOP 094 W A Display bitplane data fetch stop
|
49 |
|
|
(horiz. position) write not implemented here]
|
50 |
|
|
DMACON 096 W ADP DMA control write (clear or set) write not implemented here
|
51 |
|
|
|
52 |
|
|
DMACONR *002 R AP DMA control (and blitter status) read
|
53 |
|
|
VPOSR *004 R A( E ) Read vert most signif. bit (and frame flop)
|
54 |
|
|
VHPOSR *006 R A Read vert and horiz. position of beam
|
55 |
|
|
|
56 |
|
|
ADKCON 09E W P Audio, disk, UART control
|
57 |
|
|
|
58 |
|
|
ADKCONR *010 R P Audio, disk control register read
|
59 |
|
|
[POT0DAT *012 R P( E ) Pot counter pair 0 data (vert,horiz) read implemented here]
|
60 |
|
|
|
61 |
|
|
INTENAR *01C R P Interrupt enable bits read
|
62 |
|
|
INTREQR *01E R P Interrupt request bits read
|
63 |
|
|
|
64 |
|
|
[CLXCON 098 W D Collision control write not implemented here]
|
65 |
|
|
INTENA 09A W P Interrupt enable bits (clear or set bits) write not implemented here
|
66 |
|
|
INTREQ 09C W P Interrupt request bits (clear or set bits)
|
67 |
|
|
|
68 |
|
|
Not implemented:
|
69 |
|
|
REFPTR & *028 W A Refresh pointer
|
70 |
|
|
VPOSW *02A W A Write vert most signif. bit (and frame flop)
|
71 |
|
|
VHPOSW *02C W A Write vert and horiz position of beam
|
72 |
|
|
|
73 |
|
|
STREQU & *038 S D Strobe for horiz sync with VB and EQU
|
74 |
|
|
STRVBL & *03A S D Strobe for horiz sync with VB (vert. blank)
|
75 |
|
|
STRHOR & *03C S DP Strobe for horiz sync
|
76 |
|
|
STRLONG & *03E S D( E ) Strobe for identification of long horiz. line.
|
77 |
|
|
|
78 |
|
|
RESERVED 1110X
|
79 |
|
|
RESERVED 1111X
|
80 |
|
|
NO-OP(NULL) 1FE
|
81 |
|
|
</pre></div> <h1><a class="el" href="classocs__blitter.html" title="OCS blitter implementation with WISHBONE master and slave interface. ">ocs_blitter</a></h1>
|
82 |
|
|
<p>OCS blitter implementation with WISHBONE master and slave interface. </p>
|
83 |
|
|
<p>List of blitter registers: </p>
|
84 |
|
|
<div class="fragment"><pre class="fragment">
|
85 |
|
|
Implemented:
|
86 |
|
|
BLTCON0 ~040 W A Blitter control register 0
|
87 |
|
|
BLTCON1 ~042 W A( E ) Blitter control register 1
|
88 |
|
|
BLTAFWM ~044 W A Blitter first word mask for source A
|
89 |
|
|
BLTALWM ~046 W A Blitter last word mask for source A
|
90 |
|
|
BLTCPTH + ~048 W A Blitter pointer to source C (high 3 bits)
|
91 |
|
|
BLTCPTL + ~04A W A Blitter pointer to source C (low 15 bits)
|
92 |
|
|
BLTBPTH + ~04C W A Blitter pointer to source B (high 3 bits)
|
93 |
|
|
BLTBPTL + ~04E W A Blitter pointer to source B (low 15 bits)
|
94 |
|
|
BLTAPTH + ~050 W A( E ) Blitter pointer to source A (high 3 bits)
|
95 |
|
|
BLTAPTL + ~052 W A Blitter pointer to source A (low 15 bits)
|
96 |
|
|
BLTDPTH + ~054 W A Blitter pointer to destination D (high 3 bits)
|
97 |
|
|
BLTDPTL + ~056 W A Blitter pointer to destination D (low 15 bits)
|
98 |
|
|
BLTSIZE ~058 W A Blitter start and size (window width,height)
|
99 |
|
|
BLTCMOD ~060 W A Blitter modulo for source C
|
100 |
|
|
BLTBMOD ~062 W A Blitter modulo for source B
|
101 |
|
|
BLTAMOD ~064 W A Blitter modulo for source A
|
102 |
|
|
BLTDMOD ~066 W A Blitter modulo for destination D
|
103 |
|
|
BLTCDAT % ~070 W A Blitter source C data register
|
104 |
|
|
BLTBDAT % ~072 W A Blitter source B data register
|
105 |
|
|
BLTADAT % ~074 W A Blitter source A data register
|
106 |
|
|
Not implemented:
|
107 |
|
|
BLTDDAT & *000 ER A Blitter destination early read (dummy address)
|
108 |
|
|
</pre></div> <h1><a class="el" href="classocs__copper.html" title="OCS copper implementation with WISHBONE master and slave interface. ">ocs_copper</a></h1>
|
109 |
|
|
<p>OCS copper implementation with WISHBONE master and slave interface. </p>
|
110 |
|
|
<p>List of copper registers: </p>
|
111 |
|
|
<div class="fragment"><pre class="fragment">
|
112 |
|
|
Implemented:
|
113 |
|
|
COPCON *02E W A( E ) Coprocessor control register (CDANG)
|
114 |
|
|
COP1LCH + 080 W A( E ) Coprocessor first location register (high 3 bits, high 5 bits if ECS)
|
115 |
|
|
COP1LCL + 082 W A Coprocessor first location register (low 15 bits)
|
116 |
|
|
COP2LCH + 084 W A( E ) Coprocessor second location register (high 3 bits, high 5 bits if ECS)
|
117 |
|
|
COP2LCL + 086 W A Coprocessor second location register (low 15 bits)
|
118 |
|
|
COPJMP1 088 S A Coprocessor restart at first location
|
119 |
|
|
COPJMP2 08A S A Coprocessor restart at second location
|
120 |
|
|
Not implemented:
|
121 |
|
|
COPINS 08C W A Coprocessor instruction fetch identify
|
122 |
|
|
</pre></div><dl class="note"><dt><b>Note:</b></dt><dd><ul>
|
123 |
|
|
<li><code>COPINS</code> is not implemented. </li>
|
124 |
|
|
</ul>
|
125 |
|
|
</dd></dl>
|
126 |
|
|
<h1><a class="el" href="classocs__serial.html" title="OCS serial port implementation with WISHBONE slave interface. [functionality not implemented]. ">ocs_serial</a></h1>
|
127 |
|
|
<p>OCS serial port implementation with WISHBONE slave interface. [functionality not implemented]. </p>
|
128 |
|
|
<p>List of serial registers: </p>
|
129 |
|
|
<div class="fragment"><pre class="fragment">
|
130 |
|
|
Not implemented:
|
131 |
|
|
SERDATR *018 R P Serial port data and status read read implemented here
|
132 |
|
|
[DSKBYTR *01A R P Disk data byte and status read read implemented here]
|
133 |
|
|
|
134 |
|
|
SERDAT *030 W P Serial port data and stop bits write
|
135 |
|
|
SERPER *032 W P Serial port period and control
|
136 |
|
|
</pre></div> <h1><a class="el" href="classbus__terminator.html" title="Terminator for not handled WISHBONE bus cycles. ">bus_terminator</a></h1>
|
137 |
|
|
<p>Terminator for not handled WISHBONE bus cycles. </p>
|
138 |
|
|
<h1><a class="el" href="classbus__syscon.html" title="WISHBONE priority and round-robin SYSCON. ">bus_syscon</a></h1>
|
139 |
|
|
<p>WISHBONE priority and round-robin SYSCON. </p>
|
140 |
|
|
<h1><a class="el" href="classocs__video.html" title="OCS video implementation with WISHBONE master and slave interface. ">ocs_video</a></h1>
|
141 |
|
|
<p>OCS video implementation with WISHBONE master and slave interface. </p>
|
142 |
|
|
<p>List of video registers: </p>
|
143 |
|
|
<div class="fragment"><pre class="fragment">
|
144 |
|
|
Implemented:
|
145 |
|
|
DIWSTRT 08E W A Display window start (upper left vert-horiz position)
|
146 |
|
|
DIWSTOP 090 W A Display window stop (lower right vert.-horiz. position)
|
147 |
|
|
DDFSTRT 092 W A Display bitplane data fetch start (horiz. position)
|
148 |
|
|
DDFSTOP 094 W A Display bitplane data fetch stop write implemented here
|
149 |
|
|
[DMACON 096 W ADP DMA control write (clear or set) write implemented here]
|
150 |
|
|
|
151 |
|
|
[JOY1DAT *00C R D Joystick-mouse 1 data (vert,horiz) read not implemented here]
|
152 |
|
|
CLXDAT *00E R D Collision data register (read and clear) read not implemented here
|
153 |
|
|
CLXCON 098 W D Collision control write implemented here
|
154 |
|
|
[INTENA 09A W P Interrupt enable bits (clear or set bits) write implemented here]
|
155 |
|
|
|
156 |
|
|
BPLCON0 100 W AD( E ) Bitplane control register (misc. control bits)
|
157 |
|
|
BPLCON1 102 W D Bitplane control reg. (scroll value PF1, PF2)
|
158 |
|
|
BPLCON2 104 W D( E ) Bitplane control reg. (priority control)
|
159 |
|
|
|
160 |
|
|
BPL1MOD 108 W A Bitplane modulo (odd planes)
|
161 |
|
|
BPL2MOD 10A W A Bitplane modulo (even planes)
|
162 |
|
|
|
163 |
|
|
BPL1PTH + 0E0 W A Bitplane 1 pointer (high 3 bits)
|
164 |
|
|
BPL1PTL + 0E2 W A Bitplane 1 pointer (low 15 bits)
|
165 |
|
|
BPL2PTH + 0E4 W A Bitplane 2 pointer (high 3 bits)
|
166 |
|
|
BPL2PTL + 0E6 W A Bitplane 2 pointer (low 15 bits)
|
167 |
|
|
BPL3PTH + 0E8 W A Bitplane 3 pointer (high 3 bits)
|
168 |
|
|
BPL3PTL + 0EA W A Bitplane 3 pointer (low 15 bits)
|
169 |
|
|
BPL4PTH + 0EC W A Bitplane 4 pointer (high 3 bits)
|
170 |
|
|
BPL4PTL + 0EE W A Bitplane 4 pointer (low 15 bits)
|
171 |
|
|
BPL5PTH + 0F0 W A Bitplane 5 pointer (high 3 bits)
|
172 |
|
|
BPL5PTL + 0F2 W A Bitplane 5 pointer (low 15 bits)
|
173 |
|
|
BPL6PTH + 0F4 W A Bitplane 6 pointer (high 3 bits)
|
174 |
|
|
BPL6PTL + 0F6 W A Bitplane 6 pointer (low 15 bits)
|
175 |
|
|
|
176 |
|
|
BPL1DAT & 110 W D Bitplane 1 data (parallel-to-serial convert)
|
177 |
|
|
BPL2DAT & 112 W D Bitplane 2 data (parallel-to-serial convert)
|
178 |
|
|
BPL3DAT & 114 W D Bitplane 3 data (parallel-to-serial convert)
|
179 |
|
|
BPL4DAT & 116 W D Bitplane 4 data (parallel-to-serial convert)
|
180 |
|
|
BPL5DAT & 118 W D Bitplane 5 data (parallel-to-serial convert)
|
181 |
|
|
BPL6DAT & 11A W D Bitplane 6 data (parallel-to-serial convert)
|
182 |
|
|
|
183 |
|
|
SPR0PTH + 120 W A Sprite 0 pointer (high 3 bits)
|
184 |
|
|
SPR0PTL + 122 W A Sprite 0 pointer (low 15 bits)
|
185 |
|
|
SPR0POS % 140 W AD Sprite 0 vert-horiz start position data
|
186 |
|
|
SPR0CTL % 142 W AD( E ) Sprite 0 vert stop position and control data
|
187 |
|
|
SPR0DATA % 144 W D Sprite 0 image data register A
|
188 |
|
|
SPR0DATB % 146 W D Sprite 0 image data register B
|
189 |
|
|
SPR1PTH + 124 W A Sprite 1 pointer (high 3 bits)
|
190 |
|
|
SPR1PTL + 126 W A Sprite 1 pointer (low 15 bits)
|
191 |
|
|
SPR1POS % 148 W AD Sprite 1 vert-horiz start position data
|
192 |
|
|
SPR1CTL % 14A W AD Sprite 1 vert stop position and control data
|
193 |
|
|
SPR1DATA % 14C W D Sprite 1 image data register A
|
194 |
|
|
SPR1DATB % 14E W D Sprite 1 image data register B
|
195 |
|
|
SPR2PTH + 128 W A Sprite 2 pointer (high 3 bits)
|
196 |
|
|
SPR2PTL + 12A W A Sprite 2 pointer (low 15 bits)
|
197 |
|
|
SPR2POS % 150 W AD Sprite 2 vert-horiz start position data
|
198 |
|
|
SPR2CTL % 152 W AD Sprite 2 vert stop position and control data
|
199 |
|
|
SPR2DATA % 154 W D Sprite 2 image data register A
|
200 |
|
|
SPR2DATB % 156 W D Sprite 2 image data register B
|
201 |
|
|
SPR3PTH + 12C W A Sprite 3 pointer (high 3 bits)
|
202 |
|
|
SPR3PTL + 12E W A Sprite 3 pointer (low 15 bits)
|
203 |
|
|
SPR3POS % 158 W AD Sprite 3 vert-horiz start position data
|
204 |
|
|
SPR3CTL % 15A W AD Sprite 3 vert stop position and control data
|
205 |
|
|
SPR3DATA % 15C W D Sprite 3 image data register A
|
206 |
|
|
SPR3DATB % 15E W D Sprite 3 image data register B
|
207 |
|
|
SPR4PTH + 130 W A Sprite 4 pointer (high 3 bits)
|
208 |
|
|
SPR4PTL + 132 W A Sprite 4 pointer (low 15 bits)
|
209 |
|
|
SPR4POS % 160 W AD Sprite 4 vert-horiz start position data
|
210 |
|
|
SPR4CTL % 162 W AD Sprite 4 vert stop position and control data
|
211 |
|
|
SPR4DATA % 164 W D Sprite 4 image data register A
|
212 |
|
|
SPR4DATB % 166 W D Sprite 4 image data register B
|
213 |
|
|
SPR5PTH + 134 W A Sprite 5 pointer (high 3 bits)
|
214 |
|
|
SPR5PTL + 136 W A Sprite 5 pointer (low 15 bits)
|
215 |
|
|
SPR5POS % 168 W AD Sprite 5 vert-horiz start position data
|
216 |
|
|
SPR5CTL % 16A W AD Sprite 5 vert stop position and control data
|
217 |
|
|
SPR5DATA % 16C W D Sprite 5 image data register A
|
218 |
|
|
SPR5DATB % 16E W D Sprite 5 image data register B
|
219 |
|
|
SPR6PTH + 138 W A Sprite 6 pointer (high 3 bits)
|
220 |
|
|
SPR6PTL + 13A W A Sprite 6 pointer (low 15 bits)
|
221 |
|
|
SPR6POS % 170 W AD Sprite 6 vert-horiz start position data
|
222 |
|
|
SPR6CTL % 172 W AD Sprite 6 vert stop position and control data
|
223 |
|
|
SPR6DATA % 174 W D Sprite 6 image data register A
|
224 |
|
|
SPR6DATB % 176 W D Sprite 6 image data register B
|
225 |
|
|
SPR7PTH + 13C W A Sprite 7 pointer (high 3 bits)
|
226 |
|
|
SPR7PTL + 13E W A Sprite 7 pointer (low 15 bits)
|
227 |
|
|
SPR7POS % 178 W AD Sprite 7 vert-horiz start position data
|
228 |
|
|
SPR7CTL % 17A W AD Sprite 7 vert stop position and control data
|
229 |
|
|
SPR7DATA % 17C W D Sprite 7 image data register A
|
230 |
|
|
SPR7DATB % 17E W D Sprite 7 image data register B
|
231 |
|
|
|
232 |
|
|
COLOR00 180 W D Color table 00
|
233 |
|
|
COLOR01 182 W D Color table 01
|
234 |
|
|
COLOR02 184 W D Color table 02
|
235 |
|
|
COLOR03 186 W D Color table 03
|
236 |
|
|
COLOR04 188 W D Color table 04
|
237 |
|
|
COLOR05 18A W D Color table 05
|
238 |
|
|
COLOR06 18C W D Color table 06
|
239 |
|
|
COLOR07 18E W D Color table 07
|
240 |
|
|
COLOR08 190 W D Color table 08
|
241 |
|
|
COLOR09 192 W D Color table 09
|
242 |
|
|
COLOR10 194 W D Color table 10
|
243 |
|
|
COLOR11 196 W D Color table 11
|
244 |
|
|
COLOR12 198 W D Color table 12
|
245 |
|
|
COLOR13 19A W D Color table 13
|
246 |
|
|
COLOR14 19C W D Color table 14
|
247 |
|
|
COLOR15 19E W D Color table 15
|
248 |
|
|
COLOR16 1A0 W D Color table 16
|
249 |
|
|
COLOR17 1A2 W D Color table 17
|
250 |
|
|
COLOR18 1A4 W D Color table 18
|
251 |
|
|
COLOR19 1A6 W D Color table 19
|
252 |
|
|
COLOR20 1A8 W D Color table 20
|
253 |
|
|
COLOR21 1AA W D Color table 21
|
254 |
|
|
COLOR22 1AC W D Color table 22
|
255 |
|
|
COLOR23 1AE W D Color table 23
|
256 |
|
|
COLOR24 1B0 W D Color table 24
|
257 |
|
|
COLOR25 1B2 W D Color table 25
|
258 |
|
|
COLOR26 1B4 W D Color table 26
|
259 |
|
|
COLOR27 1B6 W D Color table 27
|
260 |
|
|
COLOR28 1B8 W D Color table 28
|
261 |
|
|
COLOR29 1BA W D Color table 29
|
262 |
|
|
COLOR30 1BC W D Color table 30
|
263 |
|
|
COLOR31 1BE W D Color table 31
|
264 |
|
|
</pre></div> <h1><a class="el" href="classocs__audio.html" title="OCS audio implementation with WISHBONE master and slave interface. ">ocs_audio</a></h1>
|
265 |
|
|
<p>OCS audio implementation with WISHBONE master and slave interface. </p>
|
266 |
|
|
<p>List of audio registers: </p>
|
267 |
|
|
<div class="fragment"><pre class="fragment">
|
268 |
|
|
Implemented:
|
269 |
|
|
AUD0LCH + 0A0 W A( E ) Audio channel 0 location (high 3 bits, 5 if ECS)
|
270 |
|
|
AUD0LCL + 0A2 W A Audio channel 0 location (low 15 bits) (horiz. position)
|
271 |
|
|
AUD0LEN 0A4 W P Audio channel 0 length
|
272 |
|
|
AUD0PER 0A6 W P( E ) Audio channel 0 period
|
273 |
|
|
AUD0VOL 0A8 W P Audio channel 0 volume
|
274 |
|
|
AUD0DAT & 0AA W P Audio channel 0 data
|
275 |
|
|
|
276 |
|
|
AUD1LCH + 0B0 W A Audio channel 1 location (high 3 bits)
|
277 |
|
|
AUD1LCL + 0B2 W A Audio channel 1 location (low 15 bits)
|
278 |
|
|
AUD1LEN 0B4 W P Audio channel 1 length
|
279 |
|
|
AUD1PER 0B6 W P Audio channel 1 period
|
280 |
|
|
AUD1VOL 0B8 W P Audio channel 1 volume
|
281 |
|
|
AUD1DAT & 0BA W P Audio channel 1 data
|
282 |
|
|
|
283 |
|
|
AUD2LCH + 0C0 W A Audio channel 2 location (high 3 bits)
|
284 |
|
|
AUD2LCL + 0C2 W A Audio channel 2 location (low 15 bits)
|
285 |
|
|
AUD2LEN 0C4 W P Audio channel 2 length
|
286 |
|
|
AUD2PER 0C6 W P Audio channel 2 period
|
287 |
|
|
AUD2VOL 0C8 W P Audio channel 2 volume
|
288 |
|
|
AUD2DAT & 0CA W P Audio channel 2 data
|
289 |
|
|
|
290 |
|
|
AUD3LCH + 0D0 W A Audio channel 3 location (high 3 bits)
|
291 |
|
|
AUD3LCL + 0D2 W A Audio channel 3 location (low 15 bits)
|
292 |
|
|
AUD3LEN 0D4 W P Audio channel 3 length
|
293 |
|
|
AUD3PER 0D6 W P Audio channel 3 period
|
294 |
|
|
AUD3VOL 0D8 W P Audio channel 3 volume
|
295 |
|
|
AUD3DAT & 0DA W P Audio channel 3 data
|
296 |
|
|
</pre></div> <h1><a class="el" href="classocs__input.html" title="OCS user input implementation with WISHBONE slave interface. ">ocs_input</a></h1>
|
297 |
|
|
<p>OCS user input implementation with WISHBONE slave interface. </p>
|
298 |
|
|
<p>List of user input registers: </p>
|
299 |
|
|
<div class="fragment"><pre class="fragment">
|
300 |
|
|
Implemented:
|
301 |
|
|
[DSKDATR & *008 ER P Disk data early read (dummy address) not implemented]
|
302 |
|
|
JOY0DAT *00A R D Joystick-mouse 0 data (vert,horiz) read implemented here
|
303 |
|
|
|
304 |
|
|
JOY1DAT *00C R D Joystick-mouse 1 data (vert,horiz) read implemented here
|
305 |
|
|
[CLXDAT *00E R D Collision data register (read and clear) read implemented here]
|
306 |
|
|
|
307 |
|
|
JOYTEST *036 W D Write to all four joystick-mouse counters at once
|
308 |
|
|
|
309 |
|
|
Not implemented:
|
310 |
|
|
[ADKCONR *010 R P Audio, disk control register read read not implemented here]
|
311 |
|
|
POT0DAT *012 R P( E ) Pot counter pair 0 data (vert,horiz) read not implemented here
|
312 |
|
|
|
313 |
|
|
POT1DAT *014 R P( E ) Pot counter pair 1 data (vert,horiz)
|
314 |
|
|
POTGOR *016 R P Pot port data read (formerly POTINP)
|
315 |
|
|
POTGO *034 W P Pot port data write and start
|
316 |
|
|
</pre></div> <h1><a class="el" href="classocs__floppy.html" title="OCS floppy implementation with WISHBONE master and slave interface. ">ocs_floppy</a></h1>
|
317 |
|
|
<p>OCS floppy implementation with WISHBONE master and slave interface. </p>
|
318 |
|
|
<p>List of floppy registers: </p>
|
319 |
|
|
<div class="fragment"><pre class="fragment">
|
320 |
|
|
Implemented:
|
321 |
|
|
[SERDATR *018 R P Serial port data and status read read not implemented here]
|
322 |
|
|
DSKBYTR *01A R P Disk data byte and status read read not implemented here
|
323 |
|
|
|
324 |
|
|
DSKPTH + *020 W A( E ) Disk pointer (high 3 bits, 5 bits if ECS)
|
325 |
|
|
DSKPTL + *022 W A Disk pointer (low 15 bits)
|
326 |
|
|
DSKLEN *024 W P Disk length
|
327 |
|
|
DSKDAT & *026 W P Disk DMA data write
|
328 |
|
|
|
329 |
|
|
[not used 07C]
|
330 |
|
|
DSKSYNC ~07E W P Disk sync pattern register for disk read
|
331 |
|
|
|
332 |
|
|
Not implemented:
|
333 |
|
|
DSKDATR & *008 ER P Disk data early read (dummy address) not implemented
|
334 |
|
|
[JOY0DAT *00A R D Joystick-mouse 0 data (vert,horiz) read not implemented here]
|
335 |
|
|
</pre></div> <h1><a class="el" href="classcia8520.html" title="Commodore 8520 Complex Interface Adapter implementation. ">cia8520</a></h1>
|
336 |
|
|
<p>Commodore 8520 Complex Interface Adapter implementation. </p>
|
337 |
|
|
<h1><a class="el" href="classdrv__vga.html" title="ADV7123 Video DAC driver for VGA output. ">drv_vga</a></h1>
|
338 |
|
|
<p>ADV7123 Video DAC driver for VGA output. </p>
|
339 |
|
|
<h1><a class="el" href="classbus__ssram.html" title="IS61LPS51236A pipelined SSRAM driver with WISHBONE slave interface. ">bus_ssram</a></h1>
|
340 |
|
|
<p>IS61LPS51236A pipelined SSRAM driver with WISHBONE slave interface. </p>
|
341 |
|
|
<h1><a class="el" href="classdrv__audio.html" title="WM8731 audio codec driver for stereo audio output. ">drv_audio</a></h1>
|
342 |
|
|
<p>WM8731 audio codec driver for stereo audio output. </p>
|
343 |
|
|
<h1><a class="el" href="classdrv__keyboard.html" title="PS/2 keyboard driver. ">drv_keyboard</a></h1>
|
344 |
|
|
<p>PS/2 keyboard driver. </p>
|
345 |
|
|
<h1><a class="el" href="classdrv__mouse.html" title="PS/2 mouse driver. ">drv_mouse</a></h1>
|
346 |
|
|
<p>PS/2 mouse driver. </p>
|
347 |
|
|
<h1><a class="el" href="classdrv__debug.html" title="Switches and hex leds driver for debug purposes. ">drv_debug</a></h1>
|
348 |
|
|
<p>Switches and hex leds driver for debug purposes. </p>
|
349 |
|
|
<h1><a class="el" href="classdrv__eth__vga__capture.html" title="DM9000A 10/100 Mbit Ethernet driver for a VGA frame grabber. ">drv_eth_vga_capture</a></h1>
|
350 |
|
|
<p>DM9000A 10/100 Mbit Ethernet driver for a VGA frame grabber. </p>
|
351 |
|
|
</div>
|
352 |
|
|
<hr class="footer"/><address class="footer"><small>Generated on Mon Dec 20 2010 21:20:19 for aoOCS by 
|
353 |
|
|
<a href="http://www.doxygen.org/index.html">
|
354 |
|
|
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.2 </small></address>
|
355 |
|
|
</body>
|
356 |
|
|
</html>
|