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/*
 * Copyright 2010, Aleksander Osman, alfik@poczta.fm. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without modification, are
 * permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright notice, this list of
 *     conditions and the following disclaimer.
 *
 *  2. Redistributions in binary form must reproduce the above copyright notice, this list
 *     of conditions and the following disclaimer in the documentation and/or other materials
 *     provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
 * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/*! \file
 * \brief On-Screen-Display and overall system management.
 */
 
/*! \brief \copybrief control_osd.v
*/
module control_osd(
    //% \name Clock and reset
    //% @{
    input               CLK_I,
        input               reset_n,
    output              reset_request,
    output reg          management_mode,
    //% @}
 
    //% \name WISHBONE master
    //% @{
    output reg          CYC_O,
    output reg          STB_O,
    output reg          WE_O,
    output reg [31:2]   ADR_O,
    output [3:0]        SEL_O,
    output reg [31:0]   master_DAT_O,
    input [31:0]        master_DAT_I,
    input               ACK_I,
    //% @}
 
    //% \name WISHBONE slave
    //% @{
    input [31:2]        ADR_I,
        input               CYC_I,
        input               WE_I,
        input               STB_I,
        input [3:0]         SEL_I,
        input [31:0]        slave_DAT_I,
        output [31:0]       slave_DAT_O,
        output reg          ACK_O,
        output              RTY_O,
        output              ERR_O,
    //% @}
 
    //% \name On-Screen-Display management interface
    //% @{
    input               request_osd,
    output reg          on_screen_display,
 
    input [4:0]         osd_line,
    input [4:0]         osd_column,
    output [7:0]        character,
 
        output reg          joystick_enable,
        input               keyboard_select,
        input               keyboard_up,
        input               keyboard_down,
        //% @}
 
        //% \name On-Screen-Display floppy management interface
    //% @{
        output              floppy_inserted,
    output reg [31:0]   floppy_sector,
    output reg          floppy_write_enabled,
    input               floppy_error
    //% @}
);
 
assign ERR_O = 1'b0;
assign RTY_O = 1'b0;
assign SEL_O = 4'b1111;
 
//****************** Display memory
wire [31:0] char;
wire [31:0] display_q;
assign slave_DAT_O = ({ADR_I, 2'b00} >= 32'h10000000 && {ADR_I, 2'b00} <= 32'h10000FFF)? display_q : 32'd0;
 
altsyncram display_ram_inst(
    .clock0(CLK_I),
    .clock1(CLK_I),
    .address_a(ADR_I[11:2]),
    .wren_a(CYC_I == 1'b1 && STB_I == 1'b1 && WE_I == 1'b1 && {ADR_I, 2'b00} >= 32'h10000000 && {ADR_I, 2'b00} <= 32'h10000FFF),
    .data_a(slave_DAT_I),
    .byteena_a(SEL_I),
    .q_a(display_q),
    .address_b(char_addr[11:2]),
    .q_b(char)
);
defparam display_ram_inst.operation_mode = "BIDIR_DUAL_PORT";
defparam display_ram_inst.width_a = 32;
defparam display_ram_inst.widthad_a = 10;
defparam display_ram_inst.width_byteena_a = 4;
defparam display_ram_inst.width_b = 32;
defparam display_ram_inst.widthad_b = 10;
defparam display_ram_inst.init_file = "control_osd.mif";
 
wire [7:0] final_char;
assign final_char =
    (char_addr[1:0] == 2'd0)? char[31:24] :
    (char_addr[1:0] == 2'd1)? char[23:16] :
    (char_addr[1:0] == 2'd2)? char[15:8] :
    char[7:0];
 
assign character = (osd_line == 5'd9 && final_char != 8'd0)? {1'b1, final_char[6:0]} : final_char;
 
//***************** Control
reg [7:0] pointer;
reg [7:0] selected_floppy_pointer;
 
reg [31:0] value_a;
reg [31:0] value_b;
 
reg [1:0] value_counter;
reg [4:0] last_osd_column;
 
reg last_keyboard_up;
reg last_keyboard_down;
reg last_keyboard_select;
reg last_request_osd;
 
reg [22:0] keyboard_counter;
reg keyboard_repeating;
wire keyboard_repeat;
assign keyboard_repeat = (keyboard_repeating == 1'b0 && keyboard_counter == 23'd6000000) || (keyboard_repeating == 1'b1 && keyboard_counter == 23'd1000000);
 
wire [12:0] current_addr;
assign current_addr = {3'b0, osd_line, 5'b0} - 13'd64 + { pointer, 5'b0 };
wire [12:0] selected_floppy_addr;
assign selected_floppy_addr = { 3'b0, 5'd9, 5'b0 } - 13'd64 + { selected_floppy_pointer, 5'b0 };
 
wire [11:0] char_addr;
assign char_addr =
    ((value_counter == 2'd1)?   5'd24 :
     (value_counter > 2'd1)?    5'd28 :
     (osd_column == 5'd31)?     12'd0 : osd_column + 5'd1
    ) +
    ((osd_line == 5'd0 && state != S_ON_SCREEN_DISPLAY)?    12'd0 :
     (osd_line == 5'd0 && state == S_ON_SCREEN_DISPLAY)?    12'd160 :
 
     (osd_line == 5'd1 && state == S_SD_CHECK_INIT)?        12'd32 :
     (osd_line == 5'd1 && state == S_SD_ERROR)?             12'd64 :
     (osd_line == 5'd1 && state == S_SELECT_ROM)?           12'd96 :
     (osd_line == 5'd1 && state == S_ON_SCREEN_DISPLAY && floppy_inserted == 1'd0)?
                                                            12'd192 :
     (osd_line == 5'd1 && state == S_ON_SCREEN_DISPLAY)?    selected_floppy_addr[11:0] - 12'd96 + 12'd1024 :
 
     (osd_line == 5'd9 && state == S_SD_ERROR)?             12'd352 :
     (state == S_SD_ERROR)?                                 12'd128 :
 
     (current_addr[12] == 1'b1)?                            12'd128 :
     (state == S_SELECT_ROM)?                               current_addr[11:0] + 12'd512 :
 
     (state != S_ON_SCREEN_DISPLAY)?                        12'd128 :
 
     (current_addr[11:0] == 12'd0 && joystick_enable == 1'b0)?
                                                            12'd224 :
     (current_addr[11:0] == 12'd0 && joystick_enable == 1'b1)?
                                                            12'd256 :
 
     (current_addr[11:0] == 12'd32 && floppy_write_enabled == 1'b0)?
                                                            12'd288 :
     (current_addr[11:0] == 12'd32 && floppy_write_enabled == 1'b1)?
                                                            12'd320 :
 
     (current_addr[11:0] == 12'd64)?                        12'd352 :
 
     (current_addr[11:0] == 12'd96 && floppy_inserted == 1'd1)?
                                                            12'd384 :
 
     (floppy_inserted == 13'd0)?                            current_addr[11:0] - 12'd96 + 12'd1024 :
 
                                                            12'd128
 
    );
 
assign floppy_inserted = (floppy_sector != 32'd0);
assign reset_request = {last_keyboard_select == 1'b0 && keyboard_select == 1'b1 && value_a[3] == 1'b1};
 
reg [3:0] state;
parameter [3:0]
    S_SD_CHECK_INIT     = 4'd0,
    S_SD_ERROR          = 4'd1,
    S_READ_INTRO        = 4'd2,
    S_READ_INTRO_WAIT   = 4'd3,
    S_READ_HEADER       = 4'd4,
    S_READ_HEADER_WAIT  = 4'd5,
    S_SELECT_ROM        = 4'd6,
    S_COPY_ROM          = 4'd7,
    S_RUNNING           = 4'd8,
    S_ON_SCREEN_DISPLAY = 4'd9;
 
reg [1:0] substate;
 
always @(posedge CLK_I or negedge reset_n) begin
    if(reset_n == 1'b0) begin
        CYC_O <= 1'b0;
        STB_O <= 1'b0;
        ADR_O <= 30'd0;
        WE_O <= 1'b0;
        master_DAT_O <= 32'd0;
 
        ACK_O <= 1'b0;
 
        management_mode <= 1'b1;
        pointer <= -8'd7;
        selected_floppy_pointer <= -8'd5;
 
        value_a <= 32'd0;
        value_b <= 32'd0;
        value_counter <= 2'd0;
        last_osd_column <= 5'd0;
 
        last_keyboard_up <= 1'b0;
        last_keyboard_down <= 1'b0;
        last_keyboard_select <= 1'b0;
        last_request_osd <= 1'b0;
 
        on_screen_display       <= 1'b1;
        joystick_enable         <= 1'b0;
        floppy_sector           <= 32'd0;
        floppy_write_enabled    <= 1'b0;
 
        keyboard_counter <= 23'd0;
        keyboard_repeating <= 1'b0;
 
        substate <= 2'd0;
        state <= S_SD_CHECK_INIT;
    end
    else begin
        if(CYC_I == 1'b1 && STB_I == 1'b1 && ACK_O == 1'b0) ACK_O <= 1'b1;
        else                                                ACK_O <= 1'b0;
 
 
        last_osd_column         <= osd_column;
        last_keyboard_up        <= keyboard_up;
        last_keyboard_down      <= keyboard_down;
        last_keyboard_select    <= keyboard_select;
        last_request_osd        <= request_osd;
 
        if(osd_column == 5'd31 && last_osd_column != 5'd31) value_counter <= 2'd1;
        else if(value_counter != 2'd0)                      value_counter <= value_counter + 2'd1;
 
        if(osd_line == 5'd9 && value_counter == 2'd2) value_a <= char;
        if(osd_line == 5'd9 && value_counter == 2'd3) value_b <= char;
 
        if(keyboard_up == 1'b0 && keyboard_down == 1'b0)    keyboard_repeating <= 1'b0;
        else if(keyboard_repeat == 1'b1)                    keyboard_repeating <= 1'b1;
 
        if((keyboard_up == 1'b1 || keyboard_down == 1'b1) && keyboard_repeat == 1'b0)   keyboard_counter <= keyboard_counter + 21'd1;
        else                                                                            keyboard_counter <= 21'd0;
 
        if(keyboard_up == 1'b1 && (last_keyboard_up == 1'b0 || keyboard_repeat == 1'b1) && value_a[0] == 1'b1 && value_a[1] == 1'b0)
            pointer <= pointer - 8'd1;
        else if(keyboard_down == 1'b1 && (last_keyboard_down == 1'b0 || keyboard_repeat == 1'b1) && value_a[0] == 1'b1 && value_a[2] == 1'b0)
            pointer <= pointer + 8'd1;
        else if(state == S_ON_SCREEN_DISPLAY && last_keyboard_select == 1'b0 && keyboard_select == 1'b1 && value_a[5] == 1'b1 && floppy_inserted == 13'd1)
            pointer <= selected_floppy_pointer;
        else if(state == S_ON_SCREEN_DISPLAY && last_keyboard_select == 1'b0 && keyboard_select == 1'b1 && value_a[5] == 1'b1 && floppy_inserted == 13'd0)
            pointer <= -8'd4;
 
        if(floppy_error == 1'b1) begin
            CYC_O <= 1'b0;
            STB_O <= 1'b0;
 
            on_screen_display <= 1'b1;
            state <= S_SD_ERROR;
        end
        else if(state == S_SD_CHECK_INIT) begin
            if(ACK_I == 1'b1 && CYC_O == 1'b1 && STB_O == 1'b1) begin
                CYC_O <= 1'b0;
                STB_O <= 1'b0;
 
                if(master_DAT_I == 32'd2) begin
                    ADR_O <= 30'h4000400; // 0x10001000, base write address
                    substate <= 2'd0;
                    state <= S_READ_INTRO;
                end
                else if(master_DAT_I == 32'd1) begin
                    state <= S_SD_ERROR;
                end
            end
            else if(ACK_I == 1'b0) begin
                CYC_O <= 1'b1;
                STB_O <= 1'b1;
                WE_O <= 1'b0;
                ADR_O <= 30'h4000400; // 0x10001000, read state
            end
        end
 
        else if(state == S_READ_INTRO) begin
            if(ACK_I == 1'b1 && CYC_O == 1'b1 && STB_O == 1'b1) begin
                CYC_O <= 1'b0;
                STB_O <= 1'b0;
 
                if(substate < 2'd3) begin
                    substate <= substate + 2'd1;
                    ADR_O <= ADR_O + 30'd1;
                end
                else begin
                    substate <= 2'd0;
                    state <= S_READ_INTRO_WAIT;
                end
            end
            else if(ACK_I == 1'b0) begin
                CYC_O <= 1'b1;
                STB_O <= 1'b1;
                WE_O <= 1'b1;
                //ADR_O <= ADR_O;
 
                master_DAT_O <=
                    (substate == 2'd0)? 32'h10180000 :  // base address, 0x10000000
                    (substate == 2'd1)? 32'd0 :         // sd sector number
                    (substate == 2'd2)? 32'd432 :       // read sector size
                    32'd2;                              // start sd read
            end
        end
        else if(state == S_READ_INTRO_WAIT) begin
            if(ACK_I == 1'b1 && CYC_O == 1'b1 && STB_O == 1'b1) begin
                CYC_O <= 1'b0;
                STB_O <= 1'b0;
 
                if(master_DAT_I == 32'd2) begin
                    ADR_O <= 30'h4000400; // 0x10001000, base write address
                    substate <= 2'd0;
                    state <= S_READ_HEADER;
                end
                else if(master_DAT_I == 32'd5) begin
                    state <= S_SD_ERROR;
                end
            end
            else if(ACK_I == 1'b0) begin
                CYC_O <= 1'b1;
                STB_O <= 1'b1;
                WE_O <= 1'b0;
                ADR_O <= 30'h4000400; // 0x10001000, read state
            end
        end
 
        else if(state == S_READ_HEADER) begin
            if(ACK_I == 1'b1 && CYC_O == 1'b1 && STB_O == 1'b1) begin
                CYC_O <= 1'b0;
                STB_O <= 1'b0;
 
                if(substate < 2'd3) begin
                    substate <= substate + 2'd1;
                    ADR_O <= ADR_O + 30'd1;
                end
                else begin
                    substate <= 2'd0;
                    state <= S_READ_HEADER_WAIT;
                end
            end
            else if(ACK_I == 1'b0) begin
                CYC_O <= 1'b1;
                STB_O <= 1'b1;
                WE_O <= 1'b1;
                //ADR_O <= ADR_O;
 
                master_DAT_O <=
                    (substate == 2'd0)? 32'h10000200 :  // base address, 0x10000000
                    (substate == 2'd1)? 32'd432 :       // sd sector number
                    (substate == 2'd2)? 32'd8 :         // read sector size
                    32'd2;                              // start sd read
            end
        end
        else if(state == S_READ_HEADER_WAIT) begin
            if(ACK_I == 1'b1 && CYC_O == 1'b1 && STB_O == 1'b1) begin
                CYC_O <= 1'b0;
                STB_O <= 1'b0;
 
                if(master_DAT_I == 32'd2) begin
                    ADR_O <= 30'h4000400; // 0x10001000, base write address
                    substate <= 2'd0;
                    state <= S_SELECT_ROM;
                end
                else if(master_DAT_I == 32'd5) begin
                    state <= S_SD_ERROR;
                end
            end
            else if(ACK_I == 1'b0) begin
                CYC_O <= 1'b1;
                STB_O <= 1'b1;
                WE_O <= 1'b0;
                ADR_O <= 30'h4000400; // 0x10001000, read state
            end
        end
        else if(state == S_SELECT_ROM && keyboard_select == 1'b1 && value_a != 32'd0) begin
            if(ACK_I == 1'b1 && CYC_O == 1'b1 && STB_O == 1'b1) begin
                CYC_O <= 1'b0;
                STB_O <= 1'b0;
 
                if(substate < 2'd3) begin
                    substate <= substate + 2'd1;
                    ADR_O <= ADR_O + 30'd1;
                end
                else begin
                    substate <= 2'd0;
                    state <= S_COPY_ROM;
                end
            end
            else if(ACK_I == 1'b0) begin
                CYC_O <= 1'b1;
                STB_O <= 1'b1;
                WE_O <= 1'b1;
                //ADR_O <= ADR_O;
 
                master_DAT_O <=
                    (substate == 2'd0)? 32'h001C0000 :  // base address, 0x00FC0000
                    (substate == 2'd1)? value_b :       // sd sector number
                    (substate == 2'd2)? 32'd512 :       // read sector size
                    32'd2;                              // start sd read
            end
        end
        else if(state == S_COPY_ROM) begin
            if(ACK_I == 1'b1 && CYC_O == 1'b1 && STB_O == 1'b1) begin
                CYC_O <= 1'b0;
                STB_O <= 1'b0;
 
                if(master_DAT_I == 32'd2) begin
                    substate <= 2'd0;
                    management_mode <= 1'b0;
                    on_screen_display <= 1'b0;
                    state <= S_RUNNING;
                end
                else if(master_DAT_I == 32'd5) begin
                    state <= S_SD_ERROR;
                end
            end
            else if(ACK_I == 1'b0) begin
                CYC_O <= 1'b1;
                STB_O <= 1'b1;
                WE_O <= 1'b0;
                ADR_O <= 30'h4000400; // 0x10001000, read state
            end
        end
        else if(state == S_RUNNING && last_request_osd == 1'b0 && request_osd == 1'b1) begin
            on_screen_display <= 1'b1;
            state <= S_ON_SCREEN_DISPLAY;
        end
        else if(state == S_ON_SCREEN_DISPLAY && last_request_osd == 1'b0 && request_osd == 1'b1) begin
            on_screen_display <= 1'b0;
            state <= S_RUNNING;
        end
        else if(state == S_ON_SCREEN_DISPLAY && last_keyboard_select == 1'b0 && keyboard_select == 1'b1 && value_a[4] == 1'b1) begin
            joystick_enable <= ~joystick_enable;
        end
        else if(state == S_ON_SCREEN_DISPLAY && last_keyboard_select == 1'b0 && keyboard_select == 1'b1 && value_a[6] == 1'b1) begin
            floppy_write_enabled <= ~floppy_write_enabled;
        end
        else if(state == S_ON_SCREEN_DISPLAY && last_keyboard_select == 1'b0 && keyboard_select == 1'b1 && value_a[5] == 1'b1) begin
            if(floppy_inserted == 13'd1) begin
                floppy_sector <= 32'd0;
            end
            else begin
                floppy_sector <= value_b;
                selected_floppy_pointer <= pointer;
            end
        end
    end
end
 
endmodule
 

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[/] [aoocs/] [trunk/] [rtl/] [control_osd.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	alfik	`/*`
2			`* Copyright 2010, Aleksander Osman, alfik@poczta.fm. All rights reserved.`
3			`*`
4			`* Redistribution and use in source and binary forms, with or without modification, are`
5			`* permitted provided that the following conditions are met:`
6			`*`
7			`* 1. Redistributions of source code must retain the above copyright notice, this list of`
8			`* conditions and the following disclaimer.`
9			`*`
10			`* 2. Redistributions in binary form must reproduce the above copyright notice, this list`
11			`* of conditions and the following disclaimer in the documentation and/or other materials`
12			`* provided with the distribution.`
13			`*`
14			* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
15			`* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND`
16			`* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR`
17			`* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR`
18			`* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR`
19			`* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON`
20			`* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING`
21			`* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF`
22			`* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.`
23			`*/`
24
25			`/*! \file`
26			`* \brief On-Screen-Display and overall system management.`
27			`*/`
28
29			`/*! \brief \copybrief control_osd.v`
30			`*/`
31			`module control_osd(`
32			`//% \name Clock and reset`
33			`//% @{`
34			`input CLK_I,`
35			`input reset_n,`
36			`output reset_request,`
37			`output reg management_mode,`
38			`//% @}`
39
40			`//% \name WISHBONE master`
41			`//% @{`
42			`output reg CYC_O,`
43			`output reg STB_O,`
44			`output reg WE_O,`
45			`output reg [31:2] ADR_O,`
46			`output [3:0] SEL_O,`
47			`output reg [31:0] master_DAT_O,`
48			`input [31:0] master_DAT_I,`
49			`input ACK_I,`
50			`//% @}`
51
52			`//% \name WISHBONE slave`
53			`//% @{`
54			`input [31:2] ADR_I,`
55			`input CYC_I,`
56			`input WE_I,`
57			`input STB_I,`
58			`input [3:0] SEL_I,`
59			`input [31:0] slave_DAT_I,`
60			`output [31:0] slave_DAT_O,`
61			`output reg ACK_O,`
62			`output RTY_O,`
63			`output ERR_O,`
64			`//% @}`
65
66			`//% \name On-Screen-Display management interface`
67			`//% @{`
68			`input request_osd,`
69			`output reg on_screen_display,`
70
71			`input [4:0] osd_line,`
72			`input [4:0] osd_column,`
73			`output [7:0] character,`
74
75			`output reg joystick_enable,`
76			`input keyboard_select,`
77			`input keyboard_up,`
78			`input keyboard_down,`
79			`//% @}`
80
81			`//% \name On-Screen-Display floppy management interface`
82			`//% @{`
83			`output floppy_inserted,`
84			`output reg [31:0] floppy_sector,`
85			`output reg floppy_write_enabled,`
86			`input floppy_error`
87			`//% @}`
88			`);`
89
90			`assign ERR_O = 1'b0;`
91			`assign RTY_O = 1'b0;`
92			`assign SEL_O = 4'b1111;`
93
94			`//****************** Display memory`
95			`wire [31:0] char;`
96			`wire [31:0] display_q;`
97			`assign slave_DAT_O = ({ADR_I, 2'b00} >= 32'h10000000 && {ADR_I, 2'b00} <= 32'h10000FFF)? display_q : 32'd0;`
98
99			`altsyncram display_ram_inst(`
100			`.clock0(CLK_I),`
101			`.clock1(CLK_I),`
102			`.address_a(ADR_I[11:2]),`
103			`.wren_a(CYC_I == 1'b1 && STB_I == 1'b1 && WE_I == 1'b1 && {ADR_I, 2'b00} >= 32'h10000000 && {ADR_I, 2'b00} <= 32'h10000FFF),`
104			`.data_a(slave_DAT_I),`
105			`.byteena_a(SEL_I),`
106			`.q_a(display_q),`
107			`.address_b(char_addr[11:2]),`
108			`.q_b(char)`
109			`);`
110			`defparam display_ram_inst.operation_mode = "BIDIR_DUAL_PORT";`
111			`defparam display_ram_inst.width_a = 32;`
112			`defparam display_ram_inst.widthad_a = 10;`
113			`defparam display_ram_inst.width_byteena_a = 4;`
114			`defparam display_ram_inst.width_b = 32;`
115			`defparam display_ram_inst.widthad_b = 10;`
116			`defparam display_ram_inst.init_file = "control_osd.mif";`
117
118			`wire [7:0] final_char;`
119			`assign final_char =`
120			`(char_addr[1:0] == 2'd0)? char[31:24] :`
121			`(char_addr[1:0] == 2'd1)? char[23:16] :`
122			`(char_addr[1:0] == 2'd2)? char[15:8] :`
123			`char[7:0];`
124
125			`assign character = (osd_line == 5'd9 && final_char != 8'd0)? {1'b1, final_char[6:0]} : final_char;`
126
127			`//***************** Control`
128			`reg [7:0] pointer;`
129			`reg [7:0] selected_floppy_pointer;`
130
131			`reg [31:0] value_a;`
132			`reg [31:0] value_b;`
133
134			`reg [1:0] value_counter;`
135			`reg [4:0] last_osd_column;`
136
137			`reg last_keyboard_up;`
138			`reg last_keyboard_down;`
139			`reg last_keyboard_select;`
140			`reg last_request_osd;`
141
142			`reg [22:0] keyboard_counter;`
143			`reg keyboard_repeating;`
144			`wire keyboard_repeat;`
145			`assign keyboard_repeat = (keyboard_repeating == 1'b0 && keyboard_counter == 23'd6000000) \|\| (keyboard_repeating == 1'b1 && keyboard_counter == 23'd1000000);`
146
147			`wire [12:0] current_addr;`
148			`assign current_addr = {3'b0, osd_line, 5'b0} - 13'd64 + { pointer, 5'b0 };`
149			`wire [12:0] selected_floppy_addr;`
150			`assign selected_floppy_addr = { 3'b0, 5'd9, 5'b0 } - 13'd64 + { selected_floppy_pointer, 5'b0 };`
151
152			`wire [11:0] char_addr;`
153			`assign char_addr =`
154			`((value_counter == 2'd1)? 5'd24 :`
155			`(value_counter > 2'd1)? 5'd28 :`
156			`(osd_column == 5'd31)? 12'd0 : osd_column + 5'd1`
157			`) +`
158			`((osd_line == 5'd0 && state != S_ON_SCREEN_DISPLAY)? 12'd0 :`
159			`(osd_line == 5'd0 && state == S_ON_SCREEN_DISPLAY)? 12'd160 :`
160
161			`(osd_line == 5'd1 && state == S_SD_CHECK_INIT)? 12'd32 :`
162			`(osd_line == 5'd1 && state == S_SD_ERROR)? 12'd64 :`
163			`(osd_line == 5'd1 && state == S_SELECT_ROM)? 12'd96 :`
164			`(osd_line == 5'd1 && state == S_ON_SCREEN_DISPLAY && floppy_inserted == 1'd0)?`
165			`12'd192 :`
166			`(osd_line == 5'd1 && state == S_ON_SCREEN_DISPLAY)? selected_floppy_addr[11:0] - 12'd96 + 12'd1024 :`
167
168			`(osd_line == 5'd9 && state == S_SD_ERROR)? 12'd352 :`
169			`(state == S_SD_ERROR)? 12'd128 :`
170
171			`(current_addr[12] == 1'b1)? 12'd128 :`
172			`(state == S_SELECT_ROM)? current_addr[11:0] + 12'd512 :`
173
174			`(state != S_ON_SCREEN_DISPLAY)? 12'd128 :`
175
176			`(current_addr[11:0] == 12'd0 && joystick_enable == 1'b0)?`
177			`12'd224 :`
178			`(current_addr[11:0] == 12'd0 && joystick_enable == 1'b1)?`
179			`12'd256 :`
180
181			`(current_addr[11:0] == 12'd32 && floppy_write_enabled == 1'b0)?`
182			`12'd288 :`
183			`(current_addr[11:0] == 12'd32 && floppy_write_enabled == 1'b1)?`
184			`12'd320 :`
185
186			`(current_addr[11:0] == 12'd64)? 12'd352 :`
187
188			`(current_addr[11:0] == 12'd96 && floppy_inserted == 1'd1)?`
189			`12'd384 :`
190
191			`(floppy_inserted == 13'd0)? current_addr[11:0] - 12'd96 + 12'd1024 :`
192
193			`12'd128`
194
195			`);`
196
197			`assign floppy_inserted = (floppy_sector != 32'd0);`
198			`assign reset_request = {last_keyboard_select == 1'b0 && keyboard_select == 1'b1 && value_a[3] == 1'b1};`
199
200			`reg [3:0] state;`
201			`parameter [3:0]`
202			`S_SD_CHECK_INIT = 4'd0,`
203			`S_SD_ERROR = 4'd1,`
204			`S_READ_INTRO = 4'd2,`
205			`S_READ_INTRO_WAIT = 4'd3,`
206			`S_READ_HEADER = 4'd4,`
207			`S_READ_HEADER_WAIT = 4'd5,`
208			`S_SELECT_ROM = 4'd6,`
209			`S_COPY_ROM = 4'd7,`
210			`S_RUNNING = 4'd8,`
211			`S_ON_SCREEN_DISPLAY = 4'd9;`
212
213			`reg [1:0] substate;`
214
215			`always @(posedge CLK_I or negedge reset_n) begin`
216			`if(reset_n == 1'b0) begin`
217			`CYC_O <= 1'b0;`
218			`STB_O <= 1'b0;`
219			`ADR_O <= 30'd0;`
220			`WE_O <= 1'b0;`
221			`master_DAT_O <= 32'd0;`
222
223			`ACK_O <= 1'b0;`
224
225			`management_mode <= 1'b1;`
226			`pointer <= -8'd7;`
227			`selected_floppy_pointer <= -8'd5;`
228
229			`value_a <= 32'd0;`
230			`value_b <= 32'd0;`
231			`value_counter <= 2'd0;`
232			`last_osd_column <= 5'd0;`
233
234			`last_keyboard_up <= 1'b0;`
235			`last_keyboard_down <= 1'b0;`
236			`last_keyboard_select <= 1'b0;`
237			`last_request_osd <= 1'b0;`
238
239			`on_screen_display <= 1'b1;`
240			`joystick_enable <= 1'b0;`
241			`floppy_sector <= 32'd0;`
242			`floppy_write_enabled <= 1'b0;`
243
244			`keyboard_counter <= 23'd0;`
245			`keyboard_repeating <= 1'b0;`
246
247			`substate <= 2'd0;`
248			`state <= S_SD_CHECK_INIT;`
249			`end`
250			`else begin`
251			`if(CYC_I == 1'b1 && STB_I == 1'b1 && ACK_O == 1'b0) ACK_O <= 1'b1;`
252			`else ACK_O <= 1'b0;`
253
254
255			`last_osd_column <= osd_column;`
256			`last_keyboard_up <= keyboard_up;`
257			`last_keyboard_down <= keyboard_down;`
258			`last_keyboard_select <= keyboard_select;`
259			`last_request_osd <= request_osd;`
260
261			`if(osd_column == 5'd31 && last_osd_column != 5'd31) value_counter <= 2'd1;`
262			`else if(value_counter != 2'd0) value_counter <= value_counter + 2'd1;`
263
264			`if(osd_line == 5'd9 && value_counter == 2'd2) value_a <= char;`
265			`if(osd_line == 5'd9 && value_counter == 2'd3) value_b <= char;`
266
267			`if(keyboard_up == 1'b0 && keyboard_down == 1'b0) keyboard_repeating <= 1'b0;`
268			`else if(keyboard_repeat == 1'b1) keyboard_repeating <= 1'b1;`
269
270			`if((keyboard_up == 1'b1 \|\| keyboard_down == 1'b1) && keyboard_repeat == 1'b0) keyboard_counter <= keyboard_counter + 21'd1;`
271			`else keyboard_counter <= 21'd0;`
272
273			`if(keyboard_up == 1'b1 && (last_keyboard_up == 1'b0 \|\| keyboard_repeat == 1'b1) && value_a[0] == 1'b1 && value_a[1] == 1'b0)`
274			`pointer <= pointer - 8'd1;`
275			`else if(keyboard_down == 1'b1 && (last_keyboard_down == 1'b0 \|\| keyboard_repeat == 1'b1) && value_a[0] == 1'b1 && value_a[2] == 1'b0)`
276			`pointer <= pointer + 8'd1;`
277			`else if(state == S_ON_SCREEN_DISPLAY && last_keyboard_select == 1'b0 && keyboard_select == 1'b1 && value_a[5] == 1'b1 && floppy_inserted == 13'd1)`
278			`pointer <= selected_floppy_pointer;`
279			`else if(state == S_ON_SCREEN_DISPLAY && last_keyboard_select == 1'b0 && keyboard_select == 1'b1 && value_a[5] == 1'b1 && floppy_inserted == 13'd0)`
280			`pointer <= -8'd4;`
281
282			`if(floppy_error == 1'b1) begin`
283			`CYC_O <= 1'b0;`
284			`STB_O <= 1'b0;`
285
286			`on_screen_display <= 1'b1;`
287			`state <= S_SD_ERROR;`
288			`end`
289			`else if(state == S_SD_CHECK_INIT) begin`
290			`if(ACK_I == 1'b1 && CYC_O == 1'b1 && STB_O == 1'b1) begin`
291			`CYC_O <= 1'b0;`
292			`STB_O <= 1'b0;`
293
294			`if(master_DAT_I == 32'd2) begin`
295			`ADR_O <= 30'h4000400; // 0x10001000, base write address`
296			`substate <= 2'd0;`
297			`state <= S_READ_INTRO;`
298			`end`
299			`else if(master_DAT_I == 32'd1) begin`
300			`state <= S_SD_ERROR;`
301			`end`
302			`end`
303			`else if(ACK_I == 1'b0) begin`
304			`CYC_O <= 1'b1;`
305			`STB_O <= 1'b1;`
306			`WE_O <= 1'b0;`
307			`ADR_O <= 30'h4000400; // 0x10001000, read state`
308			`end`
309			`end`
310
311			`else if(state == S_READ_INTRO) begin`
312			`if(ACK_I == 1'b1 && CYC_O == 1'b1 && STB_O == 1'b1) begin`
313			`CYC_O <= 1'b0;`
314			`STB_O <= 1'b0;`
315
316			`if(substate < 2'd3) begin`
317			`substate <= substate + 2'd1;`
318			`ADR_O <= ADR_O + 30'd1;`
319			`end`
320			`else begin`
321			`substate <= 2'd0;`
322			`state <= S_READ_INTRO_WAIT;`
323			`end`
324			`end`
325			`else if(ACK_I == 1'b0) begin`
326			`CYC_O <= 1'b1;`
327			`STB_O <= 1'b1;`
328			`WE_O <= 1'b1;`
329			`//ADR_O <= ADR_O;`
330
331			`master_DAT_O <=`
332			`(substate == 2'd0)? 32'h10180000 : // base address, 0x10000000`
333			`(substate == 2'd1)? 32'd0 : // sd sector number`
334			`(substate == 2'd2)? 32'd432 : // read sector size`
335			`32'd2; // start sd read`
336			`end`
337			`end`
338			`else if(state == S_READ_INTRO_WAIT) begin`
339			`if(ACK_I == 1'b1 && CYC_O == 1'b1 && STB_O == 1'b1) begin`
340			`CYC_O <= 1'b0;`
341			`STB_O <= 1'b0;`
342
343			`if(master_DAT_I == 32'd2) begin`
344			`ADR_O <= 30'h4000400; // 0x10001000, base write address`
345			`substate <= 2'd0;`
346			`state <= S_READ_HEADER;`
347			`end`
348			`else if(master_DAT_I == 32'd5) begin`
349			`state <= S_SD_ERROR;`
350			`end`
351			`end`
352			`else if(ACK_I == 1'b0) begin`
353			`CYC_O <= 1'b1;`
354			`STB_O <= 1'b1;`
355			`WE_O <= 1'b0;`
356			`ADR_O <= 30'h4000400; // 0x10001000, read state`
357			`end`
358			`end`
359
360			`else if(state == S_READ_HEADER) begin`
361			`if(ACK_I == 1'b1 && CYC_O == 1'b1 && STB_O == 1'b1) begin`
362			`CYC_O <= 1'b0;`
363			`STB_O <= 1'b0;`
364
365			`if(substate < 2'd3) begin`
366			`substate <= substate + 2'd1;`
367			`ADR_O <= ADR_O + 30'd1;`
368			`end`
369			`else begin`
370			`substate <= 2'd0;`
371			`state <= S_READ_HEADER_WAIT;`
372			`end`
373			`end`
374			`else if(ACK_I == 1'b0) begin`
375			`CYC_O <= 1'b1;`
376			`STB_O <= 1'b1;`
377			`WE_O <= 1'b1;`
378			`//ADR_O <= ADR_O;`
379
380			`master_DAT_O <=`
381			`(substate == 2'd0)? 32'h10000200 : // base address, 0x10000000`
382			`(substate == 2'd1)? 32'd432 : // sd sector number`
383			`(substate == 2'd2)? 32'd8 : // read sector size`
384			`32'd2; // start sd read`
385			`end`
386			`end`
387			`else if(state == S_READ_HEADER_WAIT) begin`
388			`if(ACK_I == 1'b1 && CYC_O == 1'b1 && STB_O == 1'b1) begin`
389			`CYC_O <= 1'b0;`
390			`STB_O <= 1'b0;`
391
392			`if(master_DAT_I == 32'd2) begin`
393			`ADR_O <= 30'h4000400; // 0x10001000, base write address`
394			`substate <= 2'd0;`
395			`state <= S_SELECT_ROM;`
396			`end`
397			`else if(master_DAT_I == 32'd5) begin`
398			`state <= S_SD_ERROR;`
399			`end`
400			`end`
401			`else if(ACK_I == 1'b0) begin`
402			`CYC_O <= 1'b1;`
403			`STB_O <= 1'b1;`
404			`WE_O <= 1'b0;`
405			`ADR_O <= 30'h4000400; // 0x10001000, read state`
406			`end`
407			`end`
408			`else if(state == S_SELECT_ROM && keyboard_select == 1'b1 && value_a != 32'd0) begin`
409			`if(ACK_I == 1'b1 && CYC_O == 1'b1 && STB_O == 1'b1) begin`
410			`CYC_O <= 1'b0;`
411			`STB_O <= 1'b0;`
412
413			`if(substate < 2'd3) begin`
414			`substate <= substate + 2'd1;`
415			`ADR_O <= ADR_O + 30'd1;`
416			`end`
417			`else begin`
418			`substate <= 2'd0;`
419			`state <= S_COPY_ROM;`
420			`end`
421			`end`
422			`else if(ACK_I == 1'b0) begin`
423			`CYC_O <= 1'b1;`
424			`STB_O <= 1'b1;`
425			`WE_O <= 1'b1;`
426			`//ADR_O <= ADR_O;`
427
428			`master_DAT_O <=`
429			`(substate == 2'd0)? 32'h001C0000 : // base address, 0x00FC0000`
430			`(substate == 2'd1)? value_b : // sd sector number`
431			`(substate == 2'd2)? 32'd512 : // read sector size`
432			`32'd2; // start sd read`
433			`end`
434			`end`
435			`else if(state == S_COPY_ROM) begin`
436			`if(ACK_I == 1'b1 && CYC_O == 1'b1 && STB_O == 1'b1) begin`
437			`CYC_O <= 1'b0;`
438			`STB_O <= 1'b0;`
439
440			`if(master_DAT_I == 32'd2) begin`
441			`substate <= 2'd0;`
442			`management_mode <= 1'b0;`
443			`on_screen_display <= 1'b0;`
444			`state <= S_RUNNING;`
445			`end`
446			`else if(master_DAT_I == 32'd5) begin`
447			`state <= S_SD_ERROR;`
448			`end`
449			`end`
450			`else if(ACK_I == 1'b0) begin`
451			`CYC_O <= 1'b1;`
452			`STB_O <= 1'b1;`
453			`WE_O <= 1'b0;`
454			`ADR_O <= 30'h4000400; // 0x10001000, read state`
455			`end`
456			`end`
457			`else if(state == S_RUNNING && last_request_osd == 1'b0 && request_osd == 1'b1) begin`
458			`on_screen_display <= 1'b1;`
459			`state <= S_ON_SCREEN_DISPLAY;`
460			`end`
461			`else if(state == S_ON_SCREEN_DISPLAY && last_request_osd == 1'b0 && request_osd == 1'b1) begin`
462			`on_screen_display <= 1'b0;`
463			`state <= S_RUNNING;`
464			`end`
465			`else if(state == S_ON_SCREEN_DISPLAY && last_keyboard_select == 1'b0 && keyboard_select == 1'b1 && value_a[4] == 1'b1) begin`
466			`joystick_enable <= ~joystick_enable;`
467			`end`
468			`else if(state == S_ON_SCREEN_DISPLAY && last_keyboard_select == 1'b0 && keyboard_select == 1'b1 && value_a[6] == 1'b1) begin`
469			`floppy_write_enabled <= ~floppy_write_enabled;`
470			`end`
471			`else if(state == S_ON_SCREEN_DISPLAY && last_keyboard_select == 1'b0 && keyboard_select == 1'b1 && value_a[5] == 1'b1) begin`
472			`if(floppy_inserted == 13'd1) begin`
473			`floppy_sector <= 32'd0;`
474			`end`
475			`else begin`
476			`floppy_sector <= value_b;`
477			`selected_floppy_pointer <= pointer;`
478			`end`
479			`end`
480			`end`
481			`end`
482
483			`endmodule`
484