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/*
 * Copyright 2010, Aleksander Osman, alfik@poczta.fm. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without modification, are
 * permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright notice, this list of
 *     conditions and the following disclaimer.
 *
 *  2. Redistributions in binary form must reproduce the above copyright notice, this list
 *     of conditions and the following disclaimer in the documentation and/or other materials
 *     provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
 * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/*! \file
 * \brief OCS audio implementation with WISHBONE master and slave interface.
 */
 
/*! \brief \copybrief ocs_audio.v
 
List of audio registers:
\verbatim
Implemented:
    AUD0LCH   +  0A0  W   A( E )  Audio channel 0 location (high 3 bits, 5 if ECS)
    AUD0LCL   +  0A2  W   A       Audio channel 0 location (low 15 bits) (horiz. position)
    AUD0LEN      0A4  W   P       Audio channel 0 length
    AUD0PER      0A6  W   P( E )  Audio channel 0 period
    AUD0VOL      0A8  W   P       Audio channel 0 volume
    AUD0DAT   &  0AA  W   P       Audio channel 0 data
 
    AUD1LCH   +  0B0  W   A       Audio channel 1 location (high 3 bits)
    AUD1LCL   +  0B2  W   A       Audio channel 1 location (low 15 bits)
    AUD1LEN      0B4  W   P       Audio channel 1 length
    AUD1PER      0B6  W   P       Audio channel 1 period
    AUD1VOL      0B8  W   P       Audio channel 1 volume
    AUD1DAT   &  0BA  W   P       Audio channel 1 data
 
    AUD2LCH   +  0C0  W   A       Audio channel 2 location (high 3 bits)
    AUD2LCL   +  0C2  W   A       Audio channel 2 location (low 15 bits)
    AUD2LEN      0C4  W   P       Audio channel 2 length
    AUD2PER      0C6  W   P       Audio channel 2 period
    AUD2VOL      0C8  W   P       Audio channel 2 volume
    AUD2DAT   &  0CA  W   P       Audio channel 2 data
 
    AUD3LCH   +  0D0  W   A       Audio channel 3 location (high 3 bits)
    AUD3LCL   +  0D2  W   A       Audio channel 3 location (low 15 bits)
    AUD3LEN      0D4  W   P       Audio channel 3 length
    AUD3PER      0D6  W   P       Audio channel 3 period
    AUD3VOL      0D8  W   P       Audio channel 3 volume
    AUD3DAT   &  0DA  W   P       Audio channel 3 data
\endverbatim
*/
module ocs_audio(
    //% \name Clock and reset
    //% @{
    input           CLK_I,
    input           reset_n,
    //% @}
 
    //% \name WISHBONE master
    //% @{
    output reg      CYC_O,
    output reg      STB_O,
    output          WE_O,
    output [31:2]   ADR_O,
    output [3:0]    SEL_O,
    input [31:0]    master_DAT_I,
    input           ACK_I,
    //% @}
 
    //% \name WISHBONE slave
    //% @{
    input           CYC_I,
    input           STB_I,
    input           WE_I,
    input [8:2]     ADR_I,
    input [3:0]     SEL_I,
    input [31:0]    slave_DAT_I,
    output reg      ACK_O,
    //% @}
 
    //% \name Internal OCS ports
    //% @{
    input           pulse_color,
    input           line_start,
 
    input [10:0]    dma_con,
    input [14:0]    adk_con,
 
    output [3:0]    audio_irq,
    //% @}
 
    //% \name drv_audio interface
    //% @{
    output [5:0] volume0,
    output [5:0] volume1,
    output [5:0] volume2,
    output [5:0] volume3,
    output [7:0] sample0,
    output [7:0] sample1,
    output [7:0] sample2,
    output [7:0] sample3
    //% @}
);
 
assign WE_O = 1'b0;
assign SEL_O = 4'b1111;
 
assign volume0 = (adk_con[0] == 1'b1 || adk_con[4] == 1'b1) ? 6'd0 : (channel0_volume[6] == 1'b1) ? 6'b111111 : channel0_volume[5:0];
assign volume1 = (adk_con[1] == 1'b1 || adk_con[5] == 1'b1) ? 6'd0 : (channel1_volume[6] == 1'b1) ? 6'b111111 : channel1_volume[5:0];
assign volume2 = (adk_con[2] == 1'b1 || adk_con[6] == 1'b1) ? 6'd0 : (channel2_volume[6] == 1'b1) ? 6'b111111 : channel2_volume[5:0];
assign volume3 = (adk_con[3] == 1'b1 || adk_con[7] == 1'b1) ? 6'd0 : (channel3_volume[6] == 1'b1) ? 6'b111111 : channel3_volume[5:0];
 
wire [3:0] dma_reqs;
wire [1:0] selected_channel;
assign selected_channel =
    (dma_reqs[0] == 1'b1) ? 2'd0 :
    (dma_reqs[1] == 1'b1) ? 2'd1 :
    (dma_reqs[2] == 1'b1) ? 2'd2 :
    2'd3;
 
assign ADR_O =
    (selected_channel == 3'd0) ? dma_address0[31:2] :
    (selected_channel == 3'd1) ? dma_address1[31:2] :
    (selected_channel == 3'd2) ? dma_address2[31:2] :
    dma_address3[31:2];
 
wire dma_req;
assign dma_req = dma_reqs[0] | dma_reqs[1] | dma_reqs[2] | dma_reqs[3];
 
//*************** Channel 0
wire [6:0] channel0_volume;
wire [15:0] channel0_data;
wire [1:0] channel0_update;
wire [31:0] dma_address0;
 
wire write_ena_extern0;
assign write_ena_extern0 = (CYC_I == 1'b1 && STB_I == 1'b1 && WE_I == 1'b1 &&
    (  { ADR_I, 2'b0 } == 9'h0A0 || { ADR_I, 2'b0 } == 9'h0A4 || { ADR_I, 2'b0 } == 9'h0A8 ) );
wire write_ena0;
assign write_ena0 = write_ena_extern0;
 
wire [1:0] write_address0;
assign write_address0 =
    ({ ADR_I, 2'b0 } == 9'h0A0) ? 2'd0 :
    ({ ADR_I, 2'b0 } == 9'h0A4) ? 2'd1 :
    2'd2;
 
wire [31:0] write_data0;
assign write_data0 = slave_DAT_I;
 
wire [3:0] write_sel0;
assign write_sel0 = SEL_I;
 
sound_channel sound_channel_0(
    .CLK_I(CLK_I),
    .reset_n(reset_n),
 
    .pulse_color(pulse_color),
    .line_start(line_start),
 
    .dma_ena(dma_con[9] == 1'b1 && dma_con[0] == 1'b1),
    .dma_req(dma_reqs[0]),
    .dma_address(dma_address0),
    .dma_done(selected_channel == 2'd0 && ACK_I == 1'b1),
    .dma_data(master_DAT_I),
 
    .write_ena(write_ena0),
    .write_address(write_address0),
    .write_data(write_data0),
    .write_sel(write_sel0),
 
    .irq(audio_irq[0]),
 
    .volume(channel0_volume),
    .sample(sample0),
    .is_modulator_channel(adk_con[0] == 1'b1 || adk_con[4] == 1'b1),
    .data(channel0_data),
    .data_update(channel0_update)
);
 
 
//*************** Channel 1
wire [6:0] channel1_volume;
wire [15:0] channel1_data;
wire [1:0] channel1_update;
wire [31:0] dma_address1;
 
wire write_ena_extern1;
assign write_ena_extern1 = (CYC_I == 1'b1 && STB_I == 1'b1 && WE_I == 1'b1 &&
    (  { ADR_I, 2'b0 } == 9'h0B0 || { ADR_I, 2'b0 } == 9'h0B4 || { ADR_I, 2'b0 } == 9'h0B8) );
wire write_ena1;
assign write_ena1 = ((adk_con[0] == 1'b1 || adk_con[4] == 1'b1) && (channel0_update == 2'b10 || channel0_update == 2'b11)) || write_ena_extern1;
 
wire [1:0] write_address1;
assign write_address1 =
    write_ena_extern1 ? (
        ({ ADR_I, 2'b0 } == 9'h0B0) ? 2'd0 :
        ({ ADR_I, 2'b0 } == 9'h0B4) ? 2'd1 :
        2'd2
    ) :
    (adk_con[0] == 1'b1 && adk_con[4] == 1'b0) ? 2'd2 :
    (adk_con[0] == 1'b0 && adk_con[4] == 1'b1) ? 2'd1 :
    (channel0_update == 2'b10) ? 2'd2 :
    2'd1;
 
wire [3:0] write_sel1;
assign write_sel1 =
    write_ena_extern1 ? SEL_I :
    (adk_con[0] == 1'b1 && adk_con[4] == 1'b0) ? 4'b1100 :
    (adk_con[0] == 1'b0 && adk_con[4] == 1'b1) ? 4'b0011 :
    (channel0_update == 2'b10) ? 4'b1100 :
    4'b0011;
 
wire [31:0] write_data1;
assign write_data1 =
    write_ena_extern1 ? slave_DAT_I :
    channel0_data;
 
sound_channel sound_channel_1(
    .CLK_I(CLK_I),
    .reset_n(reset_n),
 
    .pulse_color(pulse_color),
    .line_start(line_start),
 
    .dma_ena(dma_con[9] == 1'b1 && dma_con[1] == 1'b1),
    .dma_req(dma_reqs[1]),
    .dma_address(dma_address1),
    .dma_done(selected_channel == 2'd1 && ACK_I == 1'b1),
    .dma_data(master_DAT_I),
 
    .write_ena(write_ena1),
    .write_address(write_address1),
    .write_data(write_data1),
    .write_sel(write_sel1),
 
    .irq(audio_irq[1]),
 
    .volume(channel1_volume),
    .sample(sample1),
    .is_modulator_channel(adk_con[1] == 1'b1 || adk_con[5] == 1'b1),
    .data(channel1_data),
    .data_update(channel1_update)
);
 
//*************** Channel 2
wire [6:0] channel2_volume;
wire [15:0] channel2_data;
wire [1:0] channel2_update;
wire [31:0] dma_address2;
wire [7:0] channel2_sample;
 
wire write_ena_extern2;
assign write_ena_extern2 = (CYC_I == 1'b1 && STB_I == 1'b1 && WE_I == 1'b1 &&
    (  { ADR_I, 2'b0 } == 9'h0C0 || { ADR_I, 2'b0 } == 9'h0C4 || { ADR_I, 2'b0 } == 9'h0C8) );
wire write_ena2;
assign write_ena2 = ((adk_con[1] == 1'b1 || adk_con[5] == 1'b1) && (channel1_update == 2'b10 || channel1_update == 2'b11)) || write_ena_extern2;
 
wire [1:0] write_address2;
assign write_address2 =
    write_ena_extern2 ? (
        ({ ADR_I, 2'b0 } == 9'h0C0) ? 2'd0 :
        ({ ADR_I, 2'b0 } == 9'h0C4) ? 2'd1 :
        2'd2
    ) :
    (adk_con[1] == 1'b1 && adk_con[5] == 1'b0) ? 2'd2 :
    (adk_con[1] == 1'b0 && adk_con[5] == 1'b1) ? 2'd1 :
    (channel1_update == 2'b10) ? 2'd2 :
    2'd1;
 
wire [3:0] write_sel2;
assign write_sel2 =
    write_ena_extern2 ? SEL_I :
    (adk_con[1] == 1'b1 && adk_con[5] == 1'b0) ? 4'b1100 :
    (adk_con[1] == 1'b0 && adk_con[5] == 1'b1) ? 4'b0011 :
    (channel1_update == 2'b10) ? 4'b1100 :
    4'b0011;
 
wire [31:0] write_data2;
assign write_data2 =
    write_ena_extern2 ? slave_DAT_I :
    channel1_data;
 
sound_channel sound_channel_2(
    .CLK_I(CLK_I),
    .reset_n(reset_n),
 
    .pulse_color(pulse_color),
    .line_start(line_start),
 
    .dma_ena(dma_con[9] == 1'b1 && dma_con[2] == 1'b1),
    .dma_req(dma_reqs[2]),
    .dma_address(dma_address2),
    .dma_done(selected_channel == 2'd2 && ACK_I == 1'b1),
    .dma_data(master_DAT_I),
 
    .write_ena(write_ena2),
    .write_address(write_address2),
    .write_data(write_data2),
    .write_sel(write_sel2),
 
    .irq(audio_irq[2]),
 
    .volume(channel2_volume),
    .sample(sample2),
    .is_modulator_channel(adk_con[2] == 1'b1 || adk_con[6] == 1'b1),
    .data(channel2_data),
    .data_update(channel2_update)
);
 
//****************** Channel 3
wire [6:0] channel3_volume;
wire [15:0] channel3_data;
wire [1:0] channel3_update;
wire [31:0] dma_address3;
 
wire write_ena_extern3;
assign write_ena_extern3 = (CYC_I == 1'b1 && STB_I == 1'b1 && WE_I == 1'b1 &&
    ( { ADR_I, 2'b0 } == 9'h0D0 || { ADR_I, 2'b0 } == 9'h0D4 || { ADR_I, 2'b0 } == 9'h0D8) );
wire write_ena3;
assign write_ena3 = ((adk_con[2] == 1'b1 || adk_con[6] == 1'b1) && (channel2_update == 2'b10 || channel2_update == 2'b11)) || write_ena_extern3;
 
wire [1:0] write_address3;
assign write_address3 =
    write_ena_extern3 ? (
        ({ ADR_I, 2'b0 } == 9'h0D0) ? 2'd0 :
        ({ ADR_I, 2'b0 } == 9'h0D4) ? 2'd1 :
        2'd2
    ) :
    (adk_con[2] == 1'b1 && adk_con[6] == 1'b0) ? 2'd2 :
    (adk_con[2] == 1'b0 && adk_con[6] == 1'b1) ? 2'd1 :
    (channel2_update == 2'b10) ? 2'd2 :
    2'd1;
 
wire [3:0] write_sel3;
assign write_sel3 =
    write_ena_extern3 ? SEL_I :
    (adk_con[2] == 1'b1 && adk_con[6] == 1'b0) ? 4'b1100 :
    (adk_con[2] == 1'b0 && adk_con[6] == 1'b1) ? 4'b0011 :
    (channel2_update == 2'b10) ? 4'b1100 :
    4'b0011;
 
wire [31:0] write_data3;
assign write_data3 =
    write_ena_extern3 ? slave_DAT_I :
    channel2_data;
 
sound_channel sound_channel_3(
    .CLK_I(CLK_I),
    .reset_n(reset_n),
 
    .pulse_color(pulse_color),
    .line_start(line_start),
 
    .dma_ena(dma_con[9] == 1'b1 && dma_con[3] == 1'b1),
    .dma_req(dma_reqs[3]),
    .dma_address(dma_address3),
    .dma_done(selected_channel == 2'd3 && ACK_I == 1'b1),
    .dma_data(master_DAT_I),
 
    .write_ena(write_ena3),
    .write_address(write_address3),
    .write_data(write_data3),
    .write_sel(write_sel3),
 
    .irq(audio_irq[3]),
 
    .volume(channel3_volume),
    .sample(sample3),
    .is_modulator_channel(adk_con[3] == 1'b1 || adk_con[7] == 1'b1),
    .data(channel3_data),
    .data_update(channel3_update)
);
 
always @(posedge CLK_I or negedge reset_n) begin
    if(reset_n == 1'b0) begin
        CYC_O <= 1'b0;
        STB_O <= 1'b0;
        ACK_O <= 1'b0;
    end
    else begin
        if(ACK_O == 1'b1) begin
            ACK_O <= 1'b0;
        end
        else if(write_ena_extern0 == 1'b1 || write_ena_extern1 == 1'b1 || write_ena_extern2 == 1'b1 || write_ena_extern3 == 1'b1 ||
            (CYC_I == 1'b1 && STB_I == 1'b1 && WE_I == 1'b0))
        begin
            ACK_O <= 1'b1;
        end
 
        if(CYC_O == 1'b0 && STB_O == 1'b0 && dma_req == 1'b1) begin
            CYC_O <= 1'b1;
            STB_O <= 1'b1;
        end
        else if(CYC_O == 1'b1 && STB_O == 1'b1 && ACK_I == 1'b1) begin
            CYC_O <= 1'b0;
            STB_O <= 1'b0;
        end
 
    end
end
 
endmodule
 
/*! \brief Single audio channel.
 */
module sound_channel(
    input               CLK_I,
    input               reset_n,
 
    // color pulse
    input               pulse_color,
    input               line_start,
 
    input               dma_ena,
    output reg          dma_req,
    output reg [31:0]   dma_address,
    input               dma_done,
    input [31:0]        dma_data,
 
    input               write_ena,
    // 0:   AUDxLCH,    AUDxLCL,
    // 1:   AUDxLEN,    AUDxPER,
    // 2:   AUDxVOL,    AUDxDAT,
    input [1:0]         write_address,
    input [31:0]        write_data,
    input [3:0]         write_sel,
 
    output reg          irq,
 
    // sound interface
    // 0-63,64 only
    output reg [6:0]    volume,
    output reg [7:0]    sample,
    input               is_modulator_channel,
    // volume[6:0]:  modulation
    // period[15:0]: modulation
    output reg [15:0]   data,
    // 2'b01: 8 bit sample update only
    // 2'b10: 8 bit sample and even word update
    // 2'b11: 8 bit sample and odd word update
    output reg [1:0]    data_update
);
 
reg [31:0] location;
reg [15:0] length;
reg [16:0] length_left;
reg [15:0] period;
reg [15:0] period_left;
reg even_word;
reg [15:0] data2;
reg [1:0] avail;
reg [1:0] state;
 
parameter [1:0]
    S_IDLE      = 2'd0,
    S_DIRECT    = 2'd1,
    S_DMA       = 2'd2;
 
always @(posedge CLK_I or negedge reset_n) begin
    if(reset_n == 1'b0) begin
        dma_req <= 1'b0;
        dma_address <= 32'd0;
        irq <= 1'b0;
        volume <= 7'd0;
        sample <= 8'd0;
        data <= 16'd0;
        data_update <= 2'b00;
 
        location <= 32'd0;
        length <= 16'd0;
        length_left <= 17'd0;
        period <= 16'd0;
        period_left <= 16'd0;
        even_word <= 1'b0;
        data2 <= 16'd0;
        avail <= 2'd0;
        state <= S_IDLE;
    end
    else begin
 
        if(irq == 1'b1)             irq <= 1'b0;
        if(data_update != 2'b00)    data_update <= 2'b00;
 
        if(state == S_IDLE && dma_ena == 1'b0 && write_ena == 1'b1 && write_address == 2'd2 && write_sel[1:0] != 2'b00) begin
            state <= S_DIRECT;
            length_left <= 17'd2;
            period_left <= period;
            even_word <= 1'b0;
            avail <= 2'd0;
        end
        else if((state == S_DIRECT && dma_ena == 1'b1) || (state == S_DMA && dma_ena == 1'b0)) begin
            state <= S_IDLE;
        end
        else if(state == S_IDLE && dma_ena == 1'b1 && line_start == 1'b1 && length > 17'd0) begin
            state <= S_DMA;
            dma_address <= location;
            length_left <= { length, 1'b0 };
            period_left <= period;
            irq <= 1'b1;
            even_word <= 1'b0;
            avail <= 2'd0;
 
            dma_req <= 1'b1;
        end
        else if(state == S_DMA && line_start == 1'b1 && avail < 2'd2) begin
            dma_req <= 1'b1;
        end
        else if(state == S_DMA && dma_done == 1'b1) begin
            dma_req <= 1'b0;
            avail <= avail + 2'd1;
            dma_address <= dma_address + 32'd2;
        end
 
        if((state == S_DIRECT || state == S_DMA) && pulse_color == 1'b1) begin
            if(period_left > 16'd1) begin
                period_left <= period_left - 16'd1;
            end
            else begin
                period_left <= period;
 
                if(is_modulator_channel == 1'b0)    data_update <= 2'b01;
                else if(even_word == 1'b0)          data_update <= 2'b10;
                else                                data_update <= 2'b11;
 
                if(is_modulator_channel == 1'b1)    even_word <= ~even_word;
 
                if(length_left[0] == 1'b0)          sample <= data[15:8];
                else                                sample <= data[7:0];
 
                if(avail > 2'd0 && (is_modulator_channel == 1'b1 || length_left[0] == 1'b1)) begin
                    if(avail == 2'd2) data <= data2;
                    avail <= avail - 2'd1;
                end
 
                if((is_modulator_channel == 1'b1 && length_left <= 17'd2) || length_left <= 17'd1) begin
                    length_left <= 17'd0;
                    state <= S_IDLE;
                    if(state == S_DIRECT) irq <= 1'b1;
                end
                else if(is_modulator_channel == 1'b1)   length_left <= length_left - 17'd2;
                else                                    length_left <= length_left - 17'd1;
            end
        end
 
        if(write_ena == 1'b1) begin
            if(write_address == 2'd0 && write_sel[0] == 1'b1) location[7:0] <= write_data[7:0];
            if(write_address == 2'd0 && write_sel[1] == 1'b1) location[15:8] <= write_data[15:8];
            if(write_address == 2'd0 && write_sel[2] == 1'b1) location[23:16] <= write_data[23:16];
            if(write_address == 2'd0 && write_sel[3] == 1'b1) location[31:24] <= write_data[31:24];
            if(write_address == 2'd1 && write_sel[0] == 1'b1) period[7:0] <= write_data[7:0];
            if(write_address == 2'd1 && write_sel[1] == 1'b1) period[15:8] <= write_data[15:8];
            if(write_address == 2'd1 && write_sel[2] == 1'b1) length[7:0] <= write_data[23:16];
            if(write_address == 2'd1 && write_sel[3] == 1'b1) length[15:8] <= write_data[31:24];
            if(write_address == 2'd2 && write_sel[0] == 1'b1) data[7:0] <= write_data[7:0];
            if(write_address == 2'd2 && write_sel[1] == 1'b1) data[15:8] <= write_data[15:8];
            if(write_address == 2'd2 && write_sel[2] == 1'b1) volume[6:0] <= write_data[22:16];
            if(write_address == 2'd2 && write_sel[3] == 1'b1) ;
        end
        else if(dma_done == 1'b1) begin
            if(avail == 2'd0) begin
                if(dma_address[1] == 1'b0)  data <= dma_data[31:16];
                else                        data <= dma_data[15:0];
            end
            else begin
                if(dma_address[1] == 1'b0)  data2 <= dma_data[31:16];
                else                        data2 <= dma_data[15:0];
            end
        end
 
    end
end
 
 
endmodule
 
 
 

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1	2	alfik	`/*`
2			`* Copyright 2010, Aleksander Osman, alfik@poczta.fm. All rights reserved.`
3			`*`
4			`* Redistribution and use in source and binary forms, with or without modification, are`
5			`* permitted provided that the following conditions are met:`
6			`*`
7			`* 1. Redistributions of source code must retain the above copyright notice, this list of`
8			`* conditions and the following disclaimer.`
9			`*`
10			`* 2. Redistributions in binary form must reproduce the above copyright notice, this list`
11			`* of conditions and the following disclaimer in the documentation and/or other materials`
12			`* provided with the distribution.`
13			`*`
14			* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
15			`* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND`
16			`* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR`
17			`* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR`
18			`* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR`
19			`* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON`
20			`* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING`
21			`* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF`
22			`* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.`
23			`*/`
24
25			`/*! \file`
26			`* \brief OCS audio implementation with WISHBONE master and slave interface.`
27			`*/`
28
29			`/*! \brief \copybrief ocs_audio.v`
30
31			`List of audio registers:`
32			`\verbatim`
33			`Implemented:`
34			`AUD0LCH + 0A0 W A( E ) Audio channel 0 location (high 3 bits, 5 if ECS)`
35			`AUD0LCL + 0A2 W A Audio channel 0 location (low 15 bits) (horiz. position)`
36			`AUD0LEN 0A4 W P Audio channel 0 length`
37			`AUD0PER 0A6 W P( E ) Audio channel 0 period`
38			`AUD0VOL 0A8 W P Audio channel 0 volume`
39			`AUD0DAT & 0AA W P Audio channel 0 data`
40
41			`AUD1LCH + 0B0 W A Audio channel 1 location (high 3 bits)`
42			`AUD1LCL + 0B2 W A Audio channel 1 location (low 15 bits)`
43			`AUD1LEN 0B4 W P Audio channel 1 length`
44			`AUD1PER 0B6 W P Audio channel 1 period`
45			`AUD1VOL 0B8 W P Audio channel 1 volume`
46			`AUD1DAT & 0BA W P Audio channel 1 data`
47
48			`AUD2LCH + 0C0 W A Audio channel 2 location (high 3 bits)`
49			`AUD2LCL + 0C2 W A Audio channel 2 location (low 15 bits)`
50			`AUD2LEN 0C4 W P Audio channel 2 length`
51			`AUD2PER 0C6 W P Audio channel 2 period`
52			`AUD2VOL 0C8 W P Audio channel 2 volume`
53			`AUD2DAT & 0CA W P Audio channel 2 data`
54
55			`AUD3LCH + 0D0 W A Audio channel 3 location (high 3 bits)`
56			`AUD3LCL + 0D2 W A Audio channel 3 location (low 15 bits)`
57			`AUD3LEN 0D4 W P Audio channel 3 length`
58			`AUD3PER 0D6 W P Audio channel 3 period`
59			`AUD3VOL 0D8 W P Audio channel 3 volume`
60			`AUD3DAT & 0DA W P Audio channel 3 data`
61			`\endverbatim`
62			`*/`
63			`module ocs_audio(`
64			`//% \name Clock and reset`
65			`//% @{`
66			`input CLK_I,`
67			`input reset_n,`
68			`//% @}`
69
70			`//% \name WISHBONE master`
71			`//% @{`
72			`output reg CYC_O,`
73			`output reg STB_O,`
74			`output WE_O,`
75			`output [31:2] ADR_O,`
76			`output [3:0] SEL_O,`
77			`input [31:0] master_DAT_I,`
78			`input ACK_I,`
79			`//% @}`
80
81			`//% \name WISHBONE slave`
82			`//% @{`
83			`input CYC_I,`
84			`input STB_I,`
85			`input WE_I,`
86			`input [8:2] ADR_I,`
87			`input [3:0] SEL_I,`
88			`input [31:0] slave_DAT_I,`
89			`output reg ACK_O,`
90			`//% @}`
91
92			`//% \name Internal OCS ports`
93			`//% @{`
94			`input pulse_color,`
95			`input line_start,`
96
97			`input [10:0] dma_con,`
98			`input [14:0] adk_con,`
99
100			`output [3:0] audio_irq,`
101			`//% @}`
102
103			`//% \name drv_audio interface`
104			`//% @{`
105			`output [5:0] volume0,`
106			`output [5:0] volume1,`
107			`output [5:0] volume2,`
108			`output [5:0] volume3,`
109			`output [7:0] sample0,`
110			`output [7:0] sample1,`
111			`output [7:0] sample2,`
112			`output [7:0] sample3`
113			`//% @}`
114			`);`
115
116			`assign WE_O = 1'b0;`
117			`assign SEL_O = 4'b1111;`
118
119			`assign volume0 = (adk_con[0] == 1'b1 \|\| adk_con[4] == 1'b1) ? 6'd0 : (channel0_volume[6] == 1'b1) ? 6'b111111 : channel0_volume[5:0];`
120			`assign volume1 = (adk_con[1] == 1'b1 \|\| adk_con[5] == 1'b1) ? 6'd0 : (channel1_volume[6] == 1'b1) ? 6'b111111 : channel1_volume[5:0];`
121			`assign volume2 = (adk_con[2] == 1'b1 \|\| adk_con[6] == 1'b1) ? 6'd0 : (channel2_volume[6] == 1'b1) ? 6'b111111 : channel2_volume[5:0];`
122			`assign volume3 = (adk_con[3] == 1'b1 \|\| adk_con[7] == 1'b1) ? 6'd0 : (channel3_volume[6] == 1'b1) ? 6'b111111 : channel3_volume[5:0];`
123
124			`wire [3:0] dma_reqs;`
125			`wire [1:0] selected_channel;`
126			`assign selected_channel =`
127			`(dma_reqs[0] == 1'b1) ? 2'd0 :`
128			`(dma_reqs[1] == 1'b1) ? 2'd1 :`
129			`(dma_reqs[2] == 1'b1) ? 2'd2 :`
130			`2'd3;`
131
132			`assign ADR_O =`
133			`(selected_channel == 3'd0) ? dma_address0[31:2] :`
134			`(selected_channel == 3'd1) ? dma_address1[31:2] :`
135			`(selected_channel == 3'd2) ? dma_address2[31:2] :`
136			`dma_address3[31:2];`
137
138			`wire dma_req;`
139			`assign dma_req = dma_reqs[0] \| dma_reqs[1] \| dma_reqs[2] \| dma_reqs[3];`
140
141			`//*************** Channel 0`
142			`wire [6:0] channel0_volume;`
143			`wire [15:0] channel0_data;`
144			`wire [1:0] channel0_update;`
145			`wire [31:0] dma_address0;`
146
147			`wire write_ena_extern0;`
148			`assign write_ena_extern0 = (CYC_I == 1'b1 && STB_I == 1'b1 && WE_I == 1'b1 &&`
149			`( { ADR_I, 2'b0 } == 9'h0A0 \|\| { ADR_I, 2'b0 } == 9'h0A4 \|\| { ADR_I, 2'b0 } == 9'h0A8 ) );`
150			`wire write_ena0;`
151			`assign write_ena0 = write_ena_extern0;`
152
153			`wire [1:0] write_address0;`
154			`assign write_address0 =`
155			`({ ADR_I, 2'b0 } == 9'h0A0) ? 2'd0 :`
156			`({ ADR_I, 2'b0 } == 9'h0A4) ? 2'd1 :`
157			`2'd2;`
158
159			`wire [31:0] write_data0;`
160			`assign write_data0 = slave_DAT_I;`
161
162			`wire [3:0] write_sel0;`
163			`assign write_sel0 = SEL_I;`
164
165			`sound_channel sound_channel_0(`
166			`.CLK_I(CLK_I),`
167			`.reset_n(reset_n),`
168
169			`.pulse_color(pulse_color),`
170			`.line_start(line_start),`
171
172			`.dma_ena(dma_con[9] == 1'b1 && dma_con[0] == 1'b1),`
173			`.dma_req(dma_reqs[0]),`
174			`.dma_address(dma_address0),`
175			`.dma_done(selected_channel == 2'd0 && ACK_I == 1'b1),`
176			`.dma_data(master_DAT_I),`
177
178			`.write_ena(write_ena0),`
179			`.write_address(write_address0),`
180			`.write_data(write_data0),`
181			`.write_sel(write_sel0),`
182
183			`.irq(audio_irq[0]),`
184
185			`.volume(channel0_volume),`
186			`.sample(sample0),`
187			`.is_modulator_channel(adk_con[0] == 1'b1 \|\| adk_con[4] == 1'b1),`
188			`.data(channel0_data),`
189			`.data_update(channel0_update)`
190			`);`
191
192
193			`//*************** Channel 1`
194			`wire [6:0] channel1_volume;`
195			`wire [15:0] channel1_data;`
196			`wire [1:0] channel1_update;`
197			`wire [31:0] dma_address1;`
198
199			`wire write_ena_extern1;`
200			`assign write_ena_extern1 = (CYC_I == 1'b1 && STB_I == 1'b1 && WE_I == 1'b1 &&`
201			`( { ADR_I, 2'b0 } == 9'h0B0 \|\| { ADR_I, 2'b0 } == 9'h0B4 \|\| { ADR_I, 2'b0 } == 9'h0B8) );`
202			`wire write_ena1;`
203			`assign write_ena1 = ((adk_con[0] == 1'b1 \|\| adk_con[4] == 1'b1) && (channel0_update == 2'b10 \|\| channel0_update == 2'b11)) \|\| write_ena_extern1;`
204
205			`wire [1:0] write_address1;`
206			`assign write_address1 =`
207			`write_ena_extern1 ? (`
208			`({ ADR_I, 2'b0 } == 9'h0B0) ? 2'd0 :`
209			`({ ADR_I, 2'b0 } == 9'h0B4) ? 2'd1 :`
210			`2'd2`
211			`) :`
212			`(adk_con[0] == 1'b1 && adk_con[4] == 1'b0) ? 2'd2 :`
213			`(adk_con[0] == 1'b0 && adk_con[4] == 1'b1) ? 2'd1 :`
214			`(channel0_update == 2'b10) ? 2'd2 :`
215			`2'd1;`
216
217			`wire [3:0] write_sel1;`
218			`assign write_sel1 =`
219			`write_ena_extern1 ? SEL_I :`
220			`(adk_con[0] == 1'b1 && adk_con[4] == 1'b0) ? 4'b1100 :`
221			`(adk_con[0] == 1'b0 && adk_con[4] == 1'b1) ? 4'b0011 :`
222			`(channel0_update == 2'b10) ? 4'b1100 :`
223			`4'b0011;`
224
225			`wire [31:0] write_data1;`
226			`assign write_data1 =`
227			`write_ena_extern1 ? slave_DAT_I :`
228			`channel0_data;`
229
230			`sound_channel sound_channel_1(`
231			`.CLK_I(CLK_I),`
232			`.reset_n(reset_n),`
233
234			`.pulse_color(pulse_color),`
235			`.line_start(line_start),`
236
237			`.dma_ena(dma_con[9] == 1'b1 && dma_con[1] == 1'b1),`
238			`.dma_req(dma_reqs[1]),`
239			`.dma_address(dma_address1),`
240			`.dma_done(selected_channel == 2'd1 && ACK_I == 1'b1),`
241			`.dma_data(master_DAT_I),`
242
243			`.write_ena(write_ena1),`
244			`.write_address(write_address1),`
245			`.write_data(write_data1),`
246			`.write_sel(write_sel1),`
247
248			`.irq(audio_irq[1]),`
249
250			`.volume(channel1_volume),`
251			`.sample(sample1),`
252			`.is_modulator_channel(adk_con[1] == 1'b1 \|\| adk_con[5] == 1'b1),`
253			`.data(channel1_data),`
254			`.data_update(channel1_update)`
255			`);`
256
257			`//*************** Channel 2`
258			`wire [6:0] channel2_volume;`
259			`wire [15:0] channel2_data;`
260			`wire [1:0] channel2_update;`
261			`wire [31:0] dma_address2;`
262			`wire [7:0] channel2_sample;`
263
264			`wire write_ena_extern2;`
265			`assign write_ena_extern2 = (CYC_I == 1'b1 && STB_I == 1'b1 && WE_I == 1'b1 &&`
266			`( { ADR_I, 2'b0 } == 9'h0C0 \|\| { ADR_I, 2'b0 } == 9'h0C4 \|\| { ADR_I, 2'b0 } == 9'h0C8) );`
267			`wire write_ena2;`
268			`assign write_ena2 = ((adk_con[1] == 1'b1 \|\| adk_con[5] == 1'b1) && (channel1_update == 2'b10 \|\| channel1_update == 2'b11)) \|\| write_ena_extern2;`
269
270			`wire [1:0] write_address2;`
271			`assign write_address2 =`
272			`write_ena_extern2 ? (`
273			`({ ADR_I, 2'b0 } == 9'h0C0) ? 2'd0 :`
274			`({ ADR_I, 2'b0 } == 9'h0C4) ? 2'd1 :`
275			`2'd2`
276			`) :`
277			`(adk_con[1] == 1'b1 && adk_con[5] == 1'b0) ? 2'd2 :`
278			`(adk_con[1] == 1'b0 && adk_con[5] == 1'b1) ? 2'd1 :`
279			`(channel1_update == 2'b10) ? 2'd2 :`
280			`2'd1;`
281
282			`wire [3:0] write_sel2;`
283			`assign write_sel2 =`
284			`write_ena_extern2 ? SEL_I :`
285			`(adk_con[1] == 1'b1 && adk_con[5] == 1'b0) ? 4'b1100 :`
286			`(adk_con[1] == 1'b0 && adk_con[5] == 1'b1) ? 4'b0011 :`
287			`(channel1_update == 2'b10) ? 4'b1100 :`
288			`4'b0011;`
289
290			`wire [31:0] write_data2;`
291			`assign write_data2 =`
292			`write_ena_extern2 ? slave_DAT_I :`
293			`channel1_data;`
294
295			`sound_channel sound_channel_2(`
296			`.CLK_I(CLK_I),`
297			`.reset_n(reset_n),`
298
299			`.pulse_color(pulse_color),`
300			`.line_start(line_start),`
301
302			`.dma_ena(dma_con[9] == 1'b1 && dma_con[2] == 1'b1),`
303			`.dma_req(dma_reqs[2]),`
304			`.dma_address(dma_address2),`
305			`.dma_done(selected_channel == 2'd2 && ACK_I == 1'b1),`
306			`.dma_data(master_DAT_I),`
307
308			`.write_ena(write_ena2),`
309			`.write_address(write_address2),`
310			`.write_data(write_data2),`
311			`.write_sel(write_sel2),`
312
313			`.irq(audio_irq[2]),`
314
315			`.volume(channel2_volume),`
316			`.sample(sample2),`
317			`.is_modulator_channel(adk_con[2] == 1'b1 \|\| adk_con[6] == 1'b1),`
318			`.data(channel2_data),`
319			`.data_update(channel2_update)`
320			`);`
321
322			`//****************** Channel 3`
323			`wire [6:0] channel3_volume;`
324			`wire [15:0] channel3_data;`
325			`wire [1:0] channel3_update;`
326			`wire [31:0] dma_address3;`
327
328			`wire write_ena_extern3;`
329			`assign write_ena_extern3 = (CYC_I == 1'b1 && STB_I == 1'b1 && WE_I == 1'b1 &&`
330			`( { ADR_I, 2'b0 } == 9'h0D0 \|\| { ADR_I, 2'b0 } == 9'h0D4 \|\| { ADR_I, 2'b0 } == 9'h0D8) );`
331			`wire write_ena3;`
332			`assign write_ena3 = ((adk_con[2] == 1'b1 \|\| adk_con[6] == 1'b1) && (channel2_update == 2'b10 \|\| channel2_update == 2'b11)) \|\| write_ena_extern3;`
333
334			`wire [1:0] write_address3;`
335			`assign write_address3 =`
336			`write_ena_extern3 ? (`
337			`({ ADR_I, 2'b0 } == 9'h0D0) ? 2'd0 :`
338			`({ ADR_I, 2'b0 } == 9'h0D4) ? 2'd1 :`
339			`2'd2`
340			`) :`
341			`(adk_con[2] == 1'b1 && adk_con[6] == 1'b0) ? 2'd2 :`
342			`(adk_con[2] == 1'b0 && adk_con[6] == 1'b1) ? 2'd1 :`
343			`(channel2_update == 2'b10) ? 2'd2 :`
344			`2'd1;`
345
346			`wire [3:0] write_sel3;`
347			`assign write_sel3 =`
348			`write_ena_extern3 ? SEL_I :`
349			`(adk_con[2] == 1'b1 && adk_con[6] == 1'b0) ? 4'b1100 :`
350			`(adk_con[2] == 1'b0 && adk_con[6] == 1'b1) ? 4'b0011 :`
351			`(channel2_update == 2'b10) ? 4'b1100 :`
352			`4'b0011;`
353
354			`wire [31:0] write_data3;`
355			`assign write_data3 =`
356			`write_ena_extern3 ? slave_DAT_I :`
357			`channel2_data;`
358
359			`sound_channel sound_channel_3(`
360			`.CLK_I(CLK_I),`
361			`.reset_n(reset_n),`
362
363			`.pulse_color(pulse_color),`
364			`.line_start(line_start),`
365
366			`.dma_ena(dma_con[9] == 1'b1 && dma_con[3] == 1'b1),`
367			`.dma_req(dma_reqs[3]),`
368			`.dma_address(dma_address3),`
369			`.dma_done(selected_channel == 2'd3 && ACK_I == 1'b1),`
370			`.dma_data(master_DAT_I),`
371
372			`.write_ena(write_ena3),`
373			`.write_address(write_address3),`
374			`.write_data(write_data3),`
375			`.write_sel(write_sel3),`
376
377			`.irq(audio_irq[3]),`
378
379			`.volume(channel3_volume),`
380			`.sample(sample3),`
381			`.is_modulator_channel(adk_con[3] == 1'b1 \|\| adk_con[7] == 1'b1),`
382			`.data(channel3_data),`
383			`.data_update(channel3_update)`
384			`);`
385
386			`always @(posedge CLK_I or negedge reset_n) begin`
387			`if(reset_n == 1'b0) begin`
388			`CYC_O <= 1'b0;`
389			`STB_O <= 1'b0;`
390			`ACK_O <= 1'b0;`
391			`end`
392			`else begin`
393			`if(ACK_O == 1'b1) begin`
394			`ACK_O <= 1'b0;`
395			`end`
396			`else if(write_ena_extern0 == 1'b1 \|\| write_ena_extern1 == 1'b1 \|\| write_ena_extern2 == 1'b1 \|\| write_ena_extern3 == 1'b1 \|\|`
397			`(CYC_I == 1'b1 && STB_I == 1'b1 && WE_I == 1'b0))`
398			`begin`
399			`ACK_O <= 1'b1;`
400			`end`
401
402			`if(CYC_O == 1'b0 && STB_O == 1'b0 && dma_req == 1'b1) begin`
403			`CYC_O <= 1'b1;`
404			`STB_O <= 1'b1;`
405			`end`
406			`else if(CYC_O == 1'b1 && STB_O == 1'b1 && ACK_I == 1'b1) begin`
407			`CYC_O <= 1'b0;`
408			`STB_O <= 1'b0;`
409			`end`
410
411			`end`
412			`end`
413
414			`endmodule`
415
416			`/*! \brief Single audio channel.`
417			`*/`
418			`module sound_channel(`
419			`input CLK_I,`
420			`input reset_n,`
421
422			`// color pulse`
423			`input pulse_color,`
424			`input line_start,`
425
426			`input dma_ena,`
427			`output reg dma_req,`
428			`output reg [31:0] dma_address,`
429			`input dma_done,`
430			`input [31:0] dma_data,`
431
432			`input write_ena,`
433			`// 0: AUDxLCH, AUDxLCL,`
434			`// 1: AUDxLEN, AUDxPER,`
435			`// 2: AUDxVOL, AUDxDAT,`
436			`input [1:0] write_address,`
437			`input [31:0] write_data,`
438			`input [3:0] write_sel,`
439
440			`output reg irq,`
441
442			`// sound interface`
443			`// 0-63,64 only`
444			`output reg [6:0] volume,`
445			`output reg [7:0] sample,`
446			`input is_modulator_channel,`
447			`// volume[6:0]: modulation`
448			`// period[15:0]: modulation`
449			`output reg [15:0] data,`
450			`// 2'b01: 8 bit sample update only`
451			`// 2'b10: 8 bit sample and even word update`
452			`// 2'b11: 8 bit sample and odd word update`
453			`output reg [1:0] data_update`
454			`);`
455
456			`reg [31:0] location;`
457			`reg [15:0] length;`
458			`reg [16:0] length_left;`
459			`reg [15:0] period;`
460			`reg [15:0] period_left;`
461			`reg even_word;`
462			`reg [15:0] data2;`
463			`reg [1:0] avail;`
464			`reg [1:0] state;`
465
466			`parameter [1:0]`
467			`S_IDLE = 2'd0,`
468			`S_DIRECT = 2'd1,`
469			`S_DMA = 2'd2;`
470
471			`always @(posedge CLK_I or negedge reset_n) begin`
472			`if(reset_n == 1'b0) begin`
473			`dma_req <= 1'b0;`
474			`dma_address <= 32'd0;`
475			`irq <= 1'b0;`
476			`volume <= 7'd0;`
477			`sample <= 8'd0;`
478			`data <= 16'd0;`
479			`data_update <= 2'b00;`
480
481			`location <= 32'd0;`
482			`length <= 16'd0;`
483			`length_left <= 17'd0;`
484			`period <= 16'd0;`
485			`period_left <= 16'd0;`
486			`even_word <= 1'b0;`
487			`data2 <= 16'd0;`
488			`avail <= 2'd0;`
489			`state <= S_IDLE;`
490			`end`
491			`else begin`
492
493			`if(irq == 1'b1) irq <= 1'b0;`
494			`if(data_update != 2'b00) data_update <= 2'b00;`
495
496			`if(state == S_IDLE && dma_ena == 1'b0 && write_ena == 1'b1 && write_address == 2'd2 && write_sel[1:0] != 2'b00) begin`
497			`state <= S_DIRECT;`
498			`length_left <= 17'd2;`
499			`period_left <= period;`
500			`even_word <= 1'b0;`
501			`avail <= 2'd0;`
502			`end`
503			`else if((state == S_DIRECT && dma_ena == 1'b1) \|\| (state == S_DMA && dma_ena == 1'b0)) begin`
504			`state <= S_IDLE;`
505			`end`
506			`else if(state == S_IDLE && dma_ena == 1'b1 && line_start == 1'b1 && length > 17'd0) begin`
507			`state <= S_DMA;`
508			`dma_address <= location;`
509			`length_left <= { length, 1'b0 };`
510			`period_left <= period;`
511			`irq <= 1'b1;`
512			`even_word <= 1'b0;`
513			`avail <= 2'd0;`
514
515			`dma_req <= 1'b1;`
516			`end`
517			`else if(state == S_DMA && line_start == 1'b1 && avail < 2'd2) begin`
518			`dma_req <= 1'b1;`
519			`end`
520			`else if(state == S_DMA && dma_done == 1'b1) begin`
521			`dma_req <= 1'b0;`
522			`avail <= avail + 2'd1;`
523			`dma_address <= dma_address + 32'd2;`
524			`end`
525
526			`if((state == S_DIRECT \|\| state == S_DMA) && pulse_color == 1'b1) begin`
527			`if(period_left > 16'd1) begin`
528			`period_left <= period_left - 16'd1;`
529			`end`
530			`else begin`
531			`period_left <= period;`
532
533			`if(is_modulator_channel == 1'b0) data_update <= 2'b01;`
534			`else if(even_word == 1'b0) data_update <= 2'b10;`
535			`else data_update <= 2'b11;`
536
537			`if(is_modulator_channel == 1'b1) even_word <= ~even_word;`
538
539			`if(length_left[0] == 1'b0) sample <= data[15:8];`
540			`else sample <= data[7:0];`
541
542			`if(avail > 2'd0 && (is_modulator_channel == 1'b1 \|\| length_left[0] == 1'b1)) begin`
543			`if(avail == 2'd2) data <= data2;`
544			`avail <= avail - 2'd1;`
545			`end`
546
547			`if((is_modulator_channel == 1'b1 && length_left <= 17'd2) \|\| length_left <= 17'd1) begin`
548			`length_left <= 17'd0;`
549			`state <= S_IDLE;`
550			`if(state == S_DIRECT) irq <= 1'b1;`
551			`end`
552			`else if(is_modulator_channel == 1'b1) length_left <= length_left - 17'd2;`
553			`else length_left <= length_left - 17'd1;`
554			`end`
555			`end`
556
557			`if(write_ena == 1'b1) begin`
558			`if(write_address == 2'd0 && write_sel[0] == 1'b1) location[7:0] <= write_data[7:0];`
559			`if(write_address == 2'd0 && write_sel[1] == 1'b1) location[15:8] <= write_data[15:8];`
560			`if(write_address == 2'd0 && write_sel[2] == 1'b1) location[23:16] <= write_data[23:16];`
561			`if(write_address == 2'd0 && write_sel[3] == 1'b1) location[31:24] <= write_data[31:24];`
562			`if(write_address == 2'd1 && write_sel[0] == 1'b1) period[7:0] <= write_data[7:0];`
563			`if(write_address == 2'd1 && write_sel[1] == 1'b1) period[15:8] <= write_data[15:8];`
564			`if(write_address == 2'd1 && write_sel[2] == 1'b1) length[7:0] <= write_data[23:16];`
565			`if(write_address == 2'd1 && write_sel[3] == 1'b1) length[15:8] <= write_data[31:24];`
566			`if(write_address == 2'd2 && write_sel[0] == 1'b1) data[7:0] <= write_data[7:0];`
567			`if(write_address == 2'd2 && write_sel[1] == 1'b1) data[15:8] <= write_data[15:8];`
568			`if(write_address == 2'd2 && write_sel[2] == 1'b1) volume[6:0] <= write_data[22:16];`
569			`if(write_address == 2'd2 && write_sel[3] == 1'b1) ;`
570			`end`
571			`else if(dma_done == 1'b1) begin`
572			`if(avail == 2'd0) begin`
573			`if(dma_address[1] == 1'b0) data <= dma_data[31:16];`
574			`else data <= dma_data[15:0];`
575			`end`
576			`else begin`
577			`if(dma_address[1] == 1'b0) data2 <= dma_data[31:16];`
578			`else data2 <= dma_data[15:0];`
579			`end`
580			`end`
581
582			`end`
583			`end`
584
585
586			`endmodule`
587
588
589