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[/] [aoocs/] [trunk/] [tests/] [debug.v] - Blame information for rev 2

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1 2 alfik 
module debug(
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    input CLK_I,
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    input reset_n,
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    // WISHBONE master
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    output reg CYC_O,
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    output reg STB_O,
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    output reg WE_O,
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    output reg [31:2] ADR_O,
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    output reg [3:0] SEL_O,
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    output reg [31:0] master_DAT_O,
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    input [31:0] master_DAT_I,
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    input ACK_I,
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    input start_dump,
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    input start_dump2
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);
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reg [31:0] adr;
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reg [2:0] state;
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parameter [2:0]
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    S_IDLE          = 3'd0,
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    S_READ          = 3'd1,
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    S_READ_2        = 3'd2,
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    S_READ_3        = 3'd3,
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    S_READ_4        = 3'd4,
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    S_FINISHED      = 3'd5;
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always @(posedge CLK_I or negedge reset_n) begin
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    if(reset_n == 1'b0) begin
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        CYC_O <= 1'b0;
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        STB_O <= 1'b0;
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        WE_O <= 1'b0;
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        ADR_O <= 30'd0;
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        SEL_O <= 4'd0;
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        master_DAT_O <= 32'd0;
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        adr <= 32'd0;
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        state <= S_IDLE;
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    end
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    else begin
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        case(state)
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            S_IDLE: begin
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                if(start_dump == 1'b1) begin
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                    state <= S_READ;
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                end
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            end
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            S_READ: begin
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                CYC_O <= 1'b1;
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                STB_O <= 1'b1;
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                WE_O <= 1'b0;
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                ADR_O <= adr[31:2];
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                SEL_O <= 4'b1111;
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                if(ACK_I == 1'b0)   state <= S_READ_2;
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            end
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            S_READ_2: begin
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                if(ACK_I == 1'b1) begin
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                    CYC_O <= 1'b0;
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                    STB_O <= 1'b0;
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                    master_DAT_O <= master_DAT_I;
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                    state <= S_READ_3;
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                end
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            end
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            S_READ_3: begin
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                CYC_O <= 1'b1;
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                STB_O <= 1'b1;
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                WE_O <= 1'b1;
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                ADR_O <= 30'h4000800;
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                SEL_O <= 4'b1111;
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                adr <= adr + 32'd1;
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                if(ACK_I == 1'b0)   state <= S_READ_4;
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            end
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            S_READ_4: begin
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                if(ACK_I == 1'b1) begin
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                    CYC_O <= 1'b0;
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                    STB_O <= 1'b0;
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                    if(adr[1:0] == 2'b00 && adr < 32'h80000) begin
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                        state <= S_READ;
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                    end
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                    else if(adr[1:0] == 2'b00 && adr == 32'h80000) begin
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                        state <= S_FINISHED;
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                    end
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                    else begin
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                        master_DAT_O <= { master_DAT_O[23:0], 8'd0 };
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                        state <= S_READ_3;
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                    end
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                end
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            end
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            S_FINISHED: begin
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                if(start_dump2 == 1'b0) begin
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                    state <= S_READ;
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                    adr <= 32'd0;
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                end
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            end
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        endcase
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    end
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end
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endmodule
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