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[/] [aoocs/] [trunk/] [tests/] [ethernet_test/] [ethernet.v] - Blame information for rev 2

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/*
Send UDP packet:
ethernet
    dest mac(6), src mac(6), type(2 = 0x0800 IPv4)
ip
    version,header([1] = 0x45), tos([1] = 0x00), length([2] = 4*5 + 4*2 + len = 992 = 0x03E0)
    id([2] = 0x0000), flags,offset([2] = 0x40, 0x00)
    ttl([1] = 0x0F), protocol([1] = 0x11), header checksum([2] = 0)
    source ip([4])
    dest ip([4])
udp
    source port([2]), dest port([2])
    length([2] = 8 + len = 972 = 0x03CC), checksum([2] = 0)
data
    (len = line num(1) + line(214*36/8 = 963) = 964)
 
--full ethernet packet len = 992 + 14 = 1006 = 0x03EE
 
DM9000A control to send:
    set IMR(FFh = 0x80)
 
    set checksum reg (31h = 0x05)
 
    set early transmit (30h = 0x83) ? threshold 75%
 
    power-up PHY (1Fh = 0x00)
 
    dummy MWCDM ?
 
    DO
 
        packet I
        set MWCMD(F8h = 16-bit data)
 
        wait for packet II
        read TX(02h bit 0 == 0)
 
        set TXPLL(FCh = low byte)
        set TXPLH(FDh = high byte)
 
        write TX(02h 0x01)
 
        packet II
        set MWCMD(F8h = 16-bit data)
 
        wait for packet I
        read TX(02h bit 0 == 0)
 
        set TXPLL(FCh = low byte)
        set TXPLH(FDh = high byte)
 
        write TX(02h 0x01)
 
    LOOP
 
*/
 
module ethernet(
    input clk_50,
    input reset_ext_n,
 
    output enet_clk_25,
    output enet_reset_n,
    output enet_cs_n,
 
    input enet_irq,
 
    output reg enet_ior_n,
    output reg enet_iow_n,
    output reg enet_cmd,
 
    inout [15:0] enet_data,
 
    input key,
    output [7:0] leds
);
 
assign leds = state_counter[7:0];
 
/***********************************************************************************************************************
 * System PLL
 **********************************************************************************************************************/
 
wire [5:0]  pll_clocks;
assign      enet_clk_25 = pll_clocks[0];
wire        clk_30 = pll_clocks[1];
wire        pll_locked;
 
altpll pll_inst(
    .inclk  ( {1'b0, clk_50} ),
    .clk    (pll_clocks),
    .locked (pll_locked)
);
defparam
    pll_inst.clk0_divide_by             = 2,
    pll_inst.clk0_duty_cycle            = 50,
    pll_inst.clk0_multiply_by           = 1,
    pll_inst.clk0_phase_shift           = "0",
    pll_inst.clk1_divide_by             = 5,
    pll_inst.clk1_duty_cycle            = 50,
    pll_inst.clk1_multiply_by           = 3,
    pll_inst.clk1_phase_shift           = "0",
    pll_inst.compensate_clock           = "CLK0",
    pll_inst.gate_lock_counter          = 1048575,
    pll_inst.gate_lock_signal           = "YES",
    pll_inst.inclk0_input_frequency     = 20000,
    pll_inst.intended_device_family     = "Cyclone II",
    pll_inst.invalid_lock_multiplier    = 5,
    pll_inst.lpm_hint                   = "CBX_MODULE_PREFIX=pll30",
    pll_inst.lpm_type                   = "altpll",
    pll_inst.operation_mode             = "NORMAL",
    pll_inst.valid_lock_multiplier      = 1;
 
wire reset_n            = pll_locked & reset_ext_n;
 
/***********************************************************************************************************************
 *
 **********************************************************************************************************************/
assign enet_reset_n = reset_n;
assign enet_cs_n    = 1'b0;
 
reg tx_active;
 
reg enet_data_oe;
reg [15:0] enet_data_out;
assign enet_data = (enet_data_oe == 1'b1)? enet_data_out : 16'bZ;
 
//************
reg [5:0] ram_addr;
wire [15:0] ram_q;
 
altsyncram ethernet_ram_inst(
    .clock0(clk_30),
    .address_a(ram_addr),
    .q_a(ram_q)
);
defparam
    ethernet_ram_inst.operation_mode = "ROM",
    ethernet_ram_inst.width_a = 16,
    ethernet_ram_inst.widthad_a = 6,
    ethernet_ram_inst.init_file = "ethernet.mif";
 
//************
 
 
reg [15:0] state_counter;
always @(posedge clk_30 or negedge reset_n) begin
    if(reset_n == 1'b0) begin
        state_counter   <= 16'd0;
        tx_active       <= 1'b0;
 
        enet_iow_n      <= 1'b1;
        enet_ior_n      <= 1'b1;
        enet_cmd        <= 1'b0;        // low: INDEX, high: DATA
        enet_data_oe    <= 1'b0;
        enet_data_out   <= 16'd0;
 
        ram_addr        <= 6'd0;
    end
    else if(state_counter == 16'd50000) begin
        //if(key == 1'b0) begin
            enet_iow_n <= 1'b0;
            enet_cmd <= 1'b0;
            enet_data_oe <= 1'b1;
            enet_data_out <= { 8'd0, 8'hFF }; // set IMR(FFh = 0x80)
 
            state_counter <= state_counter + 16'd1;
        //end
    end
    else if(state_counter == 16'd50002) begin
        enet_iow_n <= 1'b0;
        enet_cmd <= 1'b1;
        enet_data_out <= { 8'd0, 8'h80 };
 
        state_counter <= state_counter + 16'd1;
    end
    else if(state_counter == 16'd50005) begin
        enet_iow_n <= 1'b0;
        enet_cmd <= 1'b0;
        enet_data_out <= { 8'd0, 8'h1F }; // power-up PHY (1Fh = 0x00)
 
        state_counter <= state_counter + 16'd1;
    end
    else if(state_counter == 16'd50007) begin
        enet_iow_n <= 1'b0;
        enet_cmd <= 1'b1;
        enet_data_out <= { 8'd0, 8'h00 };
 
        state_counter <= state_counter + 16'd1;
    end
 
    else if(state_counter == 16'd50010) begin
        enet_iow_n <= 1'b0;
        enet_cmd <= 1'b0;
        enet_data_out <= { 8'd0, 8'h31 }; // set checksum reg (31h = 0x05)
 
        state_counter <= state_counter + 16'd1;
    end
    else if(state_counter == 16'd50012) begin
        enet_iow_n <= 1'b0;
        enet_cmd <= 1'b1;
        enet_data_out <= { 8'd0, 8'h05 };
 
        state_counter <= state_counter + 16'd1;
    end
 
 
    else if(state_counter == 16'd50018) begin
        enet_iow_n <= 1'b0;
        enet_cmd <= 1'b0;
        enet_data_out <= { 8'd0, 8'hF8 }; // set MWCMD(F8h = 16-bit data) 
 
        ram_addr <= 6'd0;
        state_counter <= state_counter + 16'd1;
    end
    else if(state_counter >= 16'd50020 && state_counter <= 16'd50060 && state_counter[0] == 1'b0) begin
        enet_iow_n <= 1'b0;
        enet_cmd <= 1'b1;
        enet_data_out <= ram_q;
 
        ram_addr <= ram_addr + 6'd1;
        state_counter <= state_counter + 16'd1;
    end
 
    else if(state_counter >= 16'd50062 && state_counter <= 16'd51024 && state_counter[0] == 1'b0) begin
        enet_iow_n <= 1'b0;
        enet_cmd <= 1'b1;
        enet_data_out <= { 16'hAAAA };
 
        if(state_counter == 16'd51024)  state_counter <= 16'd60016 - 16'd1;
        else                            state_counter <= state_counter + 16'd1;
    end
 
 
    else if(state_counter == 16'd60016) begin
        enet_iow_n <= 1'b0;
        enet_cmd <= 1'b0;
        enet_data_oe <= 1'b1;
        enet_data_out <= { 8'd0, 8'h02 }; // read TX(02h bit 0 == 0)
 
        state_counter <= state_counter + 16'd1;
    end
    else if(state_counter == 16'd60018) begin
        enet_ior_n <= 1'b0;
        enet_cmd <= 1'b1;
        enet_data_oe <= 1'b0;
 
        state_counter <= state_counter + 16'd1;
    end
    else if(state_counter == 16'd60020) begin
        enet_ior_n <= 1'b1;
        tx_active <= enet_data[0];
 
        state_counter <= state_counter + 16'd1;
    end
    else if(state_counter == 16'd60022) begin
        if(tx_active == 1'b0)   state_counter <= 16'd60118;
        else                    state_counter <= 16'd60016;
    end
 
    else if(state_counter == 16'd60118) begin
        enet_iow_n <= 1'b0;
        enet_cmd <= 1'b0;
        enet_data_oe <= 1'b1;
        enet_data_out <= { 8'd0, 8'hFC }; // set TXPLL(FCh = low byte)
 
        state_counter <= state_counter + 16'd1;
    end
    else if(state_counter == 16'd60120) begin
        enet_iow_n <= 1'b0;
        enet_cmd <= 1'b1;
        enet_data_out <= { 8'h00, 8'hEE };
 
        state_counter <= state_counter + 16'd1;
    end
 
    else if(state_counter == 16'd60123) begin
        enet_iow_n <= 1'b0;
        enet_cmd <= 1'b0;
        enet_data_out <= { 8'd0, 8'hFD }; // set TXPLH(FDh = high byte)
 
        state_counter <= state_counter + 16'd1;
    end
    else if(state_counter == 16'd60125) begin
        enet_iow_n <= 1'b0;
        enet_cmd <= 1'b1;
        enet_data_out <= { 8'h00, 8'h03 };
 
        state_counter <= state_counter + 16'd1;
    end
 
    else if(state_counter == 16'd60128) begin
        enet_iow_n <= 1'b0;
        enet_cmd <= 1'b0;
        enet_data_out <= { 8'd0, 8'h02 }; // write TX(02h = 0x01)
 
        state_counter <= state_counter + 16'd1;
    end
    else if(state_counter == 16'd60130) begin
        enet_iow_n <= 1'b0;
        enet_cmd <= 1'b1;
        enet_data_out <= { 8'h00, 8'h01 };
 
        state_counter <= state_counter + 16'd1;
    end
 
    else if(state_counter == 16'd60132) begin
         state_counter <= 16'd50018;
    end
 
    else if(state_counter <= 16'd60132) begin
        enet_iow_n <= 1'b1;
        enet_ior_n <= 1'b1;
        state_counter <= state_counter + 16'd1;
    end
 
end
 
endmodule

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Subversion Repositories aoocs

[/] [aoocs/] [trunk/] [tests/] [ethernet_test/] [ethernet.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	alfik	`/*`
2			`Send UDP packet:`
3			`ethernet`
4			`dest mac(6), src mac(6), type(2 = 0x0800 IPv4)`
5			`ip`
6			`version,header([1] = 0x45), tos([1] = 0x00), length([2] = 45 + 42 + len = 992 = 0x03E0)`
7			`id([2] = 0x0000), flags,offset([2] = 0x40, 0x00)`
8			`ttl([1] = 0x0F), protocol([1] = 0x11), header checksum([2] = 0)`
9			`source ip([4])`
10			`dest ip([4])`
11			`udp`
12			`source port([2]), dest port([2])`
13			`length([2] = 8 + len = 972 = 0x03CC), checksum([2] = 0)`
14			`data`
15			`(len = line num(1) + line(214*36/8 = 963) = 964)`
16
17			`--full ethernet packet len = 992 + 14 = 1006 = 0x03EE`
18
19			`DM9000A control to send:`
20			`set IMR(FFh = 0x80)`
21
22			`set checksum reg (31h = 0x05)`
23
24			`set early transmit (30h = 0x83) ? threshold 75%`
25
26			`power-up PHY (1Fh = 0x00)`
27
28			`dummy MWCDM ?`
29
30			`DO`
31
32			`packet I`
33			`set MWCMD(F8h = 16-bit data)`
34
35			`wait for packet II`
36			`read TX(02h bit 0 == 0)`
37
38			`set TXPLL(FCh = low byte)`
39			`set TXPLH(FDh = high byte)`
40
41			`write TX(02h 0x01)`
42
43			`packet II`
44			`set MWCMD(F8h = 16-bit data)`
45
46			`wait for packet I`
47			`read TX(02h bit 0 == 0)`
48
49			`set TXPLL(FCh = low byte)`
50			`set TXPLH(FDh = high byte)`
51
52			`write TX(02h 0x01)`
53
54			`LOOP`
55
56			`*/`
57
58			`module ethernet(`
59			`input clk_50,`
60			`input reset_ext_n,`
61
62			`output enet_clk_25,`
63			`output enet_reset_n,`
64			`output enet_cs_n,`
65
66			`input enet_irq,`
67
68			`output reg enet_ior_n,`
69			`output reg enet_iow_n,`
70			`output reg enet_cmd,`
71
72			`inout [15:0] enet_data,`
73
74			`input key,`
75			`output [7:0] leds`
76			`);`
77
78			`assign leds = state_counter[7:0];`
79
80			`/***********************************************************************************************************************`
81			`* System PLL`
82			`**********************************************************************************************************************/`
83
84			`wire [5:0] pll_clocks;`
85			`assign enet_clk_25 = pll_clocks[0];`
86			`wire clk_30 = pll_clocks[1];`
87			`wire pll_locked;`
88
89			`altpll pll_inst(`
90			`.inclk ( {1'b0, clk_50} ),`
91			`.clk (pll_clocks),`
92			`.locked (pll_locked)`
93			`);`
94			`defparam`
95			`pll_inst.clk0_divide_by = 2,`
96			`pll_inst.clk0_duty_cycle = 50,`
97			`pll_inst.clk0_multiply_by = 1,`
98			`pll_inst.clk0_phase_shift = "0",`
99			`pll_inst.clk1_divide_by = 5,`
100			`pll_inst.clk1_duty_cycle = 50,`
101			`pll_inst.clk1_multiply_by = 3,`
102			`pll_inst.clk1_phase_shift = "0",`
103			`pll_inst.compensate_clock = "CLK0",`
104			`pll_inst.gate_lock_counter = 1048575,`
105			`pll_inst.gate_lock_signal = "YES",`
106			`pll_inst.inclk0_input_frequency = 20000,`
107			`pll_inst.intended_device_family = "Cyclone II",`
108			`pll_inst.invalid_lock_multiplier = 5,`
109			`pll_inst.lpm_hint = "CBX_MODULE_PREFIX=pll30",`
110			`pll_inst.lpm_type = "altpll",`
111			`pll_inst.operation_mode = "NORMAL",`
112			`pll_inst.valid_lock_multiplier = 1;`
113
114			`wire reset_n = pll_locked & reset_ext_n;`
115
116			`/***********************************************************************************************************************`
117			`*`
118			`**********************************************************************************************************************/`
119			`assign enet_reset_n = reset_n;`
120			`assign enet_cs_n = 1'b0;`
121
122			`reg tx_active;`
123
124			`reg enet_data_oe;`
125			`reg [15:0] enet_data_out;`
126			`assign enet_data = (enet_data_oe == 1'b1)? enet_data_out : 16'bZ;`
127
128			`//************`
129			`reg [5:0] ram_addr;`
130			`wire [15:0] ram_q;`
131
132			`altsyncram ethernet_ram_inst(`
133			`.clock0(clk_30),`
134			`.address_a(ram_addr),`
135			`.q_a(ram_q)`
136			`);`
137			`defparam`
138			`ethernet_ram_inst.operation_mode = "ROM",`
139			`ethernet_ram_inst.width_a = 16,`
140			`ethernet_ram_inst.widthad_a = 6,`
141			`ethernet_ram_inst.init_file = "ethernet.mif";`
142
143			`//************`
144
145
146			`reg [15:0] state_counter;`
147			`always @(posedge clk_30 or negedge reset_n) begin`
148			`if(reset_n == 1'b0) begin`
149			`state_counter <= 16'd0;`
150			`tx_active <= 1'b0;`
151
152			`enet_iow_n <= 1'b1;`
153			`enet_ior_n <= 1'b1;`
154			`enet_cmd <= 1'b0; // low: INDEX, high: DATA`
155			`enet_data_oe <= 1'b0;`
156			`enet_data_out <= 16'd0;`
157
158			`ram_addr <= 6'd0;`
159			`end`
160			`else if(state_counter == 16'd50000) begin`
161			`//if(key == 1'b0) begin`
162			`enet_iow_n <= 1'b0;`
163			`enet_cmd <= 1'b0;`
164			`enet_data_oe <= 1'b1;`
165			`enet_data_out <= { 8'd0, 8'hFF }; // set IMR(FFh = 0x80)`
166
167			`state_counter <= state_counter + 16'd1;`
168			`//end`
169			`end`
170			`else if(state_counter == 16'd50002) begin`
171			`enet_iow_n <= 1'b0;`
172			`enet_cmd <= 1'b1;`
173			`enet_data_out <= { 8'd0, 8'h80 };`
174
175			`state_counter <= state_counter + 16'd1;`
176			`end`
177			`else if(state_counter == 16'd50005) begin`
178			`enet_iow_n <= 1'b0;`
179			`enet_cmd <= 1'b0;`
180			`enet_data_out <= { 8'd0, 8'h1F }; // power-up PHY (1Fh = 0x00)`
181
182			`state_counter <= state_counter + 16'd1;`
183			`end`
184			`else if(state_counter == 16'd50007) begin`
185			`enet_iow_n <= 1'b0;`
186			`enet_cmd <= 1'b1;`
187			`enet_data_out <= { 8'd0, 8'h00 };`
188
189			`state_counter <= state_counter + 16'd1;`
190			`end`
191
192			`else if(state_counter == 16'd50010) begin`
193			`enet_iow_n <= 1'b0;`
194			`enet_cmd <= 1'b0;`
195			`enet_data_out <= { 8'd0, 8'h31 }; // set checksum reg (31h = 0x05)`
196
197			`state_counter <= state_counter + 16'd1;`
198			`end`
199			`else if(state_counter == 16'd50012) begin`
200			`enet_iow_n <= 1'b0;`
201			`enet_cmd <= 1'b1;`
202			`enet_data_out <= { 8'd0, 8'h05 };`
203
204			`state_counter <= state_counter + 16'd1;`
205			`end`
206
207
208			`else if(state_counter == 16'd50018) begin`
209			`enet_iow_n <= 1'b0;`
210			`enet_cmd <= 1'b0;`
211			`enet_data_out <= { 8'd0, 8'hF8 }; // set MWCMD(F8h = 16-bit data)`
212
213			`ram_addr <= 6'd0;`
214			`state_counter <= state_counter + 16'd1;`
215			`end`
216			`else if(state_counter >= 16'd50020 && state_counter <= 16'd50060 && state_counter[0] == 1'b0) begin`
217			`enet_iow_n <= 1'b0;`
218			`enet_cmd <= 1'b1;`
219			`enet_data_out <= ram_q;`
220
221			`ram_addr <= ram_addr + 6'd1;`
222			`state_counter <= state_counter + 16'd1;`
223			`end`
224
225			`else if(state_counter >= 16'd50062 && state_counter <= 16'd51024 && state_counter[0] == 1'b0) begin`
226			`enet_iow_n <= 1'b0;`
227			`enet_cmd <= 1'b1;`
228			`enet_data_out <= { 16'hAAAA };`
229
230			`if(state_counter == 16'd51024) state_counter <= 16'd60016 - 16'd1;`
231			`else state_counter <= state_counter + 16'd1;`
232			`end`
233
234
235			`else if(state_counter == 16'd60016) begin`
236			`enet_iow_n <= 1'b0;`
237			`enet_cmd <= 1'b0;`
238			`enet_data_oe <= 1'b1;`
239			`enet_data_out <= { 8'd0, 8'h02 }; // read TX(02h bit 0 == 0)`
240
241			`state_counter <= state_counter + 16'd1;`
242			`end`
243			`else if(state_counter == 16'd60018) begin`
244			`enet_ior_n <= 1'b0;`
245			`enet_cmd <= 1'b1;`
246			`enet_data_oe <= 1'b0;`
247
248			`state_counter <= state_counter + 16'd1;`
249			`end`
250			`else if(state_counter == 16'd60020) begin`
251			`enet_ior_n <= 1'b1;`
252			`tx_active <= enet_data[0];`
253
254			`state_counter <= state_counter + 16'd1;`
255			`end`
256			`else if(state_counter == 16'd60022) begin`
257			`if(tx_active == 1'b0) state_counter <= 16'd60118;`
258			`else state_counter <= 16'd60016;`
259			`end`
260
261			`else if(state_counter == 16'd60118) begin`
262			`enet_iow_n <= 1'b0;`
263			`enet_cmd <= 1'b0;`
264			`enet_data_oe <= 1'b1;`
265			`enet_data_out <= { 8'd0, 8'hFC }; // set TXPLL(FCh = low byte)`
266
267			`state_counter <= state_counter + 16'd1;`
268			`end`
269			`else if(state_counter == 16'd60120) begin`
270			`enet_iow_n <= 1'b0;`
271			`enet_cmd <= 1'b1;`
272			`enet_data_out <= { 8'h00, 8'hEE };`
273
274			`state_counter <= state_counter + 16'd1;`
275			`end`
276
277			`else if(state_counter == 16'd60123) begin`
278			`enet_iow_n <= 1'b0;`
279			`enet_cmd <= 1'b0;`
280			`enet_data_out <= { 8'd0, 8'hFD }; // set TXPLH(FDh = high byte)`
281
282			`state_counter <= state_counter + 16'd1;`
283			`end`
284			`else if(state_counter == 16'd60125) begin`
285			`enet_iow_n <= 1'b0;`
286			`enet_cmd <= 1'b1;`
287			`enet_data_out <= { 8'h00, 8'h03 };`
288
289			`state_counter <= state_counter + 16'd1;`
290			`end`
291
292			`else if(state_counter == 16'd60128) begin`
293			`enet_iow_n <= 1'b0;`
294			`enet_cmd <= 1'b0;`
295			`enet_data_out <= { 8'd0, 8'h02 }; // write TX(02h = 0x01)`
296
297			`state_counter <= state_counter + 16'd1;`
298			`end`
299			`else if(state_counter == 16'd60130) begin`
300			`enet_iow_n <= 1'b0;`
301			`enet_cmd <= 1'b1;`
302			`enet_data_out <= { 8'h00, 8'h01 };`
303
304			`state_counter <= state_counter + 16'd1;`
305			`end`
306
307			`else if(state_counter == 16'd60132) begin`
308			`state_counter <= 16'd50018;`
309			`end`
310
311			`else if(state_counter <= 16'd60132) begin`
312			`enet_iow_n <= 1'b1;`
313			`enet_ior_n <= 1'b1;`
314			`state_counter <= state_counter + 16'd1;`
315			`end`
316
317			`end`
318
319			`endmodule`