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[/] [astron_fifo/] [trunk/] [tech_fifo_component_pkg.vhd] - Blame information for rev 4

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1 2 danv 
-------------------------------------------------------------------------------
2 
--
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-- Copyright 2020
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
6 3 danv 
--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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--
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--     http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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--
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-------------------------------------------------------------------------------
20 
 
21 
-- Purpose: IP components declarations for various devices that get wrapped by the tech components
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LIBRARY ieee, common_pkg_lib;
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USE IEEE.STD_LOGIC_1164.ALL;
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--USE technology_lib.technology_pkg.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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PACKAGE tech_fifo_component_pkg IS
29 
 
30 
  -----------------------------------------------------------------------------
31 
  -- ip_stratixiv
32 
  -----------------------------------------------------------------------------
33 
 
34 
  COMPONENT ip_stratixiv_fifo_sc IS
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  GENERIC (
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    g_use_eab    : STRING := "ON";
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    g_dat_w      : NATURAL;
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    g_nof_words  : NATURAL
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  );
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  PORT (
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    aclr  : IN STD_LOGIC;
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    clock : IN STD_LOGIC;
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    data  : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
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    rdreq : IN STD_LOGIC;
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    wrreq : IN STD_LOGIC;
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    empty : OUT STD_LOGIC;
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    full  : OUT STD_LOGIC;
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    q     : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
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    usedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
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  );
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  END COMPONENT;
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  COMPONENT ip_stratixiv_fifo_dc IS
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  GENERIC (
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    g_dat_w      : NATURAL;
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    g_nof_words  : NATURAL
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  );
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  PORT (
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    aclr    : IN STD_LOGIC  := '0';
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    data    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
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    rdclk   : IN STD_LOGIC;
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    rdreq   : IN STD_LOGIC;
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    wrclk   : IN STD_LOGIC;
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    wrreq   : IN STD_LOGIC;
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    q       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
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    rdempty : OUT STD_LOGIC;
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    rdusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0);
68 2 danv 
    wrfull  : OUT STD_LOGIC;
69 4 danv 
    wrusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
70 2 danv 
  );
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  END COMPONENT;
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73 
  COMPONENT ip_stratixiv_fifo_dc_mixed_widths IS
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  GENERIC (
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    g_nof_words  : NATURAL;  -- FIFO size in nof wr_dat words
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    g_wrdat_w    : NATURAL;
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    g_rddat_w    : NATURAL
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  );
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  PORT (
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    aclr    : IN STD_LOGIC  := '0';
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    data    : IN STD_LOGIC_VECTOR (g_wrdat_w-1 DOWNTO 0);
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    rdclk   : IN STD_LOGIC;
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    rdreq   : IN STD_LOGIC;
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    wrclk   : IN STD_LOGIC;
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    wrreq   : IN STD_LOGIC;
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    q       : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
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    rdempty : OUT STD_LOGIC;
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    rdusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
89 2 danv 
    wrfull  : OUT STD_LOGIC;
90 4 danv 
    wrusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
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  );
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  END COMPONENT;
93 
 
94 
 
95 
--  -----------------------------------------------------------------------------
96 
--  -- ip_arria10
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--  -----------------------------------------------------------------------------
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--
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--  COMPONENT ip_arria10_fifo_sc IS
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--  GENERIC (
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--    g_use_eab   : STRING := "ON";
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--    g_dat_w     : NATURAL := 20;
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--    g_nof_words : NATURAL := 1024
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--  );
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--  PORT (
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--    aclr    : IN STD_LOGIC ;
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--    clock   : IN STD_LOGIC ;
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--    data    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
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--    rdreq   : IN STD_LOGIC ;
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--    wrreq   : IN STD_LOGIC ;
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--    empty   : OUT STD_LOGIC ;
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--    full    : OUT STD_LOGIC ;
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--    q       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0) ;
114 4 danv 
--    usedw   : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
115 2 danv 
--  );
116 
--  END COMPONENT;
117 
--
118 
--  COMPONENT ip_arria10_fifo_dc IS
119 
--  GENERIC (
120 
--    g_use_eab   : STRING := "ON";
121 
--    g_dat_w     : NATURAL := 20;
122 
--    g_nof_words : NATURAL := 1024
123 
--  );
124 
--  PORT (
125 
--    aclr    : IN STD_LOGIC  := '0';
126 
--    data    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
127 
--    rdclk   : IN STD_LOGIC ;
128 
--    rdreq   : IN STD_LOGIC ;
129 
--    wrclk   : IN STD_LOGIC ;
130 
--    wrreq   : IN STD_LOGIC ;
131 
--    q       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
132 
--    rdempty : OUT STD_LOGIC ;
133 4 danv 
--    rdusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0);
134 2 danv 
--    wrfull  : OUT STD_LOGIC ;
135 4 danv 
--    wrusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
136 2 danv 
--  );
137 
--  END COMPONENT;
138 
--
139 
--  COMPONENT ip_arria10_fifo_dc_mixed_widths IS
140 
--  GENERIC (
141 
--    g_nof_words : NATURAL := 1024;  -- FIFO size in nof wr_dat words
142 
--    g_wrdat_w   : NATURAL := 20;
143 
--    g_rddat_w   : NATURAL := 10
144 
--  );
145 
--  PORT (
146 
--    aclr    : IN STD_LOGIC  := '0';
147 
--    data    : IN STD_LOGIC_VECTOR (g_wrdat_w-1 DOWNTO 0);
148 
--    rdclk   : IN STD_LOGIC ;
149 
--    rdreq   : IN STD_LOGIC ;
150 
--    wrclk   : IN STD_LOGIC ;
151 
--    wrreq   : IN STD_LOGIC ;
152 
--    q       : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
153 
--    rdempty : OUT STD_LOGIC ;
154 4 danv 
--    rdusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
155 2 danv 
--    wrfull  : OUT STD_LOGIC ;
156 4 danv 
--    wrusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
157 2 danv 
--  );
158 
--  END COMPONENT;
159 
--
160 
--  -----------------------------------------------------------------------------
161 
--  -- ip_arria10_e3sge3
162 
--  -----------------------------------------------------------------------------
163 
--
164 
--  COMPONENT ip_arria10_e3sge3_fifo_sc IS
165 
--  GENERIC (
166 
--    g_use_eab   : STRING := "ON";
167 
--    g_dat_w     : NATURAL := 20;
168 
--    g_nof_words : NATURAL := 1024
169 
--  );
170 
--  PORT (
171 
--    aclr    : IN STD_LOGIC ;
172 
--    clock   : IN STD_LOGIC ;
173 
--    data    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
174 
--    rdreq   : IN STD_LOGIC ;
175 
--    wrreq   : IN STD_LOGIC ;
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--    empty   : OUT STD_LOGIC ;
177 
--    full    : OUT STD_LOGIC ;
178 
--    q       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0) ;
179 4 danv 
--    usedw   : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
180 2 danv 
--  );
181 
--  END COMPONENT;
182 
--
183 
--  COMPONENT ip_arria10_e3sge3_fifo_dc IS
184 
--  GENERIC (
185 
--    g_use_eab   : STRING := "ON";
186 
--    g_dat_w     : NATURAL := 20;
187 
--    g_nof_words : NATURAL := 1024
188 
--  );
189 
--  PORT (
190 
--    aclr    : IN STD_LOGIC  := '0';
191 
--    data    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
192 
--    rdclk   : IN STD_LOGIC ;
193 
--    rdreq   : IN STD_LOGIC ;
194 
--    wrclk   : IN STD_LOGIC ;
195 
--    wrreq   : IN STD_LOGIC ;
196 
--    q       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
197 
--    rdempty : OUT STD_LOGIC ;
198 4 danv 
--    rdusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0);
199 2 danv 
--    wrfull  : OUT STD_LOGIC ;
200 4 danv 
--    wrusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
201 2 danv 
--  );
202 
--  END COMPONENT;
203 
--
204 
--  COMPONENT ip_arria10_e3sge3_fifo_dc_mixed_widths IS
205 
--  GENERIC (
206 
--    g_nof_words : NATURAL := 1024;  -- FIFO size in nof wr_dat words
207 
--    g_wrdat_w   : NATURAL := 20;
208 
--    g_rddat_w   : NATURAL := 10
209 
--  );
210 
--  PORT (
211 
--    aclr    : IN STD_LOGIC  := '0';
212 
--    data    : IN STD_LOGIC_VECTOR (g_wrdat_w-1 DOWNTO 0);
213 
--    rdclk   : IN STD_LOGIC ;
214 
--    rdreq   : IN STD_LOGIC ;
215 
--    wrclk   : IN STD_LOGIC ;
216 
--    wrreq   : IN STD_LOGIC ;
217 
--    q       : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
218 
--    rdempty : OUT STD_LOGIC ;
219 4 danv 
--    rdusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
220 2 danv 
--    wrfull  : OUT STD_LOGIC ;
221 4 danv 
--    wrusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
222 2 danv 
--  );
223 
--  END COMPONENT;
224 
--
225 
--  -----------------------------------------------------------------------------
226 
--  -- ip_arria10_e1sg
227 
--  -----------------------------------------------------------------------------
228 
--
229 
--  COMPONENT ip_arria10_e1sg_fifo_sc IS
230 
--  GENERIC (
231 
--    g_use_eab   : STRING := "ON";
232 
--    g_dat_w     : NATURAL := 20;
233 
--    g_nof_words : NATURAL := 1024
234 
--  );
235 
--  PORT (
236 
--    aclr    : IN STD_LOGIC ;
237 
--    clock   : IN STD_LOGIC ;
238 
--    data    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
239 
--    rdreq   : IN STD_LOGIC ;
240 
--    wrreq   : IN STD_LOGIC ;
241 
--    empty   : OUT STD_LOGIC ;
242 
--    full    : OUT STD_LOGIC ;
243 
--    q       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0) ;
244 4 danv 
--    usedw   : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
245 2 danv 
--  );
246 
--  END COMPONENT;
247 
--
248 
--  COMPONENT ip_arria10_e1sg_fifo_dc IS
249 
--  GENERIC (
250 
--    g_use_eab   : STRING := "ON";
251 
--    g_dat_w     : NATURAL := 20;
252 
--    g_nof_words : NATURAL := 1024
253 
--  );
254 
--  PORT (
255 
--    aclr    : IN STD_LOGIC  := '0';
256 
--    data    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
257 
--    rdclk   : IN STD_LOGIC ;
258 
--    rdreq   : IN STD_LOGIC ;
259 
--    wrclk   : IN STD_LOGIC ;
260 
--    wrreq   : IN STD_LOGIC ;
261 
--    q       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
262 
--    rdempty : OUT STD_LOGIC ;
263 4 danv 
--    rdusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0);
264 2 danv 
--    wrfull  : OUT STD_LOGIC ;
265 4 danv 
--    wrusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
266 2 danv 
--  );
267 
--  END COMPONENT;
268 
--
269 
--  COMPONENT ip_arria10_e1sg_fifo_dc_mixed_widths IS
270 
--  GENERIC (
271 
--    g_nof_words : NATURAL := 1024;  -- FIFO size in nof wr_dat words
272 
--    g_wrdat_w   : NATURAL := 20;
273 
--    g_rddat_w   : NATURAL := 10
274 
--  );
275 
--  PORT (
276 
--    aclr    : IN STD_LOGIC  := '0';
277 
--    data    : IN STD_LOGIC_VECTOR (g_wrdat_w-1 DOWNTO 0);
278 
--    rdclk   : IN STD_LOGIC ;
279 
--    rdreq   : IN STD_LOGIC ;
280 
--    wrclk   : IN STD_LOGIC ;
281 
--    wrreq   : IN STD_LOGIC ;
282 
--    q       : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
283 
--    rdempty : OUT STD_LOGIC ;
284 4 danv 
--    rdusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
285 2 danv 
--    wrfull  : OUT STD_LOGIC ;
286 4 danv 
--    wrusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
287 2 danv 
--  );
288 
--  END COMPONENT;
289 
 
290 
 
291 
END tech_fifo_component_pkg;

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