1 |
6 |
ashematian |
|HD_ADPCM_Codec
|
2 |
|
|
CLOCK_IN => ADPCM_Decoder_1_Bit:u6.CLOCK_IN
|
3 |
|
|
CLOCK_IN => ADPCM_Decoder_1_Bit:u5.CLOCK_IN
|
4 |
|
|
CLOCK_IN => Flash_Memory_Driver:u4.CLOCK_IN
|
5 |
|
|
CLOCK_IN => I2S_Driver:u3.CLOCK_IN
|
6 |
|
|
CLOCK_IN => I2C_Stream_Counter[2].CLK
|
7 |
|
|
CLOCK_IN => I2C_Stream_Counter[1].CLK
|
8 |
|
|
CLOCK_IN => I2C_Stream_Counter[0].CLK
|
9 |
|
|
CLOCK_IN => Counter[24].CLK
|
10 |
|
|
CLOCK_IN => Counter[23].CLK
|
11 |
|
|
CLOCK_IN => Counter[22].CLK
|
12 |
|
|
CLOCK_IN => Counter[21].CLK
|
13 |
|
|
CLOCK_IN => Counter[20].CLK
|
14 |
|
|
CLOCK_IN => Counter[19].CLK
|
15 |
|
|
CLOCK_IN => Counter[18].CLK
|
16 |
|
|
CLOCK_IN => Counter[17].CLK
|
17 |
|
|
CLOCK_IN => Counter[16].CLK
|
18 |
|
|
CLOCK_IN => Counter[15].CLK
|
19 |
|
|
CLOCK_IN => Counter[14].CLK
|
20 |
|
|
CLOCK_IN => Counter[13].CLK
|
21 |
|
|
CLOCK_IN => Counter[12].CLK
|
22 |
|
|
CLOCK_IN => Counter[11].CLK
|
23 |
|
|
CLOCK_IN => Counter[10].CLK
|
24 |
|
|
CLOCK_IN => Counter[9].CLK
|
25 |
|
|
CLOCK_IN => Counter[8].CLK
|
26 |
|
|
CLOCK_IN => Counter[7].CLK
|
27 |
|
|
CLOCK_IN => Counter[6].CLK
|
28 |
|
|
CLOCK_IN => Counter[5].CLK
|
29 |
|
|
CLOCK_IN => Counter[4].CLK
|
30 |
|
|
CLOCK_IN => Counter[3].CLK
|
31 |
|
|
CLOCK_IN => Counter[2].CLK
|
32 |
|
|
CLOCK_IN => Counter[1].CLK
|
33 |
|
|
CLOCK_IN => Counter[0].CLK
|
34 |
|
|
CLOCK_IN => AUDIO_CODEC_VOLUME[6].CLK
|
35 |
|
|
CLOCK_IN => AUDIO_CODEC_VOLUME[5].CLK
|
36 |
|
|
CLOCK_IN => AUDIO_CODEC_VOLUME[4].CLK
|
37 |
|
|
CLOCK_IN => AUDIO_CODEC_VOLUME[3].CLK
|
38 |
|
|
CLOCK_IN => AUDIO_CODEC_VOLUME[2].CLK
|
39 |
|
|
CLOCK_IN => AUDIO_CODEC_VOLUME[1].CLK
|
40 |
|
|
CLOCK_IN => AUDIO_CODEC_VOLUME[0].CLK
|
41 |
|
|
CLOCK_IN => I2C_REGISTER_ADDRESS[7].CLK
|
42 |
|
|
CLOCK_IN => I2C_REGISTER_ADDRESS[6].CLK
|
43 |
|
|
CLOCK_IN => I2C_REGISTER_ADDRESS[5].CLK
|
44 |
|
|
CLOCK_IN => I2C_REGISTER_ADDRESS[4].CLK
|
45 |
|
|
CLOCK_IN => I2C_REGISTER_ADDRESS[3].CLK
|
46 |
|
|
CLOCK_IN => I2C_REGISTER_ADDRESS[2].CLK
|
47 |
|
|
CLOCK_IN => I2C_REGISTER_ADDRESS[1].CLK
|
48 |
|
|
CLOCK_IN => I2C_REGISTER_ADDRESS[0].CLK
|
49 |
|
|
CLOCK_IN => I2C_REGISTER_DATA[7].CLK
|
50 |
|
|
CLOCK_IN => I2C_REGISTER_DATA[6].CLK
|
51 |
|
|
CLOCK_IN => I2C_REGISTER_DATA[5].CLK
|
52 |
|
|
CLOCK_IN => I2C_REGISTER_DATA[4].CLK
|
53 |
|
|
CLOCK_IN => I2C_REGISTER_DATA[3].CLK
|
54 |
|
|
CLOCK_IN => I2C_REGISTER_DATA[2].CLK
|
55 |
|
|
CLOCK_IN => I2C_REGISTER_DATA[1].CLK
|
56 |
|
|
CLOCK_IN => I2C_REGISTER_DATA[0].CLK
|
57 |
|
|
CLOCK_IN => I2C_ACTIVE_IN.CLK
|
58 |
|
|
CLOCK_IN => I2S_ACTIVE_IN.CLK
|
59 |
|
|
CLOCK_IN => I2S_CORE_CLOCK.CLK
|
60 |
|
|
CLOCK_IN => I2C_Driver:u2.CLOCK_IN
|
61 |
|
|
S_SEVEN_SEGMENT_1_OUT[0] <= SevenSegments_Driver:u0.SEVEN_SEGMENT_1_OUT[0]
|
62 |
|
|
S_SEVEN_SEGMENT_1_OUT[1] <= SevenSegments_Driver:u0.SEVEN_SEGMENT_1_OUT[1]
|
63 |
|
|
S_SEVEN_SEGMENT_1_OUT[2] <= SevenSegments_Driver:u0.SEVEN_SEGMENT_1_OUT[2]
|
64 |
|
|
S_SEVEN_SEGMENT_1_OUT[3] <= SevenSegments_Driver:u0.SEVEN_SEGMENT_1_OUT[3]
|
65 |
|
|
S_SEVEN_SEGMENT_1_OUT[4] <= SevenSegments_Driver:u0.SEVEN_SEGMENT_1_OUT[4]
|
66 |
|
|
S_SEVEN_SEGMENT_1_OUT[5] <= SevenSegments_Driver:u0.SEVEN_SEGMENT_1_OUT[5]
|
67 |
|
|
S_SEVEN_SEGMENT_1_OUT[6] <= SevenSegments_Driver:u0.SEVEN_SEGMENT_1_OUT[6]
|
68 |
|
|
S_SEVEN_SEGMENT_2_OUT[0] <= SevenSegments_Driver:u0.SEVEN_SEGMENT_2_OUT[0]
|
69 |
|
|
S_SEVEN_SEGMENT_2_OUT[1] <= SevenSegments_Driver:u0.SEVEN_SEGMENT_2_OUT[1]
|
70 |
|
|
S_SEVEN_SEGMENT_2_OUT[2] <= SevenSegments_Driver:u0.SEVEN_SEGMENT_2_OUT[2]
|
71 |
|
|
S_SEVEN_SEGMENT_2_OUT[3] <= SevenSegments_Driver:u0.SEVEN_SEGMENT_2_OUT[3]
|
72 |
|
|
S_SEVEN_SEGMENT_2_OUT[4] <= SevenSegments_Driver:u0.SEVEN_SEGMENT_2_OUT[4]
|
73 |
|
|
S_SEVEN_SEGMENT_2_OUT[5] <= SevenSegments_Driver:u0.SEVEN_SEGMENT_2_OUT[5]
|
74 |
|
|
S_SEVEN_SEGMENT_2_OUT[6] <= SevenSegments_Driver:u0.SEVEN_SEGMENT_2_OUT[6]
|
75 |
|
|
S_SEVEN_SEGMENT_3_OUT[0] <= SevenSegments_Driver:u0.SEVEN_SEGMENT_3_OUT[0]
|
76 |
|
|
S_SEVEN_SEGMENT_3_OUT[1] <= SevenSegments_Driver:u0.SEVEN_SEGMENT_3_OUT[1]
|
77 |
|
|
S_SEVEN_SEGMENT_3_OUT[2] <= SevenSegments_Driver:u0.SEVEN_SEGMENT_3_OUT[2]
|
78 |
|
|
S_SEVEN_SEGMENT_3_OUT[3] <= SevenSegments_Driver:u0.SEVEN_SEGMENT_3_OUT[3]
|
79 |
|
|
S_SEVEN_SEGMENT_3_OUT[4] <= SevenSegments_Driver:u0.SEVEN_SEGMENT_3_OUT[4]
|
80 |
|
|
S_SEVEN_SEGMENT_3_OUT[5] <= SevenSegments_Driver:u0.SEVEN_SEGMENT_3_OUT[5]
|
81 |
|
|
S_SEVEN_SEGMENT_3_OUT[6] <= SevenSegments_Driver:u0.SEVEN_SEGMENT_3_OUT[6]
|
82 |
|
|
S_SEVEN_SEGMENT_4_OUT[0] <= SevenSegments_Driver:u0.SEVEN_SEGMENT_4_OUT[0]
|
83 |
|
|
S_SEVEN_SEGMENT_4_OUT[1] <= SevenSegments_Driver:u0.SEVEN_SEGMENT_4_OUT[1]
|
84 |
|
|
S_SEVEN_SEGMENT_4_OUT[2] <= SevenSegments_Driver:u0.SEVEN_SEGMENT_4_OUT[2]
|
85 |
|
|
S_SEVEN_SEGMENT_4_OUT[3] <= SevenSegments_Driver:u0.SEVEN_SEGMENT_4_OUT[3]
|
86 |
|
|
S_SEVEN_SEGMENT_4_OUT[4] <= SevenSegments_Driver:u0.SEVEN_SEGMENT_4_OUT[4]
|
87 |
|
|
S_SEVEN_SEGMENT_4_OUT[5] <= SevenSegments_Driver:u0.SEVEN_SEGMENT_4_OUT[5]
|
88 |
|
|
S_SEVEN_SEGMENT_4_OUT[6] <= SevenSegments_Driver:u0.SEVEN_SEGMENT_4_OUT[6]
|
89 |
|
|
S_RED_LEDS_OUT[0] <= LEDs_Bar_Driver:u1.LEDS_OUT[0]
|
90 |
|
|
S_RED_LEDS_OUT[1] <= LEDs_Bar_Driver:u1.LEDS_OUT[1]
|
91 |
|
|
S_RED_LEDS_OUT[2] <= LEDs_Bar_Driver:u1.LEDS_OUT[2]
|
92 |
|
|
S_RED_LEDS_OUT[3] <= LEDs_Bar_Driver:u1.LEDS_OUT[3]
|
93 |
|
|
S_RED_LEDS_OUT[4] <= LEDs_Bar_Driver:u1.LEDS_OUT[4]
|
94 |
|
|
S_RED_LEDS_OUT[5] <= LEDs_Bar_Driver:u1.LEDS_OUT[5]
|
95 |
|
|
S_RED_LEDS_OUT[6] <= LEDs_Bar_Driver:u1.LEDS_OUT[6]
|
96 |
|
|
S_RED_LEDS_OUT[7] <= LEDs_Bar_Driver:u1.LEDS_OUT[7]
|
97 |
|
|
S_RED_LEDS_OUT[8] <= LEDs_Bar_Driver:u1.LEDS_OUT[8]
|
98 |
|
|
S_RED_LEDS_OUT[9] <= LEDs_Bar_Driver:u1.LEDS_OUT[9]
|
99 |
|
|
I2C_CLOCK_OUT <= I2C_Driver:u2.I2C_CLOCK
|
100 |
|
|
I2C_DATA_INOUT <= I2C_Driver:u2.I2C_DATA
|
101 |
|
|
I2S_LEFT_RIGHT_CLOCK_OUT <= I2S_Driver:u3.I2S_LEFT_RIGHT_CLOCK_OUT
|
102 |
|
|
I2S_CLOCK_OUT <= I2S_Driver:u3.I2S_CLOCK_OUT
|
103 |
|
|
I2S_DATA_INOUT <= I2S_Driver:u3.I2S_DATA_INOUT
|
104 |
|
|
I2S_CORE_CLOCK_OUT <= I2S_CORE_CLOCK.DB_MAX_OUTPUT_PORT_TYPE
|
105 |
|
|
SWITCH_0 => ~NO_FANOUT~
|
106 |
|
|
KEY_0 => AUDIO_CODEC_VOLUME~27.OUTPUTSELECT
|
107 |
|
|
KEY_0 => AUDIO_CODEC_VOLUME~26.OUTPUTSELECT
|
108 |
|
|
KEY_0 => AUDIO_CODEC_VOLUME~25.OUTPUTSELECT
|
109 |
|
|
KEY_0 => AUDIO_CODEC_VOLUME~24.OUTPUTSELECT
|
110 |
|
|
KEY_0 => AUDIO_CODEC_VOLUME~23.OUTPUTSELECT
|
111 |
|
|
KEY_0 => AUDIO_CODEC_VOLUME~22.OUTPUTSELECT
|
112 |
|
|
KEY_0 => AUDIO_CODEC_VOLUME~21.OUTPUTSELECT
|
113 |
|
|
KEY_1 => AUDIO_CODEC_VOLUME~20.OUTPUTSELECT
|
114 |
|
|
KEY_1 => AUDIO_CODEC_VOLUME~19.OUTPUTSELECT
|
115 |
|
|
KEY_1 => AUDIO_CODEC_VOLUME~18.OUTPUTSELECT
|
116 |
|
|
KEY_1 => AUDIO_CODEC_VOLUME~17.OUTPUTSELECT
|
117 |
|
|
KEY_1 => AUDIO_CODEC_VOLUME~16.OUTPUTSELECT
|
118 |
|
|
KEY_1 => AUDIO_CODEC_VOLUME~15.OUTPUTSELECT
|
119 |
|
|
KEY_1 => AUDIO_CODEC_VOLUME~14.OUTPUTSELECT
|
120 |
|
|
FLASH_MEMORY_ADDRESS_OUT[0] <= Flash_Memory_Driver:u4.FLASH_MEMORY_ADDRESS[0]
|
121 |
|
|
FLASH_MEMORY_ADDRESS_OUT[1] <= Flash_Memory_Driver:u4.FLASH_MEMORY_ADDRESS[1]
|
122 |
|
|
FLASH_MEMORY_ADDRESS_OUT[2] <= Flash_Memory_Driver:u4.FLASH_MEMORY_ADDRESS[2]
|
123 |
|
|
FLASH_MEMORY_ADDRESS_OUT[3] <= Flash_Memory_Driver:u4.FLASH_MEMORY_ADDRESS[3]
|
124 |
|
|
FLASH_MEMORY_ADDRESS_OUT[4] <= Flash_Memory_Driver:u4.FLASH_MEMORY_ADDRESS[4]
|
125 |
|
|
FLASH_MEMORY_ADDRESS_OUT[5] <= Flash_Memory_Driver:u4.FLASH_MEMORY_ADDRESS[5]
|
126 |
|
|
FLASH_MEMORY_ADDRESS_OUT[6] <= Flash_Memory_Driver:u4.FLASH_MEMORY_ADDRESS[6]
|
127 |
|
|
FLASH_MEMORY_ADDRESS_OUT[7] <= Flash_Memory_Driver:u4.FLASH_MEMORY_ADDRESS[7]
|
128 |
|
|
FLASH_MEMORY_ADDRESS_OUT[8] <= Flash_Memory_Driver:u4.FLASH_MEMORY_ADDRESS[8]
|
129 |
|
|
FLASH_MEMORY_ADDRESS_OUT[9] <= Flash_Memory_Driver:u4.FLASH_MEMORY_ADDRESS[9]
|
130 |
|
|
FLASH_MEMORY_ADDRESS_OUT[10] <= Flash_Memory_Driver:u4.FLASH_MEMORY_ADDRESS[10]
|
131 |
|
|
FLASH_MEMORY_ADDRESS_OUT[11] <= Flash_Memory_Driver:u4.FLASH_MEMORY_ADDRESS[11]
|
132 |
|
|
FLASH_MEMORY_ADDRESS_OUT[12] <= Flash_Memory_Driver:u4.FLASH_MEMORY_ADDRESS[12]
|
133 |
|
|
FLASH_MEMORY_ADDRESS_OUT[13] <= Flash_Memory_Driver:u4.FLASH_MEMORY_ADDRESS[13]
|
134 |
|
|
FLASH_MEMORY_ADDRESS_OUT[14] <= Flash_Memory_Driver:u4.FLASH_MEMORY_ADDRESS[14]
|
135 |
|
|
FLASH_MEMORY_ADDRESS_OUT[15] <= Flash_Memory_Driver:u4.FLASH_MEMORY_ADDRESS[15]
|
136 |
|
|
FLASH_MEMORY_ADDRESS_OUT[16] <= Flash_Memory_Driver:u4.FLASH_MEMORY_ADDRESS[16]
|
137 |
|
|
FLASH_MEMORY_ADDRESS_OUT[17] <= Flash_Memory_Driver:u4.FLASH_MEMORY_ADDRESS[17]
|
138 |
|
|
FLASH_MEMORY_ADDRESS_OUT[18] <= Flash_Memory_Driver:u4.FLASH_MEMORY_ADDRESS[18]
|
139 |
|
|
FLASH_MEMORY_ADDRESS_OUT[19] <= Flash_Memory_Driver:u4.FLASH_MEMORY_ADDRESS[19]
|
140 |
|
|
FLASH_MEMORY_ADDRESS_OUT[20] <= Flash_Memory_Driver:u4.FLASH_MEMORY_ADDRESS[20]
|
141 |
|
|
FLASH_MEMORY_ADDRESS_OUT[21] <= Flash_Memory_Driver:u4.FLASH_MEMORY_ADDRESS[21]
|
142 |
|
|
FLASH_MEMORY_DATA_INOUT[0] <= Flash_Memory_Driver:u4.FLASH_MEMORY_DATA[0]
|
143 |
|
|
FLASH_MEMORY_DATA_INOUT[1] <= Flash_Memory_Driver:u4.FLASH_MEMORY_DATA[1]
|
144 |
|
|
FLASH_MEMORY_DATA_INOUT[2] <= Flash_Memory_Driver:u4.FLASH_MEMORY_DATA[2]
|
145 |
|
|
FLASH_MEMORY_DATA_INOUT[3] <= Flash_Memory_Driver:u4.FLASH_MEMORY_DATA[3]
|
146 |
|
|
FLASH_MEMORY_DATA_INOUT[4] <= Flash_Memory_Driver:u4.FLASH_MEMORY_DATA[4]
|
147 |
|
|
FLASH_MEMORY_DATA_INOUT[5] <= Flash_Memory_Driver:u4.FLASH_MEMORY_DATA[5]
|
148 |
|
|
FLASH_MEMORY_DATA_INOUT[6] <= Flash_Memory_Driver:u4.FLASH_MEMORY_DATA[6]
|
149 |
|
|
FLASH_MEMORY_DATA_INOUT[7] <= Flash_Memory_Driver:u4.FLASH_MEMORY_DATA[7]
|
150 |
|
|
FLASH_MEMORY_nWE_OUT <= Flash_Memory_Driver:u4.FLASH_MEMORY_nWE
|
151 |
|
|
FLASH_MEMORY_nOE_OUT <= Flash_Memory_Driver:u4.FLASH_MEMORY_nOE
|
152 |
|
|
FLASH_MEMORY_nRESET_OUT <= Flash_Memory_Driver:u4.FLASH_MEMORY_nRESET
|
153 |
|
|
FLASH_MEMORY_nCE_OUT <= Flash_Memory_Driver:u4.FLASH_MEMORY_nCE
|
154 |
|
|
|
155 |
|
|
|
156 |
|
|
|HD_ADPCM_Codec|SevenSegments_Driver:u0
|
157 |
|
|
DIGIT_1_IN[0] => Mux6.IN19
|
158 |
|
|
DIGIT_1_IN[0] => Mux5.IN19
|
159 |
|
|
DIGIT_1_IN[0] => Mux4.IN19
|
160 |
|
|
DIGIT_1_IN[0] => Mux3.IN19
|
161 |
|
|
DIGIT_1_IN[0] => Mux2.IN19
|
162 |
|
|
DIGIT_1_IN[0] => Mux1.IN19
|
163 |
|
|
DIGIT_1_IN[0] => Mux0.IN19
|
164 |
|
|
DIGIT_1_IN[1] => Mux6.IN18
|
165 |
|
|
DIGIT_1_IN[1] => Mux5.IN18
|
166 |
|
|
DIGIT_1_IN[1] => Mux4.IN18
|
167 |
|
|
DIGIT_1_IN[1] => Mux3.IN18
|
168 |
|
|
DIGIT_1_IN[1] => Mux2.IN18
|
169 |
|
|
DIGIT_1_IN[1] => Mux1.IN18
|
170 |
|
|
DIGIT_1_IN[1] => Mux0.IN18
|
171 |
|
|
DIGIT_1_IN[2] => Mux6.IN17
|
172 |
|
|
DIGIT_1_IN[2] => Mux5.IN17
|
173 |
|
|
DIGIT_1_IN[2] => Mux4.IN17
|
174 |
|
|
DIGIT_1_IN[2] => Mux3.IN17
|
175 |
|
|
DIGIT_1_IN[2] => Mux2.IN17
|
176 |
|
|
DIGIT_1_IN[2] => Mux1.IN17
|
177 |
|
|
DIGIT_1_IN[2] => Mux0.IN17
|
178 |
|
|
DIGIT_1_IN[3] => Mux6.IN16
|
179 |
|
|
DIGIT_1_IN[3] => Mux5.IN16
|
180 |
|
|
DIGIT_1_IN[3] => Mux4.IN16
|
181 |
|
|
DIGIT_1_IN[3] => Mux3.IN16
|
182 |
|
|
DIGIT_1_IN[3] => Mux2.IN16
|
183 |
|
|
DIGIT_1_IN[3] => Mux1.IN16
|
184 |
|
|
DIGIT_1_IN[3] => Mux0.IN16
|
185 |
|
|
DIGIT_2_IN[0] => Mux13.IN19
|
186 |
|
|
DIGIT_2_IN[0] => Mux12.IN19
|
187 |
|
|
DIGIT_2_IN[0] => Mux11.IN19
|
188 |
|
|
DIGIT_2_IN[0] => Mux10.IN19
|
189 |
|
|
DIGIT_2_IN[0] => Mux9.IN19
|
190 |
|
|
DIGIT_2_IN[0] => Mux8.IN19
|
191 |
|
|
DIGIT_2_IN[0] => Mux7.IN19
|
192 |
|
|
DIGIT_2_IN[1] => Mux13.IN18
|
193 |
|
|
DIGIT_2_IN[1] => Mux12.IN18
|
194 |
|
|
DIGIT_2_IN[1] => Mux11.IN18
|
195 |
|
|
DIGIT_2_IN[1] => Mux10.IN18
|
196 |
|
|
DIGIT_2_IN[1] => Mux9.IN18
|
197 |
|
|
DIGIT_2_IN[1] => Mux8.IN18
|
198 |
|
|
DIGIT_2_IN[1] => Mux7.IN18
|
199 |
|
|
DIGIT_2_IN[2] => Mux13.IN17
|
200 |
|
|
DIGIT_2_IN[2] => Mux12.IN17
|
201 |
|
|
DIGIT_2_IN[2] => Mux11.IN17
|
202 |
|
|
DIGIT_2_IN[2] => Mux10.IN17
|
203 |
|
|
DIGIT_2_IN[2] => Mux9.IN17
|
204 |
|
|
DIGIT_2_IN[2] => Mux8.IN17
|
205 |
|
|
DIGIT_2_IN[2] => Mux7.IN17
|
206 |
|
|
DIGIT_2_IN[3] => Mux13.IN16
|
207 |
|
|
DIGIT_2_IN[3] => Mux12.IN16
|
208 |
|
|
DIGIT_2_IN[3] => Mux11.IN16
|
209 |
|
|
DIGIT_2_IN[3] => Mux10.IN16
|
210 |
|
|
DIGIT_2_IN[3] => Mux9.IN16
|
211 |
|
|
DIGIT_2_IN[3] => Mux8.IN16
|
212 |
|
|
DIGIT_2_IN[3] => Mux7.IN16
|
213 |
|
|
DIGIT_3_IN[0] => Mux20.IN19
|
214 |
|
|
DIGIT_3_IN[0] => Mux19.IN19
|
215 |
|
|
DIGIT_3_IN[0] => Mux18.IN19
|
216 |
|
|
DIGIT_3_IN[0] => Mux17.IN19
|
217 |
|
|
DIGIT_3_IN[0] => Mux16.IN19
|
218 |
|
|
DIGIT_3_IN[0] => Mux15.IN19
|
219 |
|
|
DIGIT_3_IN[0] => Mux14.IN19
|
220 |
|
|
DIGIT_3_IN[1] => Mux20.IN18
|
221 |
|
|
DIGIT_3_IN[1] => Mux19.IN18
|
222 |
|
|
DIGIT_3_IN[1] => Mux18.IN18
|
223 |
|
|
DIGIT_3_IN[1] => Mux17.IN18
|
224 |
|
|
DIGIT_3_IN[1] => Mux16.IN18
|
225 |
|
|
DIGIT_3_IN[1] => Mux15.IN18
|
226 |
|
|
DIGIT_3_IN[1] => Mux14.IN18
|
227 |
|
|
DIGIT_3_IN[2] => Mux20.IN17
|
228 |
|
|
DIGIT_3_IN[2] => Mux19.IN17
|
229 |
|
|
DIGIT_3_IN[2] => Mux18.IN17
|
230 |
|
|
DIGIT_3_IN[2] => Mux17.IN17
|
231 |
|
|
DIGIT_3_IN[2] => Mux16.IN17
|
232 |
|
|
DIGIT_3_IN[2] => Mux15.IN17
|
233 |
|
|
DIGIT_3_IN[2] => Mux14.IN17
|
234 |
|
|
DIGIT_3_IN[3] => Mux20.IN16
|
235 |
|
|
DIGIT_3_IN[3] => Mux19.IN16
|
236 |
|
|
DIGIT_3_IN[3] => Mux18.IN16
|
237 |
|
|
DIGIT_3_IN[3] => Mux17.IN16
|
238 |
|
|
DIGIT_3_IN[3] => Mux16.IN16
|
239 |
|
|
DIGIT_3_IN[3] => Mux15.IN16
|
240 |
|
|
DIGIT_3_IN[3] => Mux14.IN16
|
241 |
|
|
DIGIT_4_IN[0] => Mux27.IN19
|
242 |
|
|
DIGIT_4_IN[0] => Mux26.IN19
|
243 |
|
|
DIGIT_4_IN[0] => Mux25.IN19
|
244 |
|
|
DIGIT_4_IN[0] => Mux24.IN19
|
245 |
|
|
DIGIT_4_IN[0] => Mux23.IN19
|
246 |
|
|
DIGIT_4_IN[0] => Mux22.IN19
|
247 |
|
|
DIGIT_4_IN[0] => Mux21.IN19
|
248 |
|
|
DIGIT_4_IN[1] => Mux27.IN18
|
249 |
|
|
DIGIT_4_IN[1] => Mux26.IN18
|
250 |
|
|
DIGIT_4_IN[1] => Mux25.IN18
|
251 |
|
|
DIGIT_4_IN[1] => Mux24.IN18
|
252 |
|
|
DIGIT_4_IN[1] => Mux23.IN18
|
253 |
|
|
DIGIT_4_IN[1] => Mux22.IN18
|
254 |
|
|
DIGIT_4_IN[1] => Mux21.IN18
|
255 |
|
|
DIGIT_4_IN[2] => Mux27.IN17
|
256 |
|
|
DIGIT_4_IN[2] => Mux26.IN17
|
257 |
|
|
DIGIT_4_IN[2] => Mux25.IN17
|
258 |
|
|
DIGIT_4_IN[2] => Mux24.IN17
|
259 |
|
|
DIGIT_4_IN[2] => Mux23.IN17
|
260 |
|
|
DIGIT_4_IN[2] => Mux22.IN17
|
261 |
|
|
DIGIT_4_IN[2] => Mux21.IN17
|
262 |
|
|
DIGIT_4_IN[3] => Mux27.IN16
|
263 |
|
|
DIGIT_4_IN[3] => Mux26.IN16
|
264 |
|
|
DIGIT_4_IN[3] => Mux25.IN16
|
265 |
|
|
DIGIT_4_IN[3] => Mux24.IN16
|
266 |
|
|
DIGIT_4_IN[3] => Mux23.IN16
|
267 |
|
|
DIGIT_4_IN[3] => Mux22.IN16
|
268 |
|
|
DIGIT_4_IN[3] => Mux21.IN16
|
269 |
|
|
SEVEN_SEGMENT_1_OUT[0] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE
|
270 |
|
|
SEVEN_SEGMENT_1_OUT[1] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
|
271 |
|
|
SEVEN_SEGMENT_1_OUT[2] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
|
272 |
|
|
SEVEN_SEGMENT_1_OUT[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
|
273 |
|
|
SEVEN_SEGMENT_1_OUT[4] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
|
274 |
|
|
SEVEN_SEGMENT_1_OUT[5] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
|
275 |
|
|
SEVEN_SEGMENT_1_OUT[6] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
|
276 |
|
|
SEVEN_SEGMENT_2_OUT[0] <= Mux7.DB_MAX_OUTPUT_PORT_TYPE
|
277 |
|
|
SEVEN_SEGMENT_2_OUT[1] <= Mux8.DB_MAX_OUTPUT_PORT_TYPE
|
278 |
|
|
SEVEN_SEGMENT_2_OUT[2] <= Mux9.DB_MAX_OUTPUT_PORT_TYPE
|
279 |
|
|
SEVEN_SEGMENT_2_OUT[3] <= Mux10.DB_MAX_OUTPUT_PORT_TYPE
|
280 |
|
|
SEVEN_SEGMENT_2_OUT[4] <= Mux11.DB_MAX_OUTPUT_PORT_TYPE
|
281 |
|
|
SEVEN_SEGMENT_2_OUT[5] <= Mux12.DB_MAX_OUTPUT_PORT_TYPE
|
282 |
|
|
SEVEN_SEGMENT_2_OUT[6] <= Mux13.DB_MAX_OUTPUT_PORT_TYPE
|
283 |
|
|
SEVEN_SEGMENT_3_OUT[0] <= Mux14.DB_MAX_OUTPUT_PORT_TYPE
|
284 |
|
|
SEVEN_SEGMENT_3_OUT[1] <= Mux15.DB_MAX_OUTPUT_PORT_TYPE
|
285 |
|
|
SEVEN_SEGMENT_3_OUT[2] <= Mux16.DB_MAX_OUTPUT_PORT_TYPE
|
286 |
|
|
SEVEN_SEGMENT_3_OUT[3] <= Mux17.DB_MAX_OUTPUT_PORT_TYPE
|
287 |
|
|
SEVEN_SEGMENT_3_OUT[4] <= Mux18.DB_MAX_OUTPUT_PORT_TYPE
|
288 |
|
|
SEVEN_SEGMENT_3_OUT[5] <= Mux19.DB_MAX_OUTPUT_PORT_TYPE
|
289 |
|
|
SEVEN_SEGMENT_3_OUT[6] <= Mux20.DB_MAX_OUTPUT_PORT_TYPE
|
290 |
|
|
SEVEN_SEGMENT_4_OUT[0] <= Mux21.DB_MAX_OUTPUT_PORT_TYPE
|
291 |
|
|
SEVEN_SEGMENT_4_OUT[1] <= Mux22.DB_MAX_OUTPUT_PORT_TYPE
|
292 |
|
|
SEVEN_SEGMENT_4_OUT[2] <= Mux23.DB_MAX_OUTPUT_PORT_TYPE
|
293 |
|
|
SEVEN_SEGMENT_4_OUT[3] <= Mux24.DB_MAX_OUTPUT_PORT_TYPE
|
294 |
|
|
SEVEN_SEGMENT_4_OUT[4] <= Mux25.DB_MAX_OUTPUT_PORT_TYPE
|
295 |
|
|
SEVEN_SEGMENT_4_OUT[5] <= Mux26.DB_MAX_OUTPUT_PORT_TYPE
|
296 |
|
|
SEVEN_SEGMENT_4_OUT[6] <= Mux27.DB_MAX_OUTPUT_PORT_TYPE
|
297 |
|
|
|
298 |
|
|
|
299 |
|
|
|HD_ADPCM_Codec|LEDs_Bar_Driver:u1
|
300 |
|
|
SAMPLE_VALUE[0] => Mux7.IN10
|
301 |
|
|
SAMPLE_VALUE[0] => Mux6.IN19
|
302 |
|
|
SAMPLE_VALUE[0] => Mux4.IN19
|
303 |
|
|
SAMPLE_VALUE[0] => Mux2.IN19
|
304 |
|
|
SAMPLE_VALUE[0] => Mux0.IN19
|
305 |
|
|
SAMPLE_VALUE[1] => Mux8.IN5
|
306 |
|
|
SAMPLE_VALUE[1] => Mux7.IN9
|
307 |
|
|
SAMPLE_VALUE[1] => Mux6.IN18
|
308 |
|
|
SAMPLE_VALUE[1] => Mux5.IN10
|
309 |
|
|
SAMPLE_VALUE[1] => Mux4.IN18
|
310 |
|
|
SAMPLE_VALUE[1] => Mux2.IN18
|
311 |
|
|
SAMPLE_VALUE[1] => Mux1.IN10
|
312 |
|
|
SAMPLE_VALUE[1] => Mux0.IN18
|
313 |
|
|
SAMPLE_VALUE[2] => Mux6.IN17
|
314 |
|
|
SAMPLE_VALUE[2] => Mux5.IN9
|
315 |
|
|
SAMPLE_VALUE[2] => Mux4.IN17
|
316 |
|
|
SAMPLE_VALUE[2] => Mux3.IN5
|
317 |
|
|
SAMPLE_VALUE[2] => Mux2.IN17
|
318 |
|
|
SAMPLE_VALUE[2] => Mux1.IN9
|
319 |
|
|
SAMPLE_VALUE[2] => Mux0.IN17
|
320 |
|
|
SAMPLE_VALUE[3] => Mux8.IN4
|
321 |
|
|
SAMPLE_VALUE[3] => Mux7.IN8
|
322 |
|
|
SAMPLE_VALUE[3] => Mux6.IN16
|
323 |
|
|
SAMPLE_VALUE[3] => Mux5.IN8
|
324 |
|
|
SAMPLE_VALUE[3] => Mux4.IN16
|
325 |
|
|
SAMPLE_VALUE[3] => Mux3.IN4
|
326 |
|
|
SAMPLE_VALUE[3] => Mux2.IN16
|
327 |
|
|
SAMPLE_VALUE[3] => Mux1.IN8
|
328 |
|
|
SAMPLE_VALUE[3] => Mux0.IN16
|
329 |
|
|
SAMPLE_VALUE[3] => LEDS_OUT[7].DATAIN
|
330 |
|
|
LEDS_OUT[0] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE
|
331 |
|
|
LEDS_OUT[1] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
|
332 |
|
|
LEDS_OUT[2] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
|
333 |
|
|
LEDS_OUT[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
|
334 |
|
|
LEDS_OUT[4] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
|
335 |
|
|
LEDS_OUT[5] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
|
336 |
|
|
LEDS_OUT[6] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
|
337 |
|
|
LEDS_OUT[7] <= SAMPLE_VALUE[3].DB_MAX_OUTPUT_PORT_TYPE
|
338 |
|
|
LEDS_OUT[8] <= Mux7.DB_MAX_OUTPUT_PORT_TYPE
|
339 |
|
|
LEDS_OUT[9] <= Mux8.DB_MAX_OUTPUT_PORT_TYPE
|
340 |
|
|
|
341 |
|
|
|
342 |
|
|
|HD_ADPCM_Codec|I2C_Driver:u2
|
343 |
|
|
CLOCK_IN => I2C_Stream_Counter[6].CLK
|
344 |
|
|
CLOCK_IN => I2C_Stream_Counter[5].CLK
|
345 |
|
|
CLOCK_IN => I2C_Stream_Counter[4].CLK
|
346 |
|
|
CLOCK_IN => I2C_Stream_Counter[3].CLK
|
347 |
|
|
CLOCK_IN => I2C_Stream_Counter[2].CLK
|
348 |
|
|
CLOCK_IN => I2C_Stream_Counter[1].CLK
|
349 |
|
|
CLOCK_IN => I2C_Stream_Counter[0].CLK
|
350 |
|
|
CLOCK_IN => I2C_CLOCK~reg0.CLK
|
351 |
|
|
CLOCK_IN => I2C_DATA~reg0.CLK
|
352 |
|
|
CLOCK_IN => Counter[24].CLK
|
353 |
|
|
CLOCK_IN => Counter[23].CLK
|
354 |
|
|
CLOCK_IN => Counter[22].CLK
|
355 |
|
|
CLOCK_IN => Counter[21].CLK
|
356 |
|
|
CLOCK_IN => Counter[20].CLK
|
357 |
|
|
CLOCK_IN => Counter[19].CLK
|
358 |
|
|
CLOCK_IN => Counter[18].CLK
|
359 |
|
|
CLOCK_IN => Counter[17].CLK
|
360 |
|
|
CLOCK_IN => Counter[16].CLK
|
361 |
|
|
CLOCK_IN => Counter[15].CLK
|
362 |
|
|
CLOCK_IN => Counter[14].CLK
|
363 |
|
|
CLOCK_IN => Counter[13].CLK
|
364 |
|
|
CLOCK_IN => Counter[12].CLK
|
365 |
|
|
CLOCK_IN => Counter[11].CLK
|
366 |
|
|
CLOCK_IN => Counter[10].CLK
|
367 |
|
|
CLOCK_IN => Counter[9].CLK
|
368 |
|
|
CLOCK_IN => Counter[8].CLK
|
369 |
|
|
CLOCK_IN => Counter[7].CLK
|
370 |
|
|
CLOCK_IN => Counter[6].CLK
|
371 |
|
|
CLOCK_IN => Counter[5].CLK
|
372 |
|
|
CLOCK_IN => Counter[4].CLK
|
373 |
|
|
CLOCK_IN => Counter[3].CLK
|
374 |
|
|
CLOCK_IN => Counter[2].CLK
|
375 |
|
|
CLOCK_IN => Counter[1].CLK
|
376 |
|
|
CLOCK_IN => Counter[0].CLK
|
377 |
|
|
ACTIVE_IN => I2C_Stream_Counter~13.OUTPUTSELECT
|
378 |
|
|
ACTIVE_IN => I2C_Stream_Counter~12.OUTPUTSELECT
|
379 |
|
|
ACTIVE_IN => I2C_Stream_Counter~11.OUTPUTSELECT
|
380 |
|
|
ACTIVE_IN => I2C_Stream_Counter~10.OUTPUTSELECT
|
381 |
|
|
ACTIVE_IN => I2C_Stream_Counter~9.OUTPUTSELECT
|
382 |
|
|
ACTIVE_IN => I2C_Stream_Counter~8.OUTPUTSELECT
|
383 |
|
|
ACTIVE_IN => I2C_Stream_Counter~7.OUTPUTSELECT
|
384 |
|
|
SLAVE_ADDRESS[0] => Mux1.IN77
|
385 |
|
|
SLAVE_ADDRESS[0] => Mux1.IN78
|
386 |
|
|
SLAVE_ADDRESS[0] => Mux1.IN79
|
387 |
|
|
SLAVE_ADDRESS[1] => Mux1.IN74
|
388 |
|
|
SLAVE_ADDRESS[1] => Mux1.IN75
|
389 |
|
|
SLAVE_ADDRESS[1] => Mux1.IN76
|
390 |
|
|
SLAVE_ADDRESS[2] => Mux1.IN71
|
391 |
|
|
SLAVE_ADDRESS[2] => Mux1.IN72
|
392 |
|
|
SLAVE_ADDRESS[2] => Mux1.IN73
|
393 |
|
|
SLAVE_ADDRESS[3] => Mux1.IN68
|
394 |
|
|
SLAVE_ADDRESS[3] => Mux1.IN69
|
395 |
|
|
SLAVE_ADDRESS[3] => Mux1.IN70
|
396 |
|
|
SLAVE_ADDRESS[4] => Mux1.IN65
|
397 |
|
|
SLAVE_ADDRESS[4] => Mux1.IN66
|
398 |
|
|
SLAVE_ADDRESS[4] => Mux1.IN67
|
399 |
|
|
SLAVE_ADDRESS[5] => Mux1.IN62
|
400 |
|
|
SLAVE_ADDRESS[5] => Mux1.IN63
|
401 |
|
|
SLAVE_ADDRESS[5] => Mux1.IN64
|
402 |
|
|
SLAVE_ADDRESS[6] => Mux1.IN59
|
403 |
|
|
SLAVE_ADDRESS[6] => Mux1.IN60
|
404 |
|
|
SLAVE_ADDRESS[6] => Mux1.IN61
|
405 |
|
|
SLAVE_ADDRESS[7] => Mux1.IN56
|
406 |
|
|
SLAVE_ADDRESS[7] => Mux1.IN57
|
407 |
|
|
SLAVE_ADDRESS[7] => Mux1.IN58
|
408 |
|
|
REGISTER_ADDRESS[0] => Mux1.IN101
|
409 |
|
|
REGISTER_ADDRESS[0] => Mux1.IN102
|
410 |
|
|
REGISTER_ADDRESS[0] => Mux1.IN103
|
411 |
|
|
REGISTER_ADDRESS[1] => Mux1.IN98
|
412 |
|
|
REGISTER_ADDRESS[1] => Mux1.IN99
|
413 |
|
|
REGISTER_ADDRESS[1] => Mux1.IN100
|
414 |
|
|
REGISTER_ADDRESS[2] => Mux1.IN95
|
415 |
|
|
REGISTER_ADDRESS[2] => Mux1.IN96
|
416 |
|
|
REGISTER_ADDRESS[2] => Mux1.IN97
|
417 |
|
|
REGISTER_ADDRESS[3] => Mux1.IN92
|
418 |
|
|
REGISTER_ADDRESS[3] => Mux1.IN93
|
419 |
|
|
REGISTER_ADDRESS[3] => Mux1.IN94
|
420 |
|
|
REGISTER_ADDRESS[4] => Mux1.IN89
|
421 |
|
|
REGISTER_ADDRESS[4] => Mux1.IN90
|
422 |
|
|
REGISTER_ADDRESS[4] => Mux1.IN91
|
423 |
|
|
REGISTER_ADDRESS[5] => Mux1.IN86
|
424 |
|
|
REGISTER_ADDRESS[5] => Mux1.IN87
|
425 |
|
|
REGISTER_ADDRESS[5] => Mux1.IN88
|
426 |
|
|
REGISTER_ADDRESS[6] => Mux1.IN83
|
427 |
|
|
REGISTER_ADDRESS[6] => Mux1.IN84
|
428 |
|
|
REGISTER_ADDRESS[6] => Mux1.IN85
|
429 |
|
|
REGISTER_ADDRESS[7] => Mux1.IN80
|
430 |
|
|
REGISTER_ADDRESS[7] => Mux1.IN81
|
431 |
|
|
REGISTER_ADDRESS[7] => Mux1.IN82
|
432 |
|
|
REGISTER_DATA[0] => Mux1.IN125
|
433 |
|
|
REGISTER_DATA[0] => Mux1.IN126
|
434 |
|
|
REGISTER_DATA[0] => Mux1.IN127
|
435 |
|
|
REGISTER_DATA[1] => Mux1.IN122
|
436 |
|
|
REGISTER_DATA[1] => Mux1.IN123
|
437 |
|
|
REGISTER_DATA[1] => Mux1.IN124
|
438 |
|
|
REGISTER_DATA[2] => Mux1.IN119
|
439 |
|
|
REGISTER_DATA[2] => Mux1.IN120
|
440 |
|
|
REGISTER_DATA[2] => Mux1.IN121
|
441 |
|
|
REGISTER_DATA[3] => Mux1.IN116
|
442 |
|
|
REGISTER_DATA[3] => Mux1.IN117
|
443 |
|
|
REGISTER_DATA[3] => Mux1.IN118
|
444 |
|
|
REGISTER_DATA[4] => Mux1.IN113
|
445 |
|
|
REGISTER_DATA[4] => Mux1.IN114
|
446 |
|
|
REGISTER_DATA[4] => Mux1.IN115
|
447 |
|
|
REGISTER_DATA[5] => Mux1.IN110
|
448 |
|
|
REGISTER_DATA[5] => Mux1.IN111
|
449 |
|
|
REGISTER_DATA[5] => Mux1.IN112
|
450 |
|
|
REGISTER_DATA[6] => Mux1.IN107
|
451 |
|
|
REGISTER_DATA[6] => Mux1.IN108
|
452 |
|
|
REGISTER_DATA[6] => Mux1.IN109
|
453 |
|
|
REGISTER_DATA[7] => Mux1.IN104
|
454 |
|
|
REGISTER_DATA[7] => Mux1.IN105
|
455 |
|
|
REGISTER_DATA[7] => Mux1.IN106
|
456 |
|
|
I2C_CLOCK <= I2C_CLOCK~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
457 |
|
|
I2C_DATA <= comb~1
|
458 |
|
|
|
459 |
|
|
|
460 |
|
|
|HD_ADPCM_Codec|I2S_Driver:u3
|
461 |
|
|
CLOCK_IN => Counter[24].CLK
|
462 |
|
|
CLOCK_IN => Counter[23].CLK
|
463 |
|
|
CLOCK_IN => Counter[22].CLK
|
464 |
|
|
CLOCK_IN => Counter[21].CLK
|
465 |
|
|
CLOCK_IN => Counter[20].CLK
|
466 |
|
|
CLOCK_IN => Counter[19].CLK
|
467 |
|
|
CLOCK_IN => Counter[18].CLK
|
468 |
|
|
CLOCK_IN => Counter[17].CLK
|
469 |
|
|
CLOCK_IN => Counter[16].CLK
|
470 |
|
|
CLOCK_IN => Counter[15].CLK
|
471 |
|
|
CLOCK_IN => Counter[14].CLK
|
472 |
|
|
CLOCK_IN => Counter[13].CLK
|
473 |
|
|
CLOCK_IN => Counter[12].CLK
|
474 |
|
|
CLOCK_IN => Counter[11].CLK
|
475 |
|
|
CLOCK_IN => Counter[10].CLK
|
476 |
|
|
CLOCK_IN => Counter[9].CLK
|
477 |
|
|
CLOCK_IN => Counter[8].CLK
|
478 |
|
|
CLOCK_IN => Counter[7].CLK
|
479 |
|
|
CLOCK_IN => Counter[6].CLK
|
480 |
|
|
CLOCK_IN => Counter[5].CLK
|
481 |
|
|
CLOCK_IN => Counter[4].CLK
|
482 |
|
|
CLOCK_IN => Counter[3].CLK
|
483 |
|
|
CLOCK_IN => Counter[2].CLK
|
484 |
|
|
CLOCK_IN => Counter[1].CLK
|
485 |
|
|
CLOCK_IN => Counter[0].CLK
|
486 |
|
|
CLOCK_IN => I2S_Clock.CLK
|
487 |
|
|
ACTIVE_IN => Active_Module[0].CLK
|
488 |
|
|
ACTIVE_IN => Active_Module[0].ACLR
|
489 |
|
|
PCM_DATA_LEFT_IN[0] => Mux0.IN47
|
490 |
|
|
PCM_DATA_LEFT_IN[1] => Mux0.IN46
|
491 |
|
|
PCM_DATA_LEFT_IN[2] => Mux0.IN45
|
492 |
|
|
PCM_DATA_LEFT_IN[3] => Mux0.IN44
|
493 |
|
|
PCM_DATA_LEFT_IN[4] => Mux0.IN43
|
494 |
|
|
PCM_DATA_LEFT_IN[5] => Mux0.IN42
|
495 |
|
|
PCM_DATA_LEFT_IN[6] => Mux0.IN41
|
496 |
|
|
PCM_DATA_LEFT_IN[7] => Mux0.IN40
|
497 |
|
|
PCM_DATA_LEFT_IN[8] => Mux0.IN39
|
498 |
|
|
PCM_DATA_LEFT_IN[9] => Mux0.IN38
|
499 |
|
|
PCM_DATA_LEFT_IN[10] => Mux0.IN37
|
500 |
|
|
PCM_DATA_LEFT_IN[11] => Mux0.IN36
|
501 |
|
|
PCM_DATA_LEFT_IN[12] => Mux0.IN35
|
502 |
|
|
PCM_DATA_LEFT_IN[13] => Mux0.IN34
|
503 |
|
|
PCM_DATA_LEFT_IN[14] => Mux0.IN33
|
504 |
|
|
PCM_DATA_LEFT_IN[15] => Mux0.IN32
|
505 |
|
|
PCM_DATA_RIGHT_IN[0] => Mux0.IN63
|
506 |
|
|
PCM_DATA_RIGHT_IN[1] => Mux0.IN62
|
507 |
|
|
PCM_DATA_RIGHT_IN[2] => Mux0.IN61
|
508 |
|
|
PCM_DATA_RIGHT_IN[3] => Mux0.IN60
|
509 |
|
|
PCM_DATA_RIGHT_IN[4] => Mux0.IN59
|
510 |
|
|
PCM_DATA_RIGHT_IN[5] => Mux0.IN58
|
511 |
|
|
PCM_DATA_RIGHT_IN[6] => Mux0.IN57
|
512 |
|
|
PCM_DATA_RIGHT_IN[7] => Mux0.IN56
|
513 |
|
|
PCM_DATA_RIGHT_IN[8] => Mux0.IN55
|
514 |
|
|
PCM_DATA_RIGHT_IN[9] => Mux0.IN54
|
515 |
|
|
PCM_DATA_RIGHT_IN[10] => Mux0.IN53
|
516 |
|
|
PCM_DATA_RIGHT_IN[11] => Mux0.IN52
|
517 |
|
|
PCM_DATA_RIGHT_IN[12] => Mux0.IN51
|
518 |
|
|
PCM_DATA_RIGHT_IN[13] => Mux0.IN50
|
519 |
|
|
PCM_DATA_RIGHT_IN[14] => Mux0.IN49
|
520 |
|
|
PCM_DATA_RIGHT_IN[15] => Mux0.IN48
|
521 |
|
|
I2S_LEFT_RIGHT_CLOCK_OUT <= I2S_LEFT_RIGHT_CLOCK_OUT~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
522 |
|
|
I2S_CLOCK_OUT <= I2S_Clock.DB_MAX_OUTPUT_PORT_TYPE
|
523 |
|
|
I2S_DATA_INOUT <= comb~1
|
524 |
|
|
I2S_PCM_DATA_ACCESS_OUT <= I2S_PCM_DATA_ACCESS_OUT~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
525 |
|
|
|
526 |
|
|
|
527 |
|
|
|HD_ADPCM_Codec|Flash_Memory_Driver:u4
|
528 |
|
|
CLOCK_IN => Counter[24].CLK
|
529 |
|
|
CLOCK_IN => Counter[23].CLK
|
530 |
|
|
CLOCK_IN => Counter[22].CLK
|
531 |
|
|
CLOCK_IN => Counter[21].CLK
|
532 |
|
|
CLOCK_IN => Counter[20].CLK
|
533 |
|
|
CLOCK_IN => Counter[19].CLK
|
534 |
|
|
CLOCK_IN => Counter[18].CLK
|
535 |
|
|
CLOCK_IN => Counter[17].CLK
|
536 |
|
|
CLOCK_IN => Counter[16].CLK
|
537 |
|
|
CLOCK_IN => Counter[15].CLK
|
538 |
|
|
CLOCK_IN => Counter[14].CLK
|
539 |
|
|
CLOCK_IN => Counter[13].CLK
|
540 |
|
|
CLOCK_IN => Counter[12].CLK
|
541 |
|
|
CLOCK_IN => Counter[11].CLK
|
542 |
|
|
CLOCK_IN => Counter[10].CLK
|
543 |
|
|
CLOCK_IN => Counter[9].CLK
|
544 |
|
|
CLOCK_IN => Counter[8].CLK
|
545 |
|
|
CLOCK_IN => Counter[7].CLK
|
546 |
|
|
CLOCK_IN => Counter[6].CLK
|
547 |
|
|
CLOCK_IN => Counter[5].CLK
|
548 |
|
|
CLOCK_IN => Counter[4].CLK
|
549 |
|
|
CLOCK_IN => Counter[3].CLK
|
550 |
|
|
CLOCK_IN => Counter[2].CLK
|
551 |
|
|
CLOCK_IN => Counter[1].CLK
|
552 |
|
|
CLOCK_IN => Counter[0].CLK
|
553 |
|
|
CLOCK_IN => Flash_Memory_Clock.CLK
|
554 |
|
|
ACTIVE_IN => Flash_Memory_Clock~0.OUTPUTSELECT
|
555 |
|
|
FLASH_MEMORY_ADDRESS_IN[0] => Mux26.IN2
|
556 |
|
|
FLASH_MEMORY_ADDRESS_IN[1] => Mux25.IN2
|
557 |
|
|
FLASH_MEMORY_ADDRESS_IN[2] => Mux24.IN2
|
558 |
|
|
FLASH_MEMORY_ADDRESS_IN[3] => Mux23.IN2
|
559 |
|
|
FLASH_MEMORY_ADDRESS_IN[4] => Mux22.IN2
|
560 |
|
|
FLASH_MEMORY_ADDRESS_IN[5] => Mux21.IN2
|
561 |
|
|
FLASH_MEMORY_ADDRESS_IN[6] => Mux20.IN2
|
562 |
|
|
FLASH_MEMORY_ADDRESS_IN[7] => Mux19.IN2
|
563 |
|
|
FLASH_MEMORY_ADDRESS_IN[8] => Mux18.IN2
|
564 |
|
|
FLASH_MEMORY_ADDRESS_IN[9] => Mux17.IN2
|
565 |
|
|
FLASH_MEMORY_ADDRESS_IN[10] => Mux16.IN2
|
566 |
|
|
FLASH_MEMORY_ADDRESS_IN[11] => Mux15.IN2
|
567 |
|
|
FLASH_MEMORY_ADDRESS_IN[12] => Mux14.IN2
|
568 |
|
|
FLASH_MEMORY_ADDRESS_IN[13] => Mux13.IN2
|
569 |
|
|
FLASH_MEMORY_ADDRESS_IN[14] => Mux12.IN2
|
570 |
|
|
FLASH_MEMORY_ADDRESS_IN[15] => Mux11.IN2
|
571 |
|
|
FLASH_MEMORY_ADDRESS_IN[16] => Mux10.IN2
|
572 |
|
|
FLASH_MEMORY_ADDRESS_IN[17] => Mux9.IN2
|
573 |
|
|
FLASH_MEMORY_ADDRESS_IN[18] => Mux8.IN2
|
574 |
|
|
FLASH_MEMORY_ADDRESS_IN[19] => Mux7.IN2
|
575 |
|
|
FLASH_MEMORY_ADDRESS_IN[20] => Mux6.IN2
|
576 |
|
|
FLASH_MEMORY_ADDRESS_IN[21] => Mux5.IN2
|
577 |
|
|
FLASH_MEMORY_DATA_OUT[0] <= FLASH_MEMORY_DATA_OUT[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
578 |
|
|
FLASH_MEMORY_DATA_OUT[1] <= FLASH_MEMORY_DATA_OUT[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
579 |
|
|
FLASH_MEMORY_DATA_OUT[2] <= FLASH_MEMORY_DATA_OUT[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
580 |
|
|
FLASH_MEMORY_DATA_OUT[3] <= FLASH_MEMORY_DATA_OUT[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
581 |
|
|
FLASH_MEMORY_DATA_OUT[4] <= FLASH_MEMORY_DATA_OUT[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
582 |
|
|
FLASH_MEMORY_DATA_OUT[5] <= FLASH_MEMORY_DATA_OUT[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
583 |
|
|
FLASH_MEMORY_DATA_OUT[6] <= FLASH_MEMORY_DATA_OUT[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
584 |
|
|
FLASH_MEMORY_DATA_OUT[7] <= FLASH_MEMORY_DATA_OUT[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
585 |
|
|
DATA_VALID <= Flash_Memory_Data_Valid.DB_MAX_OUTPUT_PORT_TYPE
|
586 |
|
|
FLASH_MEMORY_nWE <= FLASH_MEMORY_nWE~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
587 |
|
|
FLASH_MEMORY_nOE <= FLASH_MEMORY_nOE~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
588 |
|
|
FLASH_MEMORY_nRESET <= FLASH_MEMORY_nRESET~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
589 |
|
|
FLASH_MEMORY_nCE <= FLASH_MEMORY_nCE~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
590 |
|
|
FLASH_MEMORY_ADDRESS[0] <= FLASH_MEMORY_ADDRESS[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
591 |
|
|
FLASH_MEMORY_ADDRESS[1] <= FLASH_MEMORY_ADDRESS[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
592 |
|
|
FLASH_MEMORY_ADDRESS[2] <= FLASH_MEMORY_ADDRESS[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
593 |
|
|
FLASH_MEMORY_ADDRESS[3] <= FLASH_MEMORY_ADDRESS[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
594 |
|
|
FLASH_MEMORY_ADDRESS[4] <= FLASH_MEMORY_ADDRESS[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
595 |
|
|
FLASH_MEMORY_ADDRESS[5] <= FLASH_MEMORY_ADDRESS[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
596 |
|
|
FLASH_MEMORY_ADDRESS[6] <= FLASH_MEMORY_ADDRESS[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
597 |
|
|
FLASH_MEMORY_ADDRESS[7] <= FLASH_MEMORY_ADDRESS[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
598 |
|
|
FLASH_MEMORY_ADDRESS[8] <= FLASH_MEMORY_ADDRESS[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
599 |
|
|
FLASH_MEMORY_ADDRESS[9] <= FLASH_MEMORY_ADDRESS[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
600 |
|
|
FLASH_MEMORY_ADDRESS[10] <= FLASH_MEMORY_ADDRESS[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
601 |
|
|
FLASH_MEMORY_ADDRESS[11] <= FLASH_MEMORY_ADDRESS[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
602 |
|
|
FLASH_MEMORY_ADDRESS[12] <= FLASH_MEMORY_ADDRESS[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
603 |
|
|
FLASH_MEMORY_ADDRESS[13] <= FLASH_MEMORY_ADDRESS[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
604 |
|
|
FLASH_MEMORY_ADDRESS[14] <= FLASH_MEMORY_ADDRESS[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
605 |
|
|
FLASH_MEMORY_ADDRESS[15] <= FLASH_MEMORY_ADDRESS[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
606 |
|
|
FLASH_MEMORY_ADDRESS[16] <= FLASH_MEMORY_ADDRESS[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
607 |
|
|
FLASH_MEMORY_ADDRESS[17] <= FLASH_MEMORY_ADDRESS[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
608 |
|
|
FLASH_MEMORY_ADDRESS[18] <= FLASH_MEMORY_ADDRESS[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
609 |
|
|
FLASH_MEMORY_ADDRESS[19] <= FLASH_MEMORY_ADDRESS[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
610 |
|
|
FLASH_MEMORY_ADDRESS[20] <= FLASH_MEMORY_ADDRESS[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
611 |
|
|
FLASH_MEMORY_ADDRESS[21] <= FLASH_MEMORY_ADDRESS[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
612 |
|
|
|
613 |
|
|
|
614 |
|
|
|HD_ADPCM_Codec|ADPCM_Decoder_1_Bit:u5
|
615 |
|
|
CLOCK_IN => PCM_Data_Difference[16].CLK
|
616 |
|
|
CLOCK_IN => PCM_Data_Difference[15].CLK
|
617 |
|
|
CLOCK_IN => PCM_Data_Difference[14].CLK
|
618 |
|
|
CLOCK_IN => PCM_Data_Difference[13].CLK
|
619 |
|
|
CLOCK_IN => PCM_Data_Difference[12].CLK
|
620 |
|
|
CLOCK_IN => PCM_Data_Difference[11].CLK
|
621 |
|
|
CLOCK_IN => PCM_Data_Difference[10].CLK
|
622 |
|
|
CLOCK_IN => PCM_Data_Difference[9].CLK
|
623 |
|
|
CLOCK_IN => PCM_Data_Difference[8].CLK
|
624 |
|
|
CLOCK_IN => PCM_Data_Difference[7].CLK
|
625 |
|
|
CLOCK_IN => PCM_Data_Difference[6].CLK
|
626 |
|
|
CLOCK_IN => PCM_Data_Difference[5].CLK
|
627 |
|
|
CLOCK_IN => PCM_Data_Difference[4].CLK
|
628 |
|
|
CLOCK_IN => PCM_Data_Difference[3].CLK
|
629 |
|
|
CLOCK_IN => PCM_Data_Difference[2].CLK
|
630 |
|
|
CLOCK_IN => PCM_Data_Difference[1].CLK
|
631 |
|
|
CLOCK_IN => PCM_Data_Difference[0].CLK
|
632 |
|
|
CLOCK_IN => ADPCM_Decoder_Step_Size_Table_Pointer[9].CLK
|
633 |
|
|
CLOCK_IN => ADPCM_Decoder_Step_Size_Table_Pointer[8].CLK
|
634 |
|
|
CLOCK_IN => ADPCM_Decoder_Step_Size_Table_Pointer[7].CLK
|
635 |
|
|
CLOCK_IN => ADPCM_Decoder_Step_Size_Table_Pointer[6].CLK
|
636 |
|
|
CLOCK_IN => ADPCM_Decoder_Step_Size_Table_Pointer[5].CLK
|
637 |
|
|
CLOCK_IN => ADPCM_Decoder_Step_Size_Table_Pointer[4].CLK
|
638 |
|
|
CLOCK_IN => ADPCM_Decoder_Step_Size_Table_Pointer[3].CLK
|
639 |
|
|
CLOCK_IN => ADPCM_Decoder_Step_Size_Table_Pointer[2].CLK
|
640 |
|
|
CLOCK_IN => ADPCM_Decoder_Step_Size_Table_Pointer[1].CLK
|
641 |
|
|
CLOCK_IN => ADPCM_Decoder_Step_Size_Table_Pointer[0].CLK
|
642 |
|
|
CLOCK_IN => Last_PCM_Data[16].CLK
|
643 |
|
|
CLOCK_IN => Last_PCM_Data[15].CLK
|
644 |
|
|
CLOCK_IN => Last_PCM_Data[14].CLK
|
645 |
|
|
CLOCK_IN => Last_PCM_Data[13].CLK
|
646 |
|
|
CLOCK_IN => Last_PCM_Data[12].CLK
|
647 |
|
|
CLOCK_IN => Last_PCM_Data[11].CLK
|
648 |
|
|
CLOCK_IN => Last_PCM_Data[10].CLK
|
649 |
|
|
CLOCK_IN => Last_PCM_Data[9].CLK
|
650 |
|
|
CLOCK_IN => Last_PCM_Data[8].CLK
|
651 |
|
|
CLOCK_IN => Last_PCM_Data[7].CLK
|
652 |
|
|
CLOCK_IN => Last_PCM_Data[6].CLK
|
653 |
|
|
CLOCK_IN => Last_PCM_Data[5].CLK
|
654 |
|
|
CLOCK_IN => Last_PCM_Data[4].CLK
|
655 |
|
|
CLOCK_IN => Last_PCM_Data[3].CLK
|
656 |
|
|
CLOCK_IN => Last_PCM_Data[2].CLK
|
657 |
|
|
CLOCK_IN => Last_PCM_Data[1].CLK
|
658 |
|
|
CLOCK_IN => Last_PCM_Data[0].CLK
|
659 |
|
|
CLOCK_IN => PCM_Data[15].CLK
|
660 |
|
|
CLOCK_IN => PCM_Data[14].CLK
|
661 |
|
|
CLOCK_IN => PCM_Data[13].CLK
|
662 |
|
|
CLOCK_IN => PCM_Data[12].CLK
|
663 |
|
|
CLOCK_IN => PCM_Data[11].CLK
|
664 |
|
|
CLOCK_IN => PCM_Data[10].CLK
|
665 |
|
|
CLOCK_IN => PCM_Data[9].CLK
|
666 |
|
|
CLOCK_IN => PCM_Data[8].CLK
|
667 |
|
|
CLOCK_IN => PCM_Data[7].CLK
|
668 |
|
|
CLOCK_IN => PCM_Data[6].CLK
|
669 |
|
|
CLOCK_IN => PCM_Data[5].CLK
|
670 |
|
|
CLOCK_IN => PCM_Data[4].CLK
|
671 |
|
|
CLOCK_IN => PCM_Data[3].CLK
|
672 |
|
|
CLOCK_IN => PCM_Data[2].CLK
|
673 |
|
|
CLOCK_IN => PCM_Data[1].CLK
|
674 |
|
|
CLOCK_IN => PCM_Data[0].CLK
|
675 |
|
|
CLOCK_IN => ADPCM_Decoder_State_Counter[2].CLK
|
676 |
|
|
CLOCK_IN => ADPCM_Decoder_State_Counter[1].CLK
|
677 |
|
|
CLOCK_IN => ADPCM_Decoder_State_Counter[0].CLK
|
678 |
|
|
CLOCK_IN => Last_ADPCM_Data.CLK
|
679 |
|
|
CLOCK_IN => PCM_DATA_OUT[15]~reg0.CLK
|
680 |
|
|
CLOCK_IN => PCM_DATA_OUT[14]~reg0.CLK
|
681 |
|
|
CLOCK_IN => PCM_DATA_OUT[13]~reg0.CLK
|
682 |
|
|
CLOCK_IN => PCM_DATA_OUT[12]~reg0.CLK
|
683 |
|
|
CLOCK_IN => PCM_DATA_OUT[11]~reg0.CLK
|
684 |
|
|
CLOCK_IN => PCM_DATA_OUT[10]~reg0.CLK
|
685 |
|
|
CLOCK_IN => PCM_DATA_OUT[9]~reg0.CLK
|
686 |
|
|
CLOCK_IN => PCM_DATA_OUT[8]~reg0.CLK
|
687 |
|
|
CLOCK_IN => PCM_DATA_OUT[7]~reg0.CLK
|
688 |
|
|
CLOCK_IN => PCM_DATA_OUT[6]~reg0.CLK
|
689 |
|
|
CLOCK_IN => PCM_DATA_OUT[5]~reg0.CLK
|
690 |
|
|
CLOCK_IN => PCM_DATA_OUT[4]~reg0.CLK
|
691 |
|
|
CLOCK_IN => PCM_DATA_OUT[3]~reg0.CLK
|
692 |
|
|
CLOCK_IN => PCM_DATA_OUT[2]~reg0.CLK
|
693 |
|
|
CLOCK_IN => PCM_DATA_OUT[1]~reg0.CLK
|
694 |
|
|
CLOCK_IN => PCM_DATA_OUT[0]~reg0.CLK
|
695 |
|
|
CLOCK_IN => Active_Module.CLK
|
696 |
|
|
ACTIVE_IN => Active_Module~0.DATAB
|
697 |
|
|
ACTIVE_IN => process_0~0.IN1
|
698 |
|
|
ADPCM_DATA_IN => Mux27.IN0
|
699 |
|
|
ADPCM_DATA_IN => Last_PCM_Data~16.OUTPUTSELECT
|
700 |
|
|
ADPCM_DATA_IN => Last_PCM_Data~15.OUTPUTSELECT
|
701 |
|
|
ADPCM_DATA_IN => Last_PCM_Data~14.OUTPUTSELECT
|
702 |
|
|
ADPCM_DATA_IN => Last_PCM_Data~13.OUTPUTSELECT
|
703 |
|
|
ADPCM_DATA_IN => Last_PCM_Data~12.OUTPUTSELECT
|
704 |
|
|
ADPCM_DATA_IN => Last_PCM_Data~11.OUTPUTSELECT
|
705 |
|
|
ADPCM_DATA_IN => Last_PCM_Data~10.OUTPUTSELECT
|
706 |
|
|
ADPCM_DATA_IN => Last_PCM_Data~9.OUTPUTSELECT
|
707 |
|
|
ADPCM_DATA_IN => Last_PCM_Data~8.OUTPUTSELECT
|
708 |
|
|
ADPCM_DATA_IN => Last_PCM_Data~7.OUTPUTSELECT
|
709 |
|
|
ADPCM_DATA_IN => Last_PCM_Data~6.OUTPUTSELECT
|
710 |
|
|
ADPCM_DATA_IN => Last_PCM_Data~5.OUTPUTSELECT
|
711 |
|
|
ADPCM_DATA_IN => Last_PCM_Data~4.OUTPUTSELECT
|
712 |
|
|
ADPCM_DATA_IN => Last_PCM_Data~3.OUTPUTSELECT
|
713 |
|
|
ADPCM_DATA_IN => Last_PCM_Data~2.OUTPUTSELECT
|
714 |
|
|
ADPCM_DATA_IN => Last_PCM_Data~1.OUTPUTSELECT
|
715 |
|
|
ADPCM_DATA_IN => Last_PCM_Data~0.OUTPUTSELECT
|
716 |
|
|
ADPCM_DATA_IN => process_0~1.IN1
|
717 |
|
|
PCM_DATA_OUT[0] <= PCM_DATA_OUT[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
718 |
|
|
PCM_DATA_OUT[1] <= PCM_DATA_OUT[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
719 |
|
|
PCM_DATA_OUT[2] <= PCM_DATA_OUT[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
720 |
|
|
PCM_DATA_OUT[3] <= PCM_DATA_OUT[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
721 |
|
|
PCM_DATA_OUT[4] <= PCM_DATA_OUT[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
722 |
|
|
PCM_DATA_OUT[5] <= PCM_DATA_OUT[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
723 |
|
|
PCM_DATA_OUT[6] <= PCM_DATA_OUT[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
724 |
|
|
PCM_DATA_OUT[7] <= PCM_DATA_OUT[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
725 |
|
|
PCM_DATA_OUT[8] <= PCM_DATA_OUT[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
726 |
|
|
PCM_DATA_OUT[9] <= PCM_DATA_OUT[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
727 |
|
|
PCM_DATA_OUT[10] <= PCM_DATA_OUT[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
728 |
|
|
PCM_DATA_OUT[11] <= PCM_DATA_OUT[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
729 |
|
|
PCM_DATA_OUT[12] <= PCM_DATA_OUT[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
730 |
|
|
PCM_DATA_OUT[13] <= PCM_DATA_OUT[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
731 |
|
|
PCM_DATA_OUT[14] <= PCM_DATA_OUT[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
732 |
|
|
PCM_DATA_OUT[15] <= PCM_DATA_OUT[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
733 |
|
|
|
734 |
|
|
|
735 |
|
|
|HD_ADPCM_Codec|ADPCM_Decoder_1_Bit:u6
|
736 |
|
|
CLOCK_IN => PCM_Data_Difference[16].CLK
|
737 |
|
|
CLOCK_IN => PCM_Data_Difference[15].CLK
|
738 |
|
|
CLOCK_IN => PCM_Data_Difference[14].CLK
|
739 |
|
|
CLOCK_IN => PCM_Data_Difference[13].CLK
|
740 |
|
|
CLOCK_IN => PCM_Data_Difference[12].CLK
|
741 |
|
|
CLOCK_IN => PCM_Data_Difference[11].CLK
|
742 |
|
|
CLOCK_IN => PCM_Data_Difference[10].CLK
|
743 |
|
|
CLOCK_IN => PCM_Data_Difference[9].CLK
|
744 |
|
|
CLOCK_IN => PCM_Data_Difference[8].CLK
|
745 |
|
|
CLOCK_IN => PCM_Data_Difference[7].CLK
|
746 |
|
|
CLOCK_IN => PCM_Data_Difference[6].CLK
|
747 |
|
|
CLOCK_IN => PCM_Data_Difference[5].CLK
|
748 |
|
|
CLOCK_IN => PCM_Data_Difference[4].CLK
|
749 |
|
|
CLOCK_IN => PCM_Data_Difference[3].CLK
|
750 |
|
|
CLOCK_IN => PCM_Data_Difference[2].CLK
|
751 |
|
|
CLOCK_IN => PCM_Data_Difference[1].CLK
|
752 |
|
|
CLOCK_IN => PCM_Data_Difference[0].CLK
|
753 |
|
|
CLOCK_IN => ADPCM_Decoder_Step_Size_Table_Pointer[9].CLK
|
754 |
|
|
CLOCK_IN => ADPCM_Decoder_Step_Size_Table_Pointer[8].CLK
|
755 |
|
|
CLOCK_IN => ADPCM_Decoder_Step_Size_Table_Pointer[7].CLK
|
756 |
|
|
CLOCK_IN => ADPCM_Decoder_Step_Size_Table_Pointer[6].CLK
|
757 |
|
|
CLOCK_IN => ADPCM_Decoder_Step_Size_Table_Pointer[5].CLK
|
758 |
|
|
CLOCK_IN => ADPCM_Decoder_Step_Size_Table_Pointer[4].CLK
|
759 |
|
|
CLOCK_IN => ADPCM_Decoder_Step_Size_Table_Pointer[3].CLK
|
760 |
|
|
CLOCK_IN => ADPCM_Decoder_Step_Size_Table_Pointer[2].CLK
|
761 |
|
|
CLOCK_IN => ADPCM_Decoder_Step_Size_Table_Pointer[1].CLK
|
762 |
|
|
CLOCK_IN => ADPCM_Decoder_Step_Size_Table_Pointer[0].CLK
|
763 |
|
|
CLOCK_IN => Last_PCM_Data[16].CLK
|
764 |
|
|
CLOCK_IN => Last_PCM_Data[15].CLK
|
765 |
|
|
CLOCK_IN => Last_PCM_Data[14].CLK
|
766 |
|
|
CLOCK_IN => Last_PCM_Data[13].CLK
|
767 |
|
|
CLOCK_IN => Last_PCM_Data[12].CLK
|
768 |
|
|
CLOCK_IN => Last_PCM_Data[11].CLK
|
769 |
|
|
CLOCK_IN => Last_PCM_Data[10].CLK
|
770 |
|
|
CLOCK_IN => Last_PCM_Data[9].CLK
|
771 |
|
|
CLOCK_IN => Last_PCM_Data[8].CLK
|
772 |
|
|
CLOCK_IN => Last_PCM_Data[7].CLK
|
773 |
|
|
CLOCK_IN => Last_PCM_Data[6].CLK
|
774 |
|
|
CLOCK_IN => Last_PCM_Data[5].CLK
|
775 |
|
|
CLOCK_IN => Last_PCM_Data[4].CLK
|
776 |
|
|
CLOCK_IN => Last_PCM_Data[3].CLK
|
777 |
|
|
CLOCK_IN => Last_PCM_Data[2].CLK
|
778 |
|
|
CLOCK_IN => Last_PCM_Data[1].CLK
|
779 |
|
|
CLOCK_IN => Last_PCM_Data[0].CLK
|
780 |
|
|
CLOCK_IN => PCM_Data[15].CLK
|
781 |
|
|
CLOCK_IN => PCM_Data[14].CLK
|
782 |
|
|
CLOCK_IN => PCM_Data[13].CLK
|
783 |
|
|
CLOCK_IN => PCM_Data[12].CLK
|
784 |
|
|
CLOCK_IN => PCM_Data[11].CLK
|
785 |
|
|
CLOCK_IN => PCM_Data[10].CLK
|
786 |
|
|
CLOCK_IN => PCM_Data[9].CLK
|
787 |
|
|
CLOCK_IN => PCM_Data[8].CLK
|
788 |
|
|
CLOCK_IN => PCM_Data[7].CLK
|
789 |
|
|
CLOCK_IN => PCM_Data[6].CLK
|
790 |
|
|
CLOCK_IN => PCM_Data[5].CLK
|
791 |
|
|
CLOCK_IN => PCM_Data[4].CLK
|
792 |
|
|
CLOCK_IN => PCM_Data[3].CLK
|
793 |
|
|
CLOCK_IN => PCM_Data[2].CLK
|
794 |
|
|
CLOCK_IN => PCM_Data[1].CLK
|
795 |
|
|
CLOCK_IN => PCM_Data[0].CLK
|
796 |
|
|
CLOCK_IN => ADPCM_Decoder_State_Counter[2].CLK
|
797 |
|
|
CLOCK_IN => ADPCM_Decoder_State_Counter[1].CLK
|
798 |
|
|
CLOCK_IN => ADPCM_Decoder_State_Counter[0].CLK
|
799 |
|
|
CLOCK_IN => Last_ADPCM_Data.CLK
|
800 |
|
|
CLOCK_IN => PCM_DATA_OUT[15]~reg0.CLK
|
801 |
|
|
CLOCK_IN => PCM_DATA_OUT[14]~reg0.CLK
|
802 |
|
|
CLOCK_IN => PCM_DATA_OUT[13]~reg0.CLK
|
803 |
|
|
CLOCK_IN => PCM_DATA_OUT[12]~reg0.CLK
|
804 |
|
|
CLOCK_IN => PCM_DATA_OUT[11]~reg0.CLK
|
805 |
|
|
CLOCK_IN => PCM_DATA_OUT[10]~reg0.CLK
|
806 |
|
|
CLOCK_IN => PCM_DATA_OUT[9]~reg0.CLK
|
807 |
|
|
CLOCK_IN => PCM_DATA_OUT[8]~reg0.CLK
|
808 |
|
|
CLOCK_IN => PCM_DATA_OUT[7]~reg0.CLK
|
809 |
|
|
CLOCK_IN => PCM_DATA_OUT[6]~reg0.CLK
|
810 |
|
|
CLOCK_IN => PCM_DATA_OUT[5]~reg0.CLK
|
811 |
|
|
CLOCK_IN => PCM_DATA_OUT[4]~reg0.CLK
|
812 |
|
|
CLOCK_IN => PCM_DATA_OUT[3]~reg0.CLK
|
813 |
|
|
CLOCK_IN => PCM_DATA_OUT[2]~reg0.CLK
|
814 |
|
|
CLOCK_IN => PCM_DATA_OUT[1]~reg0.CLK
|
815 |
|
|
CLOCK_IN => PCM_DATA_OUT[0]~reg0.CLK
|
816 |
|
|
CLOCK_IN => Active_Module.CLK
|
817 |
|
|
ACTIVE_IN => Active_Module~0.DATAB
|
818 |
|
|
ACTIVE_IN => process_0~0.IN1
|
819 |
|
|
ADPCM_DATA_IN => Mux27.IN0
|
820 |
|
|
ADPCM_DATA_IN => Last_PCM_Data~16.OUTPUTSELECT
|
821 |
|
|
ADPCM_DATA_IN => Last_PCM_Data~15.OUTPUTSELECT
|
822 |
|
|
ADPCM_DATA_IN => Last_PCM_Data~14.OUTPUTSELECT
|
823 |
|
|
ADPCM_DATA_IN => Last_PCM_Data~13.OUTPUTSELECT
|
824 |
|
|
ADPCM_DATA_IN => Last_PCM_Data~12.OUTPUTSELECT
|
825 |
|
|
ADPCM_DATA_IN => Last_PCM_Data~11.OUTPUTSELECT
|
826 |
|
|
ADPCM_DATA_IN => Last_PCM_Data~10.OUTPUTSELECT
|
827 |
|
|
ADPCM_DATA_IN => Last_PCM_Data~9.OUTPUTSELECT
|
828 |
|
|
ADPCM_DATA_IN => Last_PCM_Data~8.OUTPUTSELECT
|
829 |
|
|
ADPCM_DATA_IN => Last_PCM_Data~7.OUTPUTSELECT
|
830 |
|
|
ADPCM_DATA_IN => Last_PCM_Data~6.OUTPUTSELECT
|
831 |
|
|
ADPCM_DATA_IN => Last_PCM_Data~5.OUTPUTSELECT
|
832 |
|
|
ADPCM_DATA_IN => Last_PCM_Data~4.OUTPUTSELECT
|
833 |
|
|
ADPCM_DATA_IN => Last_PCM_Data~3.OUTPUTSELECT
|
834 |
|
|
ADPCM_DATA_IN => Last_PCM_Data~2.OUTPUTSELECT
|
835 |
|
|
ADPCM_DATA_IN => Last_PCM_Data~1.OUTPUTSELECT
|
836 |
|
|
ADPCM_DATA_IN => Last_PCM_Data~0.OUTPUTSELECT
|
837 |
|
|
ADPCM_DATA_IN => process_0~1.IN1
|
838 |
|
|
PCM_DATA_OUT[0] <= PCM_DATA_OUT[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
839 |
|
|
PCM_DATA_OUT[1] <= PCM_DATA_OUT[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
840 |
|
|
PCM_DATA_OUT[2] <= PCM_DATA_OUT[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
841 |
|
|
PCM_DATA_OUT[3] <= PCM_DATA_OUT[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
842 |
|
|
PCM_DATA_OUT[4] <= PCM_DATA_OUT[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
843 |
|
|
PCM_DATA_OUT[5] <= PCM_DATA_OUT[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
844 |
|
|
PCM_DATA_OUT[6] <= PCM_DATA_OUT[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
845 |
|
|
PCM_DATA_OUT[7] <= PCM_DATA_OUT[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
846 |
|
|
PCM_DATA_OUT[8] <= PCM_DATA_OUT[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
847 |
|
|
PCM_DATA_OUT[9] <= PCM_DATA_OUT[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
848 |
|
|
PCM_DATA_OUT[10] <= PCM_DATA_OUT[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
849 |
|
|
PCM_DATA_OUT[11] <= PCM_DATA_OUT[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
850 |
|
|
PCM_DATA_OUT[12] <= PCM_DATA_OUT[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
851 |
|
|
PCM_DATA_OUT[13] <= PCM_DATA_OUT[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
852 |
|
|
PCM_DATA_OUT[14] <= PCM_DATA_OUT[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
853 |
|
|
PCM_DATA_OUT[15] <= PCM_DATA_OUT[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
854 |
|
|
|
855 |
|
|
|