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[/] [axi4_tlm_bfm/] [trunk/] [tester/] [tester.vhdl] - Blame information for rev 38

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1 24 daniel.kho
/*
2
        This file is part of the AXI4 Transactor and Bus Functional Model
3
        (axi4_tlm_bfm) project:
4
                http://www.opencores.org/project,axi4_tlm_bfm
5
 
6
        Description
7
        Synthesisable use case for AXI4 on-chip messaging.
8
 
9
        To Do:
10
 
11
        Author(s):
12
        - Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com
13
 
14
        Copyright (C) 2012-2013 Authors and OPENCORES.ORG
15
 
16
        This source file may be used and distributed without
17
        restriction provided that this copyright statement is not
18
        removed from the file and that any derivative work contains
19
        the original copyright notice and the associated disclaimer.
20
 
21
        This source file is free software; you can redistribute it
22
        and/or modify it under the terms of the GNU Lesser General
23
        Public License as published by the Free Software Foundation;
24
        either version 2.1 of the License, or (at your option) any
25
        later version.
26
 
27
        This source is distributed in the hope that it will be
28
        useful, but WITHOUT ANY WARRANTY; without even the implied
29
        warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
30
        PURPOSE. See the GNU Lesser General Public License for more
31
        details.
32
 
33
        You should have received a copy of the GNU Lesser General
34
        Public License along with this source; if not, download it
35
        from http://www.opencores.org/lgpl.shtml.
36
*/
37 38 daniel.kho
library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all, ieee.math_real.all;
38 24 daniel.kho
library tauhop; use tauhop.transactor.all, tauhop.axiTransactor.all;            --TODO just use axiTransactor here as transactor should already be wrapped up.
39
 
40
/* TODO remove once generic packages are supported. */
41
--library tauhop; use tauhop.tlm.all, tauhop.axiTLM.all;
42
 
43
/* synthesis translate_off */
44 38 daniel.kho
library osvvm; use osvvm.RandomPkg.all, osvvm.CoveragePkg.all;
45 24 daniel.kho
/* synthesis translate_on */
46
 
47
--library altera; use altera.stp;
48
 
49
 
50
entity tester is port(
51
        /* Comment-out for simulation. */
52
        clk,reset:in std_ulogic;
53
 
54
        /* AXI Master interface */
55
        axiMaster_in:buffer t_axi4StreamTransactor_s2m;
56
        axiMaster_out:in t_axi4StreamTransactor_m2s;
57
 
58
        /* BFM signalling. */
59
--      readRequest,writeRequest:t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false);
60
--      readResponse,writeResponse:t_bfm;
61
        readRequest,writeRequest:buffer t_bfm;
62
        readResponse,writeResponse:in t_bfm;
63
 
64
        irq_write:buffer std_ulogic;            -- clock gating.
65
 
66 38 daniel.kho
        lastTransaction:out boolean;
67 24 daniel.kho
 
68
        /* Debug ports. */
69
--      dataIn:in t_msg;
70
        selTxn:in unsigned(3 downto 0)
71
);
72
end entity tester;
73
 
74
architecture rtl of tester is
75
--      signal reset:std_ulogic:='0';
76
        signal locked:std_ulogic;
77
        signal porCnt:unsigned(3 downto 0);
78
        signal trigger:boolean;
79
 
80
        /* Global counters. */
81
        constant maxSymbols:positive:=2048;             --maximum number of symbols allowed to be transmitted in a frame. Each symbol's width equals tData's width. 
82
--      signal symbolsPerTransfer:t_cnt;
83
--      signal outstandingTransactions:t_cnt;
84
 
85
--      /* BFM signalling. */
86
--      signal readRequest,writeRequest:t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false);
87
--      signal readResponse,writeResponse:t_bfm;
88
 
89
        type txStates is (idle,transmitting);
90
        signal txFSM,i_txFSM:txStates;
91
 
92
        /* Tester signals. */
93
        /* synthesis translate_off */
94
--      signal clk,nReset:std_ulogic:='0';
95
        attribute period:time; attribute period of clk:signal is 10 ps;
96
        /* synthesis translate_on */
97
 
98
        signal testerClk:std_ulogic;
99
        signal dbg_axiTxFSM:axiBfmStatesTx;
100
        signal anlysr_dataIn:std_logic_vector(127 downto 0);
101
        signal anlysr_trigger:std_ulogic;
102
 
103
--      signal axiMaster_in:t_axi4StreamTransactor_s2m;
104
--      signal irq_write:std_ulogic;            -- clock gating.
105
 
106
        signal prbs:t_msg;
107
 
108 38 daniel.kho
        /* Coverage-driven randomisation. */
109
        shared variable rv0:covPType;
110
        signal rv:integer;
111
        signal pctCovered:real;
112
        signal isCovered,i_isCovered:boolean;
113
 
114 24 daniel.kho
begin
115
        /* PLL to generate tester's clock. */
116
/*    f100MHz: entity altera.pll(syn) port map(
117
        areset=>'0',    --not nReset,
118
        inclk0=>clk,
119
        c0=>testerClk,
120
        locked=>locked
121
    );
122
*/
123
        /* Interrupt-request generator. */
124
        trigger<=txFSM/=i_txFSM or writeResponse.trigger;
125
        irq_write<=clk when not reset else '0';
126
 
127
        /* SignalTap II embedded logic analyser. Included as part of BiST architecture. */
128
        --anlysr_trigger<='1' when writeRequest.trigger else '0';
129
        anlysr_trigger<='1' when reset else '0';
130
 
131
        /* Disable this for synthesis as this is not currently synthesisable.
132
                Pull the framerFSM statemachine signal from lower down the hierarchy to this level instead.
133
        */
134
        /* synthesis translate_off */
135
        --framerFSM<=to_unsigned(<<signal framers_txs(0).i_framer.framerFSM: framerFsmStates>>,framerFSM'length);
136
        /* synthesis translate_on */
137
 
138 38 daniel.kho
--      anlysr_dataIn(7 downto 0)<=std_logic_vector(symbolsPerTransfer(7 downto 0));
139
--      anlysr_dataIn(15 downto 8)<=std_logic_vector(outstandingTransactions(7 downto 0));
140 24 daniel.kho
        --anlysr_dataIn(2 downto 0) <= <<signal axiMaster.axiTxState:axiBfmStatesTx>>;
141
        anlysr_dataIn(17 downto 16)<=to_std_logic_vector(dbg_axiTxFSM);
142
        anlysr_dataIn(18)<='1' when clk else '0';
143
        anlysr_dataIn(19)<='1' when reset else '0';
144
        anlysr_dataIn(20)<='1' when irq_write else '0';
145
        anlysr_dataIn(21)<='1' when axiMaster_in.tReady else '0';
146
        anlysr_dataIn(22)<='1' when axiMaster_out.tValid else '0';
147
        anlysr_dataIn(54 downto 23)<=std_logic_vector(axiMaster_out.tData);
148
        anlysr_dataIn(86 downto 55)<=std_logic_vector(prbs);
149
        --anlysr_dataIn(90 downto 87)<=std_logic_vector(axiMaster_out.tStrb);
150
        --anlysr_dataIn(94 downto 91)<=std_logic_vector(axiMaster_out.tKeep);
151
        anlysr_dataIn(95)<='1' when axiMaster_out.tLast else '0';
152
        anlysr_dataIn(96)<='1' when writeRequest.trigger else '0';
153
        anlysr_dataIn(97)<='1' when writeResponse.trigger else '0';
154
        anlysr_dataIn(99 downto 98)<=to_std_logic_vector(dbg_axiTxFSM);
155
        anlysr_dataIn(101 downto 98)<=std_logic_vector(porCnt);
156
--      anlysr_dataIn(102)<='1' when locked else '0';
157
--      anlysr_dataIn(102)<=locked;
158
 
159
        anlysr_dataIn(anlysr_dataIn'high downto 102)<=(others=>'0');
160
 
161
 
162
        /* Simulate only if you have compiled Altera's simulation libraries. */
163
/*      i_bist_logicAnalyser: entity altera.stp(syn) port map(
164
                acq_clk=>testerClk,
165
                acq_data_in=>anlysr_dataIn,
166
                acq_trigger_in=>"1",
167
                trigger_in=>anlysr_trigger
168
        );
169
*/
170
 
171
 
172
        /* Stimuli sequencer. TODO move to tester/stimuli.
173
                This emulates the AXI4-Stream Slave.
174
        */
175
        /* Simulation-only stimuli sequencer. */
176
        /* synthesis translate_off */
177
        process is begin
178 38 daniel.kho
                /* Fast read. */
179 24 daniel.kho
                report "Performing fast read..." severity note;
180
                while not axiMaster_out.tLast loop
181
                        /* Wait for tValid to assert. */
182
                        while not axiMaster_out.tValid loop
183
                                wait until falling_edge(clk);
184
                        end loop;
185
 
186
                        axiMaster_in.tReady<=true;
187
 
188
                        wait until falling_edge(clk);
189
                        axiMaster_in.tReady<=false;
190 38 daniel.kho
 
191
                        report "coverage: " & to_string(pctCovered) severity note;
192 24 daniel.kho
                end loop;
193 38 daniel.kho
                report "coverage: " & to_string(pctCovered) severity note;
194
                report "Completed fast read." severity note;
195 24 daniel.kho
 
196
                wait until falling_edge(clk);
197
 
198
                /* Normal read. */
199 38 daniel.kho
                report "Performing normal read..." severity note;
200 24 daniel.kho
                while not axiMaster_out.tLast loop
201 38 daniel.kho
                        wait until falling_edge(clk);
202
 
203 24 daniel.kho
                        /* Wait for tValid to assert. */
204
                        while not axiMaster_out.tValid loop
205
                                wait until falling_edge(clk);
206
                        end loop;
207
 
208
                        wait until falling_edge(clk);
209
                        wait until falling_edge(clk);
210
                        axiMaster_in.tReady<=true;
211
 
212
                        wait until falling_edge(clk);
213
                        axiMaster_in.tReady<=false;
214
 
215 38 daniel.kho
                        --wait until falling_edge(clk);
216
 
217
                        report "coverage: " & to_string(pctCovered) severity note;
218 24 daniel.kho
                end loop;
219 38 daniel.kho
                report "coverage: " & to_string(pctCovered) severity note;
220 24 daniel.kho
                report "Completed normal read." severity note;
221
 
222
                for i in 0 to 10 loop
223
                        wait until falling_edge(clk);
224
                end loop;
225
 
226
                /* One-shot read. */
227 38 daniel.kho
                report "Performing one-shot read..." severity note;
228 24 daniel.kho
                axiMaster_in.tReady<=true;
229
 
230
                wait until falling_edge(clk);
231
                axiMaster_in.tReady<=false;
232
 
233 38 daniel.kho
                report "coverage: " & to_string(pctCovered) severity note;
234 24 daniel.kho
                report "Completed one-shot read." severity note;
235
 
236
                wait;
237
        end process;
238
        /* synthesis translate_on */
239
 
240
        /* Synthesisable stimuli sequencer. */
241
/*      process(clk) is begin
242
                if falling_edge(clk) then
243
                        axiMaster_in.tReady<=false;
244
                        --if axiMaster_out.tValid and not axiMaster_out.tLast then
245
                        if not axiMaster_in.tReady and axiMaster_out.tValid and not axiMaster_out.tLast then
246
                                axiMaster_in.tReady<=true;
247
                        end if;
248
                end if;
249
        end process;
250
*/
251
 
252
        /* Data transmitter. */
253 38 daniel.kho
        /* Use either PRBS (LFSR) stimuli, or OSVVM randomisation stimuli, not both. */
254 24 daniel.kho
        i_prbs: entity tauhop.prbs31(rtl)
255
                generic map(
256
                        isParallelLoad=>true,
257
                        tapVector=>(
258
                                /* Example polynomial from Wikipedia:
259
                                        http://en.wikipedia.org/wiki/Computation_of_cyclic_redundancy_checks
260
                                */
261
                                0|3|31=>true, 1|2|30 downto 4=>false
262
                        )
263
                )
264
                port map(
265
                        /* Comment-out for simulation. */
266
                        clk=>irq_write, reset=>reset,
267
                        en=>trigger,
268 38 daniel.kho
                        seed=>32x"ace1",
269 24 daniel.kho
                        prbs=>prbs
270
                );
271
 
272
        sequencer_ns: process(all) is begin
273
                txFSM<=i_txFSM;
274
                if reset then txFSM<=idle;
275
                else
276
                        case i_txFSM is
277
                                when idle=>
278 38 daniel.kho
                                        if not lastTransaction then txFSM<=transmitting; end if;
279 24 daniel.kho
                                when transmitting=>
280
                                        if axiMaster_out.tLast then
281
                                                txFSM<=idle;
282
                                        end if;
283
                                when others=> null;
284
                        end case;
285
                end if;
286
        end process sequencer_ns;
287
 
288
        sequencer_op: process(reset,irq_write) is
289
                /* Local procedures to map BFM signals with the package procedure. */
290
                procedure read(address:in t_addr) is begin
291
                        read(readRequest,address);
292
                end procedure read;
293
 
294
                procedure write(data:in t_msg) is begin
295
                        write(request=>writeRequest, address=>(others=>'-'), data=>data);
296
                end procedure write;
297
 
298
                variable isPktError:boolean;
299
 
300
        begin
301 38 daniel.kho
                /* Asynchronous reset. */
302 24 daniel.kho
                if falling_edge(irq_write) then
303
                        case txFSM is
304
                                when transmitting=>
305 38 daniel.kho
                                        if trigger and not isCovered then
306 24 daniel.kho
                                                /* Pseudorandom stimuli generation using OS-VVM. */
307
                                                /* synthesis translate_off */
308 38 daniel.kho
                                                rv<=rv0.randCovPoint;
309
                                                rv0.iCover(rv);
310
 
311
                                                write(to_signed(rv, axiMaster_out.tData'length));
312 24 daniel.kho
                                                /* synthesis translate_on */
313
 
314
                                                /* Pseudorandom stimuli generation using LFSR. */
315
                                                /*
316
                                                case selTxn is
317
                                                        when x"1"=> write(32x"12ab34cd");
318
                                                        when x"2"=> write(32x"12345678");
319
                                                        when x"3"=> write(32x"87654321");
320
                                                        when x"4"=> write(32x"abcd1234");
321
                                                        when others=> write(prbs);
322
                                                end case;
323
                                                */
324
                                        end if;
325
                                when others=>null;
326
                        end case;
327
                end if;
328
        end process sequencer_op;
329
 
330 38 daniel.kho
        coverageMonitor: process is
331
                procedure initialise is begin
332
                        /* simulation only. */
333
                        /* synthesis translate_off */
334
                        rv0.deallocate;                 --destroy rv0 and all bins.
335
                        rv0.initSeed(rv0'instance_name);
336
                        /* synthesis translate_on */
337
                end procedure initialise;
338
 
339
        begin
340
                /* Fast- and normal-reads. */
341
                for i in 0 to 1 loop
342
                        initialise;
343
                        rv0.addBins(genBin(integer'low,integer'high,512));
344
 
345
                        wait until isCovered;
346
--                      rv0.writeBin;
347
                        rv0.setCovZero;         -- reset all coverage counts to zero.
348
                end loop;
349
 
350
                /* One-shot read. */
351
                initialise;
352
                rv0.addBins(genBin(integer'low,integer'high,1));
353
 
354
                wait until isCovered;
355
--              rv0.writeBin;
356
                rv0.setCovZero;
357
 
358
        wait for 500 ps;
359
        std.env.stop;
360
    end process coverageMonitor;
361
 
362
        process(irq_write) is begin
363
                if falling_edge(irq_write) then
364
                        pctCovered<=rv0.getCov;
365
                        isCovered<=rv0.isCovered;
366
                        i_isCovered<=isCovered;
367
                end if;
368
        end process;
369
 
370 24 daniel.kho
        sequencer_regs: process(irq_write) is begin
371
        if falling_edge(irq_write) then
372
            i_txFSM<=txFSM;
373
        end if;
374
    end process sequencer_regs;
375
 
376 38 daniel.kho
        lastTransaction<=true when isCovered else false;
377 24 daniel.kho
 
378 38 daniel.kho
        checker: process(clk) is begin
379
                if rising_edge(clk) then
380
                        if axiMaster_in.tReady then
381
                                assert axiMaster_out.tData/="ZZZZZZZZ"
382
                                        report "[Error]: tData must be valid when tReady is asserted at the rising edge of the clock." severity error;
383 24 daniel.kho
                        end if;
384
                end if;
385 38 daniel.kho
        end process checker;
386 24 daniel.kho
end architecture rtl;

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