| 1 |
29 |
daniel.kho |
configure wave -signalnamewidth 1
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| 2 |
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| 3 |
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add wave -divider "DUV"
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| 4 |
41 |
daniel.kho |
add wave -position end -decimal sim:/user/axiMaster/lastTransaction
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| 5 |
29 |
daniel.kho |
add wave -position end sim:/user/axiMaster/axiTxState
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| 6 |
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add wave -position end sim:/user/axiMaster/next_axiTxState
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| 7 |
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| 8 |
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add wave -divider "Tester"
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| 9 |
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add wave -position end sim:/user/clk
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| 10 |
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add wave -position end sim:/user/reset
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| 11 |
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add wave -position end sim:/user/irq_write
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| 12 |
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add wave -position end sim:/user/axiMaster/trigger
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| 13 |
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add wave -position end sim:/user/axiMaster/i_trigger
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| 14 |
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add wave -position end -hexadecimal sim:/bist/prbs
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| 15 |
41 |
daniel.kho |
add wave -position end sim:/bist/isCovered
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add wave -position end sim:/bist/i_isCovered
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| 17 |
29 |
daniel.kho |
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| 18 |
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# Paper publication:
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| 19 |
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#add wave -position end sim:/user/irq_write
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| 20 |
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#add wave -position end -hexadecimal sim:/user/axiMaster_in.tReady
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| 21 |
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#add wave -position end -hexadecimal sim:/user/axiMaster_out.tValid
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| 22 |
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#add wave -position end -hexadecimal sim:/user/axiMaster_out.tData
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| 23 |
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#add wave -position end -hexadecimal sim:/bist/prbs
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| 24 |
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#add wave -position end -hexadecimal sim:/user/writeRequest.trigger
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| 25 |
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#add wave -position end -hexadecimal sim:/user/writeResponse.trigger
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| 26 |
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| 27 |
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add wave -position end -expand -hexadecimal sim:/user/axiMaster_in
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| 28 |
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add wave -position end -expand -hexadecimal sim:/user/axiMaster_out
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| 29 |
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add wave -position end -decimal sim:/user/readRequest
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| 30 |
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add wave -position end -expand -hexadecimal sim:/user/writeRequest
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| 31 |
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add wave -position end -decimal sim:/user/readResponse
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| 32 |
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add wave -position end -expand -hexadecimal sim:/user/axiMaster/i_writeResponse
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| 33 |
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add wave -position end -expand -hexadecimal sim:/user/writeResponse
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| 34 |
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add wave -position end sim:/bist/txFSM
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| 35 |
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add wave -position end sim:/bist/i_txFSM
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| 36 |
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| 37 |
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#OS-VVM solution:
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| 38 |
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#add wave -position end -unsigned -format analog-step -height 80 -scale 0.4e-17 sim:/user/axiMaster_out.tData
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| 40 |
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#LFSR solution:
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| 41 |
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add wave -position end -unsigned -format analog-step -height 80 -scale 0.18e-7 sim:/user/axiMaster_out.tData
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| 42 |
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| 43 |
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add wave -position end sim:/bist/i_prbs/isParallelLoad
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| 44 |
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add wave -position end sim:/bist/i_prbs/loadEn
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| 45 |
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add wave -position end sim:/bist/i_prbs/loaded
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| 46 |
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add wave -position end sim:/bist/i_prbs/i_loaded
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| 47 |
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add wave -position end sim:/bist/i_prbs/load
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| 48 |
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add wave -position end -hexadecimal sim:/bist/i_prbs/d
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| 49 |
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add wave -position end -hexadecimal sim:/bist/i_prbs/seed
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| 50 |
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add wave -position end -hexadecimal sim:/bist/prbs
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| 51 |
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| 52 |
41 |
daniel.kho |
run -all;
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| 53 |
29 |
daniel.kho |
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| 54 |
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wave zoomfull
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| 55 |
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#.wave.tree zoomfull # with some versions of ModelSim
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