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/* ********************************************************************************* */
/*        Wishbone compatible IO module for read/write of filter coefficients        */
/*                                                                                   */
/*  Author:  Chuck Cox (chuck100@home.com)                                           */
/*                                                                                   */
/* Wishbone data:                                                                    */
/* General description:  16x5 register file                                          */
/* Supported cycles:  Slave Read/write, block read/write, RMW                        */
/* Data port size:  16 bit                                                           */
/* Data port granularity: 16 bit                                                     */
/* Data port maximum operand size:  16 bit                                           */
/*                                                                                   */
/*      Addr    register                                                             */
/*      0x0     a11                                                                  */
/*      0x1     a12                                                                  */
/*      0x2     b10                                                                  */
/*      0x3     b11                                                                  */
/*      0x4     b12                                                                  */
/*                                                                                   */
/*  Filter coefficients need to be written as 16 bit twos complement fractional      */
/*  numbers.  For example:  0100_0000_0000_0001 = 2^-1 + 2^-15 = .500030517578125    */
/*                                                                                   */
/*  The biquad filter module is parameterized.  If a filter with coefficients less   */
/*  than 16 bits in length is selected then the most significant bits shall be used. */
/* ********************************************************************************* */
 
 
module coefio
        (
        clk_i,
        rst_i,
        we_i,
        stb_i,
        ack_o,
        dat_i,
        dat_o,
        adr_i,
        a11,
        a12,
        b10,
        b11,
        b12
        );
 
 
 
input           clk_i;
input           rst_i;
input           we_i;
input           stb_i;
output          ack_o;
input   [15:0]   dat_i;
output  [15:0]   dat_o;
input   [2:0]    adr_i;
output  [15:0]   a11;
output  [15:0]   a12;
output  [15:0]   b10;
output  [15:0]   b11;
output  [15:0]   b12;
 
 
reg     [15:0]   a11;
reg     [15:0]   a12;
reg     [15:0]   b10;
reg     [15:0]   b11;
reg     [15:0]   b12;
 
wire            ack_o;
wire            sel_a11;
wire            sel_a12;
wire            sel_b10;
wire            sel_b11;
wire            sel_b12;
 
assign sel_a11 = (adr_i == 3'b000);
assign sel_a12 = (adr_i == 3'b001);
assign sel_b10 = (adr_i == 3'b010);
assign sel_b11 = (adr_i == 3'b011);
assign sel_b12 = (adr_i == 3'b100);
 
assign ack_o = stb_i;
 
always @(posedge clk_i or posedge rst_i)
if ( rst_i )
  begin
    a11 <= 15'd0;
    a12 <= 15'd0;
    b10 <= 15'd0;
    b11 <= 15'd0;
    b12 <= 15'd0;
  end
else
  begin
    a11 <= (stb_i & we_i & sel_a11) ? (dat_i) : (a11);
    a12 <= (stb_i & we_i & sel_a12) ? (dat_i) : (a12);
    b10 <= (stb_i & we_i & sel_b10) ? (dat_i) : (b10);
    b11 <= (stb_i & we_i & sel_b11) ? (dat_i) : (b11);
    b12 <= (stb_i & we_i & sel_b12) ? (dat_i) : (b12);
  end
 
assign dat_o = sel_a11 ? (a11) :
                ((sel_a12) ? (a12) :
                ((sel_b10) ? (b10) :
                ((sel_b11) ? (b11) :
                ((sel_b12) ? (b12) :
                (16'h0000)))));
 
 
endmodule

Line No.	Rev	Author	Line
1	6	root	`/* ********************************************************************************* */`
2			`/* Wishbone compatible IO module for read/write of filter coefficients */`
3			`/* */`
4			`/* Author: Chuck Cox (chuck100@home.com) */`
5			`/* */`
6			`/* Wishbone data: */`
7			`/* General description: 16x5 register file */`
8			`/* Supported cycles: Slave Read/write, block read/write, RMW */`
9			`/* Data port size: 16 bit */`
10			`/* Data port granularity: 16 bit */`
11			`/* Data port maximum operand size: 16 bit */`
12			`/* */`
13			`/* Addr register */`
14			`/* 0x0 a11 */`
15			`/* 0x1 a12 */`
16			`/* 0x2 b10 */`
17			`/* 0x3 b11 */`
18			`/* 0x4 b12 */`
19			`/* */`
20			`/* Filter coefficients need to be written as 16 bit twos complement fractional */`
21			`/* numbers. For example: 0100_0000_0000_0001 = 2^-1 + 2^-15 = .500030517578125 */`
22			`/* */`
23			`/* The biquad filter module is parameterized. If a filter with coefficients less */`
24			`/* than 16 bits in length is selected then the most significant bits shall be used. */`
25			`/* ********************************************************************************* */`
26
27
28			`module coefio`
29			`(`
30			`clk_i,`
31			`rst_i,`
32			`we_i,`
33			`stb_i,`
34			`ack_o,`
35			`dat_i,`
36			`dat_o,`
37			`adr_i,`
38			`a11,`
39			`a12,`
40			`b10,`
41			`b11,`
42			`b12`
43			`);`
44
45
46
47			`input clk_i;`
48			`input rst_i;`
49			`input we_i;`
50			`input stb_i;`
51			`output ack_o;`
52			`input [15:0] dat_i;`
53			`output [15:0] dat_o;`
54			`input [2:0] adr_i;`
55			`output [15:0] a11;`
56			`output [15:0] a12;`
57			`output [15:0] b10;`
58			`output [15:0] b11;`
59			`output [15:0] b12;`
60
61
62			`reg [15:0] a11;`
63			`reg [15:0] a12;`
64			`reg [15:0] b10;`
65			`reg [15:0] b11;`
66			`reg [15:0] b12;`
67
68			`wire ack_o;`
69			`wire sel_a11;`
70			`wire sel_a12;`
71			`wire sel_b10;`
72			`wire sel_b11;`
73			`wire sel_b12;`
74
75			`assign sel_a11 = (adr_i == 3'b000);`
76			`assign sel_a12 = (adr_i == 3'b001);`
77			`assign sel_b10 = (adr_i == 3'b010);`
78			`assign sel_b11 = (adr_i == 3'b011);`
79			`assign sel_b12 = (adr_i == 3'b100);`
80
81			`assign ack_o = stb_i;`
82
83			`always @(posedge clk_i or posedge rst_i)`
84			`if ( rst_i )`
85			`begin`
86			`a11 <= 15'd0;`
87			`a12 <= 15'd0;`
88			`b10 <= 15'd0;`
89			`b11 <= 15'd0;`
90			`b12 <= 15'd0;`
91			`end`
92			`else`
93			`begin`
94			`a11 <= (stb_i & we_i & sel_a11) ? (dat_i) : (a11);`
95			`a12 <= (stb_i & we_i & sel_a12) ? (dat_i) : (a12);`
96			`b10 <= (stb_i & we_i & sel_b10) ? (dat_i) : (b10);`
97			`b11 <= (stb_i & we_i & sel_b11) ? (dat_i) : (b11);`
98			`b12 <= (stb_i & we_i & sel_b12) ? (dat_i) : (b12);`
99			`end`
100
101			`assign dat_o = sel_a11 ? (a11) :`
102			`((sel_a12) ? (a12) :`
103			`((sel_b10) ? (b10) :`
104			`((sel_b11) ? (b11) :`
105			`((sel_b12) ? (b12) :`
106			`(16'h0000)))));`
107
108
109			`endmodule`

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[/] [biquad/] [web_uploads/] [coefio.v] - Blame information for rev 6