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[/] [bubblesortmodule/] [trunk/] [sim/] [rtl_sim/] [src/] [testbench.v] - Blame information for rev 5

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////////////////////////////////////////////////
 
module testbench;
 
        // Inputs
        reg clk;
        reg rst;
        reg load0_i;
        reg load1_i;
        reg load2_i;
        reg load3_i;
        reg load4_i;
        reg load5_i;
        reg load6_i;
        reg [7:0] writedata0_i;
        reg [7:0] writedata1_i;
        reg [7:0] writedata2_i;
        reg [7:0] writedata3_i;
        reg [7:0] writedata4_i;
        reg [7:0] writedata5_i;
        reg [7:0] writedata6_i;
        reg start_i;
        reg abort_i;
 
        // Outputs
        wire [7:0] readdata0_o;
        wire [7:0] readdata1_o;
        wire [7:0] readdata2_o;
        wire [7:0] readdata3_o;
        wire [7:0] readdata4_o;
        wire [7:0] readdata5_o;
        wire [7:0] readdata6_o;
        wire done_o;
        wire interrupt_o;
 
        // Instantiate the Unit Under Test
        bublesort #(8,7)
        uut (
                .clk(clk),
                .rst(rst),
                .load_i({load6_i,load5_i,load4_i,load3_i,load2_i,load1_i,load0_i}),
                .writedata_i({writedata6_i,writedata5_i,writedata4_i,writedata3_i,writedata2_i,writedata1_i,writedata0_i}),
                .readdata_o({readdata6_o,readdata5_o,readdata4_o,readdata3_o,readdata2_o,readdata1_o,readdata0_o}),
                .start_i(start_i),
                .done_o(done_o),
                .interrupt_o(interrupt_o),
                .abort_i(abort_i)
        );
 
        initial begin
                // Initialize Inputs
                clk = 0;
                rst = 1;
                load0_i = 0;
 
                writedata0_i = 0;
 
                load1_i = 0;
 
                writedata1_i = 0;
 
                load2_i = 0;
 
                writedata2_i = 0;
 
                load3_i = 0;
 
                writedata3_i = 0;
 
                load4_i = 0;
 
                writedata4_i = 0;
 
                load5_i = 0;
 
                writedata5_i = 0;
 
                load6_i = 0;
 
                writedata6_i = 0;
 
                start_i = 0;
                abort_i = 0;
 
                // Wait 10 ns
                #10;
 
                // Stimulus 
        clk = 1; #5 clk = 0; #5;
 
        clk = 1; #5 clk = 0; #5;
 
        clk = 1; #1;
 
            rst = 0;
 
            #4; clk = 0; #5;
 
        clk = 1; #5 clk = 0; #5;
 
        clk = 1; #1;
 
            writedata0_i = 0;
 
            writedata1_i = 7;
 
            writedata2_i = 100;
 
            writedata3_i = 254;
 
            writedata4_i = 255;
 
            writedata5_i = 128;
 
            writedata6_i = 2;
 
            load0_i = 1;
 
            load1_i = 1;
 
            load2_i = 1;
 
            load3_i = 1;
 
            load4_i = 1;
 
            load5_i = 1;
 
            load6_i = 1;
 
            #4; clk = 0; #5;
 
        clk = 1; #1;
 
            writedata0_i = 0;
 
            writedata1_i = 0;
 
            writedata2_i = 0;
 
            writedata3_i = 0;
 
            writedata4_i = 0;
 
            writedata5_i = 0;
 
            writedata6_i = 0;
 
            load0_i = 0;
 
            load1_i = 0;
 
            load2_i = 0;
 
            load3_i = 0;
 
            load4_i = 0;
 
            load5_i = 0;
 
            load6_i = 0;
 
            #4; clk = 0; #5;
 
        clk = 1; #1;
 
            start_i = 1;
 
            #4; clk = 0; #5;
 
        clk = 1; #1;
 
            start_i = 0;
 
            #4; clk = 0; #5;
 
        while(!interrupt_o) begin
 
            clk = 1; #5 clk = 0; #5;
 
        end
 
        clk = 1; #5 clk = 0; #5;
 
        clk = 1; #5 clk = 0; #5;
 
        clk = 1; #5 clk = 0; #5;
 
        clk = 1; #5 clk = 0; #5;
 
        clk = 1; #5 clk = 0; #5;
 
        clk = 1; #5 clk = 0; #5;
 
        clk = 1; #5 clk = 0; #5;
 
        clk = 1; #5 clk = 0; #5;
 
        end
 
endmodule
 

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[/] [bubblesortmodule/] [trunk/] [sim/] [rtl_sim/] [src/] [testbench.v] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	avramionut
2			`////////////////////////////////////////////////`
3
4			`module testbench;`
5
6			`// Inputs`
7			`reg clk;`
8			`reg rst;`
9			`reg load0_i;`
10			`reg load1_i;`
11			`reg load2_i;`
12			`reg load3_i;`
13			`reg load4_i;`
14			`reg load5_i;`
15			`reg load6_i;`
16			`reg [7:0] writedata0_i;`
17			`reg [7:0] writedata1_i;`
18			`reg [7:0] writedata2_i;`
19			`reg [7:0] writedata3_i;`
20			`reg [7:0] writedata4_i;`
21			`reg [7:0] writedata5_i;`
22			`reg [7:0] writedata6_i;`
23			`reg start_i;`
24			`reg abort_i;`
25
26			`// Outputs`
27			`wire [7:0] readdata0_o;`
28			`wire [7:0] readdata1_o;`
29			`wire [7:0] readdata2_o;`
30			`wire [7:0] readdata3_o;`
31			`wire [7:0] readdata4_o;`
32			`wire [7:0] readdata5_o;`
33			`wire [7:0] readdata6_o;`
34			`wire done_o;`
35			`wire interrupt_o;`
36
37			`// Instantiate the Unit Under Test`
38			`bublesort #(8,7)`
39			`uut (`
40			`.clk(clk),`
41			`.rst(rst),`
42			`.load_i({load6_i,load5_i,load4_i,load3_i,load2_i,load1_i,load0_i}),`
43			`.writedata_i({writedata6_i,writedata5_i,writedata4_i,writedata3_i,writedata2_i,writedata1_i,writedata0_i}),`
44			`.readdata_o({readdata6_o,readdata5_o,readdata4_o,readdata3_o,readdata2_o,readdata1_o,readdata0_o}),`
45			`.start_i(start_i),`
46			`.done_o(done_o),`
47			`.interrupt_o(interrupt_o),`
48			`.abort_i(abort_i)`
49			`);`
50
51			`initial begin`
52			`// Initialize Inputs`
53			`clk = 0;`
54			`rst = 1;`
55			`load0_i = 0;`
56
57			`writedata0_i = 0;`
58
59			`load1_i = 0;`
60
61			`writedata1_i = 0;`
62
63			`load2_i = 0;`
64
65			`writedata2_i = 0;`
66
67			`load3_i = 0;`
68
69			`writedata3_i = 0;`
70
71			`load4_i = 0;`
72
73			`writedata4_i = 0;`
74
75			`load5_i = 0;`
76
77			`writedata5_i = 0;`
78
79			`load6_i = 0;`
80
81			`writedata6_i = 0;`
82
83			`start_i = 0;`
84			`abort_i = 0;`
85
86			`// Wait 10 ns`
87			`#10;`
88
89			`// Stimulus`
90			`clk = 1; #5 clk = 0; #5;`
91
92			`clk = 1; #5 clk = 0; #5;`
93
94			`clk = 1; #1;`
95
96			`rst = 0;`
97
98			`#4; clk = 0; #5;`
99
100			`clk = 1; #5 clk = 0; #5;`
101
102			`clk = 1; #1;`
103
104			`writedata0_i = 0;`
105
106			`writedata1_i = 7;`
107
108			`writedata2_i = 100;`
109
110			`writedata3_i = 254;`
111
112			`writedata4_i = 255;`
113
114			`writedata5_i = 128;`
115
116			`writedata6_i = 2;`
117
118			`load0_i = 1;`
119
120			`load1_i = 1;`
121
122			`load2_i = 1;`
123
124			`load3_i = 1;`
125
126			`load4_i = 1;`
127
128			`load5_i = 1;`
129
130			`load6_i = 1;`
131
132			`#4; clk = 0; #5;`
133
134			`clk = 1; #1;`
135
136			`writedata0_i = 0;`
137
138			`writedata1_i = 0;`
139
140			`writedata2_i = 0;`
141
142			`writedata3_i = 0;`
143
144			`writedata4_i = 0;`
145
146			`writedata5_i = 0;`
147
148			`writedata6_i = 0;`
149
150			`load0_i = 0;`
151
152			`load1_i = 0;`
153
154			`load2_i = 0;`
155
156			`load3_i = 0;`
157
158			`load4_i = 0;`
159
160			`load5_i = 0;`
161
162			`load6_i = 0;`
163
164			`#4; clk = 0; #5;`
165
166			`clk = 1; #1;`
167
168			`start_i = 1;`
169
170			`#4; clk = 0; #5;`
171
172			`clk = 1; #1;`
173
174			`start_i = 0;`
175
176			`#4; clk = 0; #5;`
177
178			`while(!interrupt_o) begin`
179
180			`clk = 1; #5 clk = 0; #5;`
181
182			`end`
183
184			`clk = 1; #5 clk = 0; #5;`
185
186			`clk = 1; #5 clk = 0; #5;`
187
188			`clk = 1; #5 clk = 0; #5;`
189
190			`clk = 1; #5 clk = 0; #5;`
191
192			`clk = 1; #5 clk = 0; #5;`
193
194			`clk = 1; #5 clk = 0; #5;`
195
196			`clk = 1; #5 clk = 0; #5;`
197
198			`clk = 1; #5 clk = 0; #5;`
199
200			`end`
201
202			`endmodule`
203