OpenCores
URL https://opencores.org/ocsvn/bustap-jtag/bustap-jtag/trunk

Subversion Repositories bustap-jtag

[/] [bustap-jtag/] [trunk/] [par/] [xilinx/] [xps/] [zynq_bram.mhs] - Blame information for rev 20

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 20 ash_riple 
 
2 
 PARAMETER VERSION = 2.1.0
3 
 
4 
 
5 
 PORT PS_SRSTB = PS_SRSTB, DIR = I
6 
 PORT PS_CLK = PS_CLK, DIR = I, SIGIS = CLK
7 
 PORT PS_PORB = PS_PORB, DIR = I
8 
 PORT PS_DDR_Clk = PS_DDR_Clk, DIR = IO, SIGIS = CLK
9 
 PORT PS_DDR_Clk_n = PS_DDR_Clk_n, DIR = IO, SIGIS = CLK
10 
 PORT PS_DDR_CKE = PS_DDR_CKE, DIR = IO
11 
 PORT PS_DDR_CS_n = PS_DDR_CS_n, DIR = IO
12 
 PORT PS_DDR_RAS_n = PS_DDR_RAS_n, DIR = IO
13 
 PORT PS_DDR_CAS_n = PS_DDR_CAS_n, DIR = IO
14 
 PORT PS_DDR_WEB = PS_DDR_WEB, DIR = O
15 
 PORT PS_DDR_BankAddr = PS_DDR_BankAddr, DIR = IO, VEC = [2:0]
16 
 PORT PS_DDR_Addr = PS_DDR_Addr, DIR = IO, VEC = [14:0]
17 
 PORT PS_DDR_ODT = PS_DDR_ODT, DIR = IO
18 
 PORT PS_DDR_DRSTB = PS_DDR_DRSTB, DIR = IO, SIGIS = RST
19 
 PORT PS_DDR_DQ = PS_DDR_DQ, DIR = IO, VEC = [31:0]
20 
 PORT PS_DDR_DM = PS_DDR_DM, DIR = IO, VEC = [3:0]
21 
 PORT PS_DDR_DQS = PS_DDR_DQS, DIR = IO, VEC = [3:0]
22 
 PORT PS_DDR_DQS_n = PS_DDR_DQS_n, DIR = IO, VEC = [3:0]
23 
 PORT PS_DDR_VRN = PS_DDR_VRN, DIR = IO
24 
 PORT PS_DDR_VRP = PS_DDR_VRP, DIR = IO
25 
 PORT PS_MIO = PS_MIO, DIR = IO, VEC = [53:0]
26 
 
27 
 
28 
BEGIN processing_system7
29 
 PARAMETER INSTANCE = PS
30 
 PARAMETER HW_VER = 4.02.a
31 
 PARAMETER C_DDR_RAM_HIGHADDR = 0x3FFFFFFF
32 
 PARAMETER C_EN_EMIO_CAN0 = 0
33 
 PARAMETER C_EN_EMIO_CAN1 = 0
34 
 PARAMETER C_EN_EMIO_ENET0 = 0
35 
 PARAMETER C_EN_EMIO_ENET1 = 0
36 
 PARAMETER C_EN_EMIO_I2C0 = 0
37 
 PARAMETER C_EN_EMIO_I2C1 = 0
38 
 PARAMETER C_EN_EMIO_PJTAG = 0
39 
 PARAMETER C_EN_EMIO_SDIO0 = 0
40 
 PARAMETER C_EN_EMIO_CD_SDIO0 = 0
41 
 PARAMETER C_EN_EMIO_WP_SDIO0 = 0
42 
 PARAMETER C_EN_EMIO_SDIO1 = 0
43 
 PARAMETER C_EN_EMIO_CD_SDIO1 = 0
44 
 PARAMETER C_EN_EMIO_WP_SDIO1 = 0
45 
 PARAMETER C_EN_EMIO_SPI0 = 0
46 
 PARAMETER C_EN_EMIO_SPI1 = 0
47 
 PARAMETER C_EN_EMIO_SRAM_INT = 0
48 
 PARAMETER C_EN_EMIO_TRACE = 0
49 
 PARAMETER C_EN_EMIO_TTC0 = 1
50 
 PARAMETER C_EN_EMIO_TTC1 = 0
51 
 PARAMETER C_EN_EMIO_UART0 = 0
52 
 PARAMETER C_EN_EMIO_UART1 = 0
53 
 PARAMETER C_EN_EMIO_MODEM_UART0 = 0
54 
 PARAMETER C_EN_EMIO_MODEM_UART1 = 0
55 
 PARAMETER C_EN_EMIO_WDT = 1
56 
 PARAMETER C_EN_QSPI = 1
57 
 PARAMETER C_EN_SMC = 0
58 
 PARAMETER C_EN_CAN0 = 1
59 
 PARAMETER C_EN_CAN1 = 0
60 
 PARAMETER C_EN_ENET0 = 1
61 
 PARAMETER C_EN_ENET1 = 0
62 
 PARAMETER C_EN_I2C0 = 1
63 
 PARAMETER C_EN_I2C1 = 0
64 
 PARAMETER C_EN_PJTAG = 0
65 
 PARAMETER C_EN_SDIO0 = 1
66 
 PARAMETER C_EN_SDIO1 = 0
67 
 PARAMETER C_EN_SPI0 = 0
68 
 PARAMETER C_EN_SPI1 = 0
69 
 PARAMETER C_EN_TRACE = 0
70 
 PARAMETER C_EN_TTC0 = 1
71 
 PARAMETER C_EN_TTC1 = 0
72 
 PARAMETER C_EN_UART0 = 0
73 
 PARAMETER C_EN_UART1 = 1
74 
 PARAMETER C_EN_MODEM_UART0 = 0
75 
 PARAMETER C_EN_MODEM_UART1 = 0
76 
 PARAMETER C_EN_USB0 = 1
77 
 PARAMETER C_EN_USB1 = 0
78 
 PARAMETER C_EN_WDT = 1
79 
 PARAMETER C_EN_DDR = 1
80 
 PARAMETER C_EN_GPIO = 1
81 
 PARAMETER C_FCLK_CLK0_FREQ = 100000000
82 
 PARAMETER C_FCLK_CLK1_FREQ = 50000000
83 
 PARAMETER C_FCLK_CLK2_FREQ = 50000000
84 
 PARAMETER C_FCLK_CLK3_FREQ = 50000000
85 
 PARAMETER C_USE_M_AXI_GP0 = 1
86 
 PARAMETER C_USE_M_AXI_GP1 = 1
87 
 PARAMETER C_USE_CR_FABRIC = 1
88 
 PARAMETER C_NUM_F2P_INTR_INPUTS = 7
89 
 PARAMETER C_USE_S_AXI_GP0 = 0
90 
 PARAMETER C_USE_S_AXI_GP1 = 0
91 
 PARAMETER C_USE_S_AXI_HP0 = 1
92 
 PARAMETER C_USE_S_AXI_HP1 = 1
93 
 PARAMETER C_USE_S_AXI_HP2 = 1
94 
 PARAMETER C_USE_S_AXI_HP3 = 1
95 
 PARAMETER C_S_AXI_HP0_BASEADDR = 0x00000000
96 
 PARAMETER C_S_AXI_HP0_HIGHADDR = 0x3FFFFFFF
97 
 PARAMETER C_EMIO_GPIO_WIDTH = 64
98 
 PARAMETER C_EN_EMIO_GPIO = 0
99 
 BUS_INTERFACE M_AXI_GP0 = AXI_PS_PL
100 
 PORT PS_SRSTB = PS_SRSTB
101 
 PORT PS_CLK = PS_CLK
102 
 PORT PS_PORB = PS_PORB
103 
 PORT FCLK_CLK0 = PS_FCLK_CLK0
104 
 PORT DDR_Clk = PS_DDR_Clk
105 
 PORT DDR_Clk_n = PS_DDR_Clk_n
106 
 PORT DDR_CKE = PS_DDR_CKE
107 
 PORT DDR_CS_n = PS_DDR_CS_n
108 
 PORT DDR_RAS_n = PS_DDR_RAS_n
109 
 PORT DDR_CAS_n = PS_DDR_CAS_n
110 
 PORT DDR_WEB = PS_DDR_WEB
111 
 PORT DDR_BankAddr = PS_DDR_BankAddr
112 
 PORT DDR_Addr = PS_DDR_Addr
113 
 PORT DDR_ODT = PS_DDR_ODT
114 
 PORT DDR_DRSTB = PS_DDR_DRSTB
115 
 PORT DDR_DQ = PS_DDR_DQ
116 
 PORT DDR_DM = PS_DDR_DM
117 
 PORT DDR_DQS = PS_DDR_DQS
118 
 PORT DDR_DQS_n = PS_DDR_DQS_n
119 
 PORT DDR_VRN = PS_DDR_VRN
120 
 PORT DDR_VRP = PS_DDR_VRP
121 
 PORT MIO = PS_MIO
122 
 PORT M_AXI_GP1_ACLK = clock_generator_0_CLKOUT0
123 
 PORT M_AXI_GP0_ARESETN = PS_M_AXI_GP0_ARESETN
124 
 PORT M_AXI_GP0_ACLK = clock_generator_0_CLKOUT0
125 
 PORT S_AXI_HP0_ACLK = clock_generator_0_CLKOUT0
126 
 PORT S_AXI_HP1_ACLK = clock_generator_0_CLKOUT0
127 
 PORT S_AXI_HP2_ACLK = clock_generator_0_CLKOUT0
128 
 PORT S_AXI_HP3_ACLK = clock_generator_0_CLKOUT0
129 
 PORT FCLK_RESET0_N = PS_FCLK_RESET0_N
130 
END
131 
 
132 
BEGIN bram_block
133 
 PARAMETER INSTANCE = PL_bram_block
134 
 PARAMETER HW_VER = 1.00.a
135 
 BUS_INTERFACE PORTA = axi_bram_ctrl_1_BRAM_PORTA
136 
 BUS_INTERFACE PORTB = axi_bram_ctrl_1_BRAM_PORTB
137 
END
138 
 
139 
BEGIN axi_bram_ctrl
140 
 PARAMETER INSTANCE = PL_bram_ctrl
141 
 PARAMETER HW_VER = 1.03.a
142 
 PARAMETER C_S_AXI_BASEADDR = 0x40000000
143 
 PARAMETER C_S_AXI_HIGHADDR = 0x40000FFF
144 
 PARAMETER C_INTERCONNECT_S_AXI_MASTERS = PS.M_AXI_GP0
145 
 BUS_INTERFACE S_AXI = AXI_PS_PL
146 
 BUS_INTERFACE BRAM_PORTA = axi_bram_ctrl_1_BRAM_PORTA
147 
 BUS_INTERFACE BRAM_PORTB = axi_bram_ctrl_1_BRAM_PORTB
148 
 PORT S_AXI_ACLK = clock_generator_0_CLKOUT0
149 
END
150 
 
151 
BEGIN axi_interconnect
152 
 PARAMETER INSTANCE = AXI_PS_PL
153 
 PARAMETER HW_VER = 1.06.a
154 
 PORT INTERCONNECT_ACLK = clock_generator_0_CLKOUT0
155 
 PORT INTERCONNECT_ARESETN = PS_M_AXI_GP0_ARESETN
156 
END
157 
 
158 
BEGIN clock_generator
159 
 PARAMETER INSTANCE = clock_generator_0
160 
 PARAMETER HW_VER = 4.03.a
161 
 PARAMETER C_CLKIN_FREQ = 100000000
162 
 PARAMETER C_CLKOUT0_FREQ = 75000000
163 
 PARAMETER C_EXT_RESET_HIGH = 0
164 
 PARAMETER C_CLKOUT1_FREQ = 50000000
165 
 PARAMETER C_CLKOUT2_FREQ = 0
166 
 PORT CLKIN = PS_FCLK_CLK0
167 
 PORT RST = PS_FCLK_RESET0_N
168 
 PORT CLKOUT0 = clock_generator_0_CLKOUT0
169 
END
170 
 
171 
BEGIN bustap_jtag
172 
 PARAMETER INSTANCE = bustap_jtag_0
173 
 PARAMETER HW_VER = 1.00.a
174 
 BUS_INTERFACE MON_AXI = PS.M_AXI_GP0
175 
 PORT ACLK = clock_generator_0_CLKOUT0
176 
 PORT CHIPSCOPE_ICON_CONTROL0 = chipscope_icon_0_control0
177 
 PORT CHIPSCOPE_ICON_CONTROL1 = chipscope_icon_0_control1
178 
 PORT CHIPSCOPE_ICON_CONTROL2 = chipscope_icon_0_control2
179 
END
180 
 
181 
BEGIN chipscope_icon
182 
 PARAMETER INSTANCE = chipscope_icon_0
183 
 PARAMETER HW_VER = 1.06.a
184 
 PARAMETER C_NUM_CONTROL_PORTS = 3
185 
 PORT control0 = chipscope_icon_0_control0
186 
 PORT control1 = chipscope_icon_0_control1
187 
 PORT control2 = chipscope_icon_0_control2
188 
END
189 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.