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[/] [bustap-jtag/] [trunk/] [rtl/] [altera/] [virtual_jtag_adda_trig.v] - Blame information for rev 2

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module virtual_jtag_adda_trig(trig_out);
 
parameter trig_width  = 32;
 
output [trig_width-1:0] trig_out;
 
reg [trig_width-1:0] trig_out;
 
wire tdi, tck, cdr, cir, e1dr, e2dr, pdr, sdr, udr, uir;
reg  tdo;
reg  [trig_width-1:0] trig_instr_reg;
reg  bypass_reg;
 
wire [1:0] ir_in;
wire trig_instr = ~ir_in[1] &  ir_in[0]; // 1
 
always @(posedge tck)
begin
  if (trig_instr && e1dr)
    trig_out <= trig_instr_reg;
end
 
/* trig_instr Instruction Handler */
always @ (posedge tck)
  if ( trig_instr && cdr )
    trig_instr_reg <= trig_instr_reg;
  else if ( trig_instr && sdr )
    trig_instr_reg <= {tdi, trig_instr_reg[trig_width-1:1]};
 
/* Bypass register */
always @ (posedge tck)
  bypass_reg <= tdi;
 
/* Node TDO Output */
always @ ( trig_instr, trig_instr_reg, bypass_reg )
begin
  if (trig_instr)
    tdo <= trig_instr_reg[0];
  else
    tdo <= bypass_reg;// Used to maintain the continuity of the scan chain.
end
 
sld_virtual_jtag        sld_virtual_jtag_component (
                                .ir_in (ir_in),
                                .ir_out (2'b0),
                                .tdo (tdo),
                                .tdi (tdi),
                                .tms (),
                                .tck (tck),
                                .virtual_state_cir (cir),
                                .virtual_state_pdr (pdr),
                                .virtual_state_uir (uir),
                                .virtual_state_sdr (sdr),
                                .virtual_state_cdr (cdr),
                                .virtual_state_udr (udr),
                                .virtual_state_e1dr (e1dr),
                                .virtual_state_e2dr (e2dr),
                                .jtag_state_rti (),
                                .jtag_state_e1dr (),
                                .jtag_state_e2dr (),
                                .jtag_state_pir (),
                                .jtag_state_tlr (),
                                .jtag_state_sir (),
                                .jtag_state_cir (),
                                .jtag_state_uir (),
                                .jtag_state_pdr (),
                                .jtag_state_sdrs (),
                                .jtag_state_sdr (),
                                .jtag_state_cdr (),
                                .jtag_state_udr (),
                                .jtag_state_sirs (),
                                .jtag_state_e1ir (),
                                .jtag_state_e2ir ());
        defparam
                sld_virtual_jtag_component.sld_auto_instance_index = "NO",
                sld_virtual_jtag_component.sld_instance_index = 2,
                sld_virtual_jtag_component.sld_ir_width = 2,
                sld_virtual_jtag_component.sld_sim_action = "((1,1,1,2))",
                sld_virtual_jtag_component.sld_sim_n_scan = 1,
                sld_virtual_jtag_component.sld_sim_total_length = 2;
 
endmodule

Line No.	Rev	Author	Line
1	2	ash_riple	`module virtual_jtag_adda_trig(trig_out);`
2
3			`parameter trig_width = 32;`
4
5			`output [trig_width-1:0] trig_out;`
6
7			`reg [trig_width-1:0] trig_out;`
8
9			`wire tdi, tck, cdr, cir, e1dr, e2dr, pdr, sdr, udr, uir;`
10			`reg tdo;`
11			`reg [trig_width-1:0] trig_instr_reg;`
12			`reg bypass_reg;`
13
14			`wire [1:0] ir_in;`
15			`wire trig_instr = ~ir_in[1] & ir_in[0]; // 1`
16
17			`always @(posedge tck)`
18			`begin`
19			`if (trig_instr && e1dr)`
20			`trig_out <= trig_instr_reg;`
21			`end`
22
23			`/* trig_instr Instruction Handler */`
24			`always @ (posedge tck)`
25			`if ( trig_instr && cdr )`
26			`trig_instr_reg <= trig_instr_reg;`
27			`else if ( trig_instr && sdr )`
28			`trig_instr_reg <= {tdi, trig_instr_reg[trig_width-1:1]};`
29
30			`/* Bypass register */`
31			`always @ (posedge tck)`
32			`bypass_reg <= tdi;`
33
34			`/* Node TDO Output */`
35			`always @ ( trig_instr, trig_instr_reg, bypass_reg )`
36			`begin`
37			`if (trig_instr)`
38			`tdo <= trig_instr_reg[0];`
39			`else`
40			`tdo <= bypass_reg;// Used to maintain the continuity of the scan chain.`
41			`end`
42
43			`sld_virtual_jtag sld_virtual_jtag_component (`
44			`.ir_in (ir_in),`
45			`.ir_out (2'b0),`
46			`.tdo (tdo),`
47			`.tdi (tdi),`
48			`.tms (),`
49			`.tck (tck),`
50			`.virtual_state_cir (cir),`
51			`.virtual_state_pdr (pdr),`
52			`.virtual_state_uir (uir),`
53			`.virtual_state_sdr (sdr),`
54			`.virtual_state_cdr (cdr),`
55			`.virtual_state_udr (udr),`
56			`.virtual_state_e1dr (e1dr),`
57			`.virtual_state_e2dr (e2dr),`
58			`.jtag_state_rti (),`
59			`.jtag_state_e1dr (),`
60			`.jtag_state_e2dr (),`
61			`.jtag_state_pir (),`
62			`.jtag_state_tlr (),`
63			`.jtag_state_sir (),`
64			`.jtag_state_cir (),`
65			`.jtag_state_uir (),`
66			`.jtag_state_pdr (),`
67			`.jtag_state_sdrs (),`
68			`.jtag_state_sdr (),`
69			`.jtag_state_cdr (),`
70			`.jtag_state_udr (),`
71			`.jtag_state_sirs (),`
72			`.jtag_state_e1ir (),`
73			`.jtag_state_e2ir ());`
74			`defparam`
75			`sld_virtual_jtag_component.sld_auto_instance_index = "NO",`
76			`sld_virtual_jtag_component.sld_instance_index = 2,`
77			`sld_virtual_jtag_component.sld_ir_width = 2,`
78			`sld_virtual_jtag_component.sld_sim_action = "((1,1,1,2))",`
79			`sld_virtual_jtag_component.sld_sim_n_scan = 1,`
80			`sld_virtual_jtag_component.sld_sim_total_length = 2;`
81
82			`endmodule`

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[/] [bustap-jtag/] [trunk/] [rtl/] [altera/] [virtual_jtag_adda_trig.v] - Blame information for rev 2