URL https://opencores.org/ocsvn/bustap-jtag/bustap-jtag/trunk

Subversion Repositories bustap-jtag

[/] [bustap-jtag/] [trunk/] [rtl/] [xilinx/] [coregen/] [chipscope_icon.v] - Blame information for rev 18

Line No.	Rev	Author	Line
1	18	ash_riple	`///////////////////////////////////////////////////////////////////////////////`
2			`// Copyright (c) 2012 Xilinx, Inc.`
3			`// All Rights Reserved`
4			`///////////////////////////////////////////////////////////////////////////////`
5			`// ____ ____`
6			`// / /\/ /`
7			`// /___/ \ / Vendor : Xilinx`
8			`// \ \ \/ Version : 14.2`
9			`// \ \ Application: Xilinx CORE Generator`
10			`// / / Filename : chipscope_icon.v`
11			`// /___/ /\ Timestamp : Mon Nov 19 22:31:40 �й��׼ʱ�� 2012`
12			`// \ \ / \`
13			`// \___\/\___\`
14			`//`
15			`// Design Name: Verilog Synthesis Wrapper`
16			`///////////////////////////////////////////////////////////////////////////////`
17			`// This wrapper is used to integrate with Project Navigator and PlanAhead`
18
19			`timescale 1ns/1ps
20
21			`module chipscope_icon(`
22			`CONTROL0,`
23			`CONTROL1,`
24			`CONTROL2);`
25
26
27			`inout [35 : 0] CONTROL0;`
28			`inout [35 : 0] CONTROL1;`
29			`inout [35 : 0] CONTROL2;`
30
31			`endmodule`