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[/] [bustap-jtag/] [trunk/] [rtl/] [xilinx/] [coregen/] [coregen.cgc] - Blame information for rev 18

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   xilinx.com
   project
   coregen
   1.0
   
      
         chipscope_icon
         
         
            chipscope_icon
            false
            3
            true
            external
            false
            false
            USER1
            false
         
         
            
               
                  coregen
                  ./
                  ./tmp/
                  ./tmp/_cg/
               
               
                  xc7z020
                  zynq
                  clg400
                  -2
               
               
                  BusFormatAngleBracketNotRipped
                  Verilog
                  true
                  Other
                  false
                  false
                  false
                  Ngc
                  false
               
               
                  Behavioral
                  Verilog
                  false
               
               
                  2012-07-21+03:11
               
            
         
      
      
         chipscope_vio_fifo
         
         
            chipscope_vio_fifo
            92
            2
            false
            false
            external
            false
            8
            true
            8
            true
            true
            8
            1
            8
            1
            2
            2
            0
            92
            chipscope_vio_fifo
            true
            Component_Name=chipscope_vio_fifo;Enable_Synchronous_Input_Port=true;Enable_Synchronous_Output_Port=true;Enable_Asynchronous_Input_Port=false;Enable_Asynchronous_Output_Port=false;Synchronous_Input_Port_Width=92;Synchronous_Output_Port_Width=2;Asynchronous_Input_Port_Width=8;Asynchronous_Output_Port_Width=8;Invert_Clock_Input=false
            external
            0
            0
            1
         
         
            
               
                  coregen
                  ./
                  ./tmp/
                  ./tmp/_cg/
               
               
                  xc7z020
                  zynq
                  clg400
                  -2
               
               
                  BusFormatAngleBracketNotRipped
                  Verilog
                  true
                  Other
                  false
                  false
                  false
                  Ngc
                  false
               
               
                  Structural
                  Verilog
                  false
               
               
                  2012-07-21+03:12
               
            
            
               
                  customization_generator
               
               
                  model_parameter_resolution_generator
               
               
                  ip_xco_generator
                  
                     ./chipscope_vio_fifo.xco
                     xco
                     Tue Nov 20 02:34:08 GMT 2012
                     0x8A36FA63
                     generationID_4013899584
                  
               
               
                  ngc_netlist_generator
                  
                     ./chipscope_vio_fifo/example_design/chipscope_vio_fifo_bb_lib.v
                     ignore
                     verilogSynthesis
                     Tue Nov 20 02:34:09 GMT 2012
                     0x9770D02F
                     generationID_4013899584
                  
                  
                     ./chipscope_vio_fifo/example_design/example_chipscope_vio_fifo.ucf
                     ignore
                     ucf
                     Tue Nov 20 02:34:11 GMT 2012
                     0x1390C322
                     generationID_4013899584
                  
                  
                     ./chipscope_vio_fifo/example_design/example_chipscope_vio_fifo.v
                     ignore
                     verilogSynthesis
                     Tue Nov 20 02:34:11 GMT 2012
                     0x3E0AC7FF
                     generationID_4013899584
                  
                  
                     ./chipscope_vio_fifo/example_design/example_chipscope_vio_fifo.xdc
                     ignore
                     xdc
                     Tue Nov 20 02:34:11 GMT 2012
                     0x90E75716
                     generationID_4013899584
                  
                  
                     ./chipscope_vio_fifo/implement/chipscope_icon.xco
                     ignore
                     xco
                     Tue Nov 20 02:34:09 GMT 2012
                     0x1FF80BFB
                     generationID_4013899584
                  
                  
                     ./chipscope_vio_fifo/implement/coregen.cgp
                     ignore
                     unknown
                     Tue Nov 20 02:34:09 GMT 2012
                     0x940C30DF
                     generationID_4013899584
                  
                  
                     ./chipscope_vio_fifo/implement/example_chipscope_vio_fifo.prj
                     ignore
                     unknown
                     Tue Nov 20 02:34:10 GMT 2012
                     0xAE724F77
                     generationID_4013899584
                  
                  
                     ./chipscope_vio_fifo/implement/example_chipscope_vio_fifo.xst
                     ignore
                     unknown
                     Tue Nov 20 02:34:13 GMT 2012
                     0xEBBE356D
                     generationID_4013899584
                  
                  
                     ./chipscope_vio_fifo/implement/ise_implement.bat
                     ignore
                     unknown
                     Tue Nov 20 02:34:10 GMT 2012
                     0xEE86AB45
                     generationID_4013899584
                  
                  
                     ./chipscope_vio_fifo/implement/ise_implement.sh
                     ignore
                     unknown
                     Tue Nov 20 02:34:13 GMT 2012
                     0x32780610
                     generationID_4013899584
                  
                  
                     ./chipscope_vio_fifo/implement/pa_ise_implement.tcl
                     ignore
                     tcl
                     Tue Nov 20 02:34:11 GMT 2012
                     0xC8D9F8F9
                     generationID_4013899584
                  
                  
                     ./chipscope_vio_fifo/implement/rdi_implement.tcl
                     ignore
                     tcl
                     Tue Nov 20 02:34:12 GMT 2012
                     0xBD351EB6
                     generationID_4013899584
                  
                  
                     ./chipscope_vio_fifo/implement/v_rdi_implement.tcl
                     ignore
                     tcl
                     Tue Nov 20 02:34:12 GMT 2012
                     0x74FFDD3B
                     generationID_4013899584
                  
                  
                     ./chipscope_vio_fifo/read_me.txt
                     ignore
                     txt
                     Tue Nov 20 02:34:12 GMT 2012
                     0x4A2AE78B
                     generationID_4013899584
                  
                  
                     ./chipscope_vio_fifo.cdc
                     unknown
                     Tue Nov 20 02:35:09 GMT 2012
                     0xB3886A39
                     generationID_4013899584
                  
                  
                     ./chipscope_vio_fifo.constraints/chipscope_vio_fifo.ucf
                     ucf
                     Tue Nov 20 02:35:09 GMT 2012
                     0x46D4F328
                     generationID_4013899584
                  
                  
                     ./chipscope_vio_fifo.constraints/chipscope_vio_fifo.xdc
                     xdc
                     Tue Nov 20 02:35:09 GMT 2012
                     0xC2D11607
                     generationID_4013899584
                  
                  
                     ./chipscope_vio_fifo.ngc
                     ngc
                     Tue Nov 20 02:35:08 GMT 2012
                     0xB712EB26
                     generationID_4013899584
                  
                  
                     ./chipscope_vio_fifo.ucf
                     ignore
                     ucf
                     Tue Nov 20 02:35:09 GMT 2012
                     0x46D4F328
                     generationID_4013899584
                  
                  
                     ./chipscope_vio_fifo.v
                     verilog
                     verilogSynthesis
                     Tue Nov 20 02:35:09 GMT 2012
                     0x84C0DD82
                     generationID_4013899584
                  
                  
                     ./chipscope_vio_fifo.veo
                     veo
                     Tue Nov 20 02:35:09 GMT 2012
                     0xEA70F2E8
                     generationID_4013899584
                  
                  
                     ./chipscope_vio_fifo.xdc
                     ignore
                     xdc
                     Tue Nov 20 02:35:09 GMT 2012
                     0xC2D11607
                     generationID_4013899584
                  
                  
                     ./chipscope_vio_fifo_xmdf.tcl
                     tcl
                     Tue Nov 20 02:34:12 GMT 2012
                     0x136E503B
                     generationID_4013899584
                  
               
               
                  instantiation_template_generator
               
               
                  asy_generator
                  
                     ./chipscope_vio_fifo.asy
                     asy
                     Tue Nov 20 02:35:10 GMT 2012
                     0xEE4A2520
                     generationID_4013899584
                  
               
               
                  xmdf_generator
               
               
                  ise_generator
                  
                     ./chipscope_vio_fifo.gise
                     ignore
                     gise
                     Tue Nov 20 02:35:14 GMT 2012
                     0xE46738AE
                     generationID_4013899584
                  
                  
                     ./chipscope_vio_fifo.xise
                     ignore
                     xise
                     Tue Nov 20 02:35:14 GMT 2012
                     0x78819C93
                     generationID_4013899584
                  
               
               
                  deliver_readme_generator
                  
                     ./chipscope_vio_fifo_readme.txt
                     ignore
                     txtReadme
                     txt
                     Tue Nov 20 02:35:14 GMT 2012
                     0x8A5D60C8
                     generationID_4013899584
                  
               
               
                  flist_generator
                  
                     ./chipscope_vio_fifo_flist.txt
                     ignore
                     txtFlist
                     txt
                     Tue Nov 20 02:35:14 GMT 2012
                     0x2E57030C
                     generationID_4013899584
                  
               
               
                  view_readme_generator
               
            
         
      
      
         chipscope_vio_mask
         
         
            chipscope_vio_mask
            8
            40
            false
            false
            external
            false
            8
            true
            8
            false
            true
            8
            1
            8
            0
            2
            40
            0
            8
            chipscope_vio_mask
            true
            Component_Name=chipscope_vio_mask;Enable_Synchronous_Input_Port=false;Enable_Synchronous_Output_Port=true;Enable_Asynchronous_Input_Port=false;Enable_Asynchronous_Output_Port=false;Synchronous_Input_Port_Width=8;Synchronous_Output_Port_Width=40;Asynchronous_Input_Port_Width=8;Asynchronous_Output_Port_Width=8;Invert_Clock_Input=false
            external
            0
            0
            1
         
         
            
               
                  coregen
                  ./
                  ./tmp/
                  ./tmp/_cg/
               
               
                  xc7z020
                  zynq
                  clg400
                  -2
               
               
                  BusFormatAngleBracketNotRipped
                  Verilog
                  true
                  Other
                  false
                  false
                  false
                  Ngc
                  false
               
               
                  Structural
                  Verilog
                  false
               
               
                  2012-07-21+03:12
               
            
            
               
                  customization_generator
               
               
                  model_parameter_resolution_generator
               
               
                  ip_xco_generator
                  
                     ./chipscope_vio_mask.xco
                     xco
                     Tue Nov 20 02:35:57 GMT 2012
                     0xE543A821
                     generationID_1879581046
                  
               
               
                  ngc_netlist_generator
                  
                     ./chipscope_vio_mask/example_design/chipscope_vio_mask_bb_lib.v
                     ignore
                     verilogSynthesis
                     Tue Nov 20 02:35:57 GMT 2012
                     0x8C39E98A
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_mask/example_design/example_chipscope_vio_mask.ucf
                     ignore
                     ucf
                     Tue Nov 20 02:36:00 GMT 2012
                     0x8A99C5D7
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_mask/example_design/example_chipscope_vio_mask.v
                     ignore
                     verilogSynthesis
                     Tue Nov 20 02:35:59 GMT 2012
                     0x75E2D857
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_mask/example_design/example_chipscope_vio_mask.xdc
                     ignore
                     xdc
                     Tue Nov 20 02:36:00 GMT 2012
                     0xED983B09
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_mask/implement/chipscope_icon.xco
                     ignore
                     xco
                     Tue Nov 20 02:35:58 GMT 2012
                     0x1FF80BFB
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_mask/implement/coregen.cgp
                     ignore
                     unknown
                     Tue Nov 20 02:35:58 GMT 2012
                     0x940C30DF
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_mask/implement/example_chipscope_vio_mask.prj
                     ignore
                     unknown
                     Tue Nov 20 02:35:59 GMT 2012
                     0xDD5C1574
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_mask/implement/example_chipscope_vio_mask.xst
                     ignore
                     unknown
                     Tue Nov 20 02:36:01 GMT 2012
                     0x95BB138E
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_mask/implement/ise_implement.bat
                     ignore
                     unknown
                     Tue Nov 20 02:35:58 GMT 2012
                     0xEF02D4FF
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_mask/implement/ise_implement.sh
                     ignore
                     unknown
                     Tue Nov 20 02:36:01 GMT 2012
                     0x9A745C3F
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_mask/implement/pa_ise_implement.tcl
                     ignore
                     tcl
                     Tue Nov 20 02:35:59 GMT 2012
                     0xF047984E
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_mask/implement/rdi_implement.tcl
                     ignore
                     tcl
                     Tue Nov 20 02:36:00 GMT 2012
                     0x5B9127B8
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_mask/implement/v_rdi_implement.tcl
                     ignore
                     tcl
                     Tue Nov 20 02:36:00 GMT 2012
                     0x94CF2579
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_mask/read_me.txt
                     ignore
                     txt
                     Tue Nov 20 02:36:01 GMT 2012
                     0x4A2AE78B
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_mask.cdc
                     unknown
                     Tue Nov 20 02:36:39 GMT 2012
                     0xA96F5278
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_mask.constraints/chipscope_vio_mask.ucf
                     ucf
                     Tue Nov 20 02:36:39 GMT 2012
                     0x46D4F328
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_mask.constraints/chipscope_vio_mask.xdc
                     xdc
                     Tue Nov 20 02:36:39 GMT 2012
                     0xC2D11607
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_mask.ngc
                     ngc
                     Tue Nov 20 02:36:38 GMT 2012
                     0xE1997330
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_mask.ucf
                     ignore
                     ucf
                     Tue Nov 20 02:36:39 GMT 2012
                     0x46D4F328
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_mask.v
                     verilog
                     verilogSynthesis
                     Tue Nov 20 02:36:39 GMT 2012
                     0x78FBC74D
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_mask.veo
                     veo
                     Tue Nov 20 02:36:39 GMT 2012
                     0xAF798824
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_mask.xdc
                     ignore
                     xdc
                     Tue Nov 20 02:36:39 GMT 2012
                     0xC2D11607
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_mask_xmdf.tcl
                     tcl
                     Tue Nov 20 02:36:01 GMT 2012
                     0xBADC42BD
                     generationID_1879581046
                  
               
               
                  instantiation_template_generator
               
               
                  asy_generator
                  
                     ./chipscope_vio_mask.asy
                     asy
                     Tue Nov 20 02:36:40 GMT 2012
                     0xB7DFDEC6
                     generationID_1879581046
                  
               
               
                  xmdf_generator
               
               
                  ise_generator
                  
                     ./chipscope_vio_mask.gise
                     ignore
                     gise
                     Tue Nov 20 02:36:44 GMT 2012
                     0x81874387
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_mask.xise
                     ignore
                     xise
                     Tue Nov 20 02:36:44 GMT 2012
                     0xD0AB24F1
                     generationID_1879581046
                  
               
               
                  deliver_readme_generator
                  
                     ./chipscope_vio_mask_readme.txt
                     ignore
                     txtReadme
                     txt
                     Tue Nov 20 02:36:44 GMT 2012
                     0x736C765D
                     generationID_1879581046
                  
               
               
                  flist_generator
                  
                     ./chipscope_vio_mask_flist.txt
                     ignore
                     txtFlist
                     txt
                     Tue Nov 20 02:36:44 GMT 2012
                     0x1CC0385A
                     generationID_1879581046
                  
               
               
                  view_readme_generator
               
            
         
      
      
         chipscope_vio_trig
         
         
            chipscope_vio_trig
            8
            66
            false
            false
            external
            false
            8
            true
            8
            false
            true
            8
            1
            8
            0
            2
            66
            0
            8
            chipscope_vio_trig
            true
            Component_Name=chipscope_vio_trig;Enable_Synchronous_Input_Port=false;Enable_Synchronous_Output_Port=true;Enable_Asynchronous_Input_Port=false;Enable_Asynchronous_Output_Port=false;Synchronous_Input_Port_Width=8;Synchronous_Output_Port_Width=66;Asynchronous_Input_Port_Width=8;Asynchronous_Output_Port_Width=8;Invert_Clock_Input=false
            external
            0
            0
            1
         
         
            
               
                  coregen
                  ./
                  ./tmp/
                  ./tmp/_cg/
               
               
                  xc7z020
                  zynq
                  clg400
                  -2
               
               
                  BusFormatAngleBracketNotRipped
                  Verilog
                  true
                  Other
                  false
                  false
                  false
                  Ngc
                  false
               
               
                  Structural
                  Verilog
                  false
               
               
                  2012-07-21+03:12
               
            
            
               
                  customization_generator
               
               
                  model_parameter_resolution_generator
               
               
                  ip_xco_generator
                  
                     ./chipscope_vio_trig.xco
                     xco
                     Tue Nov 20 02:37:14 GMT 2012
                     0x1C211B73
                     generationID_3673615094
                  
               
               
                  ngc_netlist_generator
                  
                     ./chipscope_vio_trig/example_design/chipscope_vio_trig_bb_lib.v
                     ignore
                     verilogSynthesis
                     Tue Nov 20 02:37:15 GMT 2012
                     0x4FF83256
                     generationID_3673615094
                  
                  
                     ./chipscope_vio_trig/example_design/example_chipscope_vio_trig.ucf
                     ignore
                     ucf
                     Tue Nov 20 02:37:17 GMT 2012
                     0xB859E54F
                     generationID_3673615094
                  
                  
                     ./chipscope_vio_trig/example_design/example_chipscope_vio_trig.v
                     ignore
                     verilogSynthesis
                     Tue Nov 20 02:37:17 GMT 2012
                     0x604E80B9
                     generationID_3673615094
                  
                  
                     ./chipscope_vio_trig/example_design/example_chipscope_vio_trig.xdc
                     ignore
                     xdc
                     Tue Nov 20 02:37:17 GMT 2012
                     0x2338DEFF
                     generationID_3673615094
                  
                  
                     ./chipscope_vio_trig/implement/chipscope_icon.xco
                     ignore
                     xco
                     Tue Nov 20 02:37:15 GMT 2012
                     0x1FF80BFB
                     generationID_3673615094
                  
                  
                     ./chipscope_vio_trig/implement/coregen.cgp
                     ignore
                     unknown
                     Tue Nov 20 02:37:15 GMT 2012
                     0x940C30DF
                     generationID_3673615094
                  
                  
                     ./chipscope_vio_trig/implement/example_chipscope_vio_trig.prj
                     ignore
                     unknown
                     Tue Nov 20 02:37:16 GMT 2012
                     0x34375C50
                     generationID_3673615094
                  
                  
                     ./chipscope_vio_trig/implement/example_chipscope_vio_trig.xst
                     ignore
                     unknown
                     Tue Nov 20 02:37:18 GMT 2012
                     0x8A9B51FF
                     generationID_3673615094
                  
                  
                     ./chipscope_vio_trig/implement/ise_implement.bat
                     ignore
                     unknown
                     Tue Nov 20 02:37:15 GMT 2012
                     0xD215B1A8
                     generationID_3673615094
                  
                  
                     ./chipscope_vio_trig/implement/ise_implement.sh
                     ignore
                     unknown
                     Tue Nov 20 02:37:18 GMT 2012
                     0x2A4B1B2C
                     generationID_3673615094
                  
                  
                     ./chipscope_vio_trig/implement/pa_ise_implement.tcl
                     ignore
                     tcl
                     Tue Nov 20 02:37:16 GMT 2012
                     0x2C7947C8
                     generationID_3673615094
                  
                  
                     ./chipscope_vio_trig/implement/rdi_implement.tcl
                     ignore
                     tcl
                     Tue Nov 20 02:37:17 GMT 2012
                     0x3BC95413
                     generationID_3673615094
                  
                  
                     ./chipscope_vio_trig/implement/v_rdi_implement.tcl
                     ignore
                     tcl
                     Tue Nov 20 02:37:18 GMT 2012
                     0x7F500418
                     generationID_3673615094
                  
                  
                     ./chipscope_vio_trig/read_me.txt
                     ignore
                     txt
                     Tue Nov 20 02:37:18 GMT 2012
                     0x4A2AE78B
                     generationID_3673615094
                  
                  
                     ./chipscope_vio_trig.cdc
                     unknown
                     Tue Nov 20 02:37:58 GMT 2012
                     0x97DAF80B
                     generationID_3673615094
                  
                  
                     ./chipscope_vio_trig.constraints/chipscope_vio_trig.ucf
                     ucf
                     Tue Nov 20 02:37:58 GMT 2012
                     0x46D4F328
                     generationID_3673615094
                  
                  
                     ./chipscope_vio_trig.constraints/chipscope_vio_trig.xdc
                     xdc
                     Tue Nov 20 02:37:58 GMT 2012
                     0xC2D11607
                     generationID_3673615094
                  
                  
                     ./chipscope_vio_trig.ngc
                     ngc
                     Tue Nov 20 02:37:56 GMT 2012
                     0xE667CCD8
                     generationID_3673615094
                  
                  
                     ./chipscope_vio_trig.ucf
                     ignore
                     ucf
                     Tue Nov 20 02:37:58 GMT 2012
                     0x46D4F328
                     generationID_3673615094
                  
                  
                     ./chipscope_vio_trig.v
                     verilog
                     verilogSynthesis
                     Tue Nov 20 02:37:58 GMT 2012
                     0x22E2DC33
                     generationID_3673615094
                  
                  
                     ./chipscope_vio_trig.veo
                     veo
                     Tue Nov 20 02:37:58 GMT 2012
                     0x4BA52A8E
                     generationID_3673615094
                  
                  
                     ./chipscope_vio_trig.xdc
                     ignore
                     xdc
                     Tue Nov 20 02:37:58 GMT 2012
                     0xC2D11607
                     generationID_3673615094
                  
                  
                     ./chipscope_vio_trig_xmdf.tcl
                     tcl
                     Tue Nov 20 02:37:18 GMT 2012
                     0x0BB32865
                     generationID_3673615094
                  
               
               
                  instantiation_template_generator
               
               
                  asy_generator
                  
                     ./chipscope_vio_trig.asy
                     asy
                     Tue Nov 20 02:37:58 GMT 2012
                     0x7C5E1854
                     generationID_3673615094
                  
               
               
                  xmdf_generator
               
               
                  ise_generator
                  
                     ./chipscope_vio_trig.gise
                     ignore
                     gise
                     Tue Nov 20 02:38:02 GMT 2012
                     0xD388EB56
                     generationID_3673615094
                  
                  
                     ./chipscope_vio_trig.xise
                     ignore
                     xise
                     Tue Nov 20 02:38:02 GMT 2012
                     0x20B90E56
                     generationID_3673615094
                  
               
               
                  deliver_readme_generator
                  
                     ./chipscope_vio_trig_readme.txt
                     ignore
                     txtReadme
                     txt
                     Tue Nov 20 02:38:02 GMT 2012
                     0x7BAD3427
                     generationID_3673615094
                  
               
               
                  flist_generator
                  
                     ./chipscope_vio_trig_flist.txt
                     ignore
                     txtFlist
                     txt
                     Tue Nov 20 02:38:02 GMT 2012
                     0x4B4A8590
                     generationID_3673615094
                  
               
               
                  view_readme_generator
               
            
         
      
      
         scfifo
         
         
            scfifo
            Common_Clock_Block_RAM
            2
            2
            Native
            Standard_FIFO
            82
            1024
            82
            1024
            false
            false
            true
            true
            Asynchronous_Reset
            1
            true
            0
            false
            false
            false
            Active_High
            false
            Active_High
            false
            Active_High
            false
            Active_High
            false
            false
            false
            true
            10
            false
            10
            false
            10
            false
            1
            1
            No_Programmable_Full_Threshold
            1022
            1021
            No_Programmable_Empty_Threshold
            2
            3
            AXI4_Stream
            Common_Clock
            false
            Slave_Interface_Clock_Enable
            false
            false
            4
            32
            64
            false
            1
            false
            1
            false
            1
            false
            1
            false
            1
            false
            64
            false
            8
            false
            4
            false
            4
            true
            false
            false
            4
            false
            4
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            16
            false
            No_Programmable_Full_Threshold
            1023
            No_Programmable_Empty_Threshold
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            1024
            false
            No_Programmable_Full_Threshold
            1023
            No_Programmable_Empty_Threshold
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            16
            false
            No_Programmable_Full_Threshold
            1023
            No_Programmable_Empty_Threshold
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            16
            false
            No_Programmable_Full_Threshold
            1023
            No_Programmable_Empty_Threshold
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            1024
            false
            No_Programmable_Full_Threshold
            1023
            No_Programmable_Empty_Threshold
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            1024
            false
            No_Programmable_Full_Threshold
            1023
            No_Programmable_Empty_Threshold
            1022
            Fully_Registered
            Fully_Registered
            Fully_Registered
            Fully_Registered
            Fully_Registered
            Fully_Registered
            false
            Active_High
            false
            Active_High
            false
            false
            false
            false
            false
         
         
            
               
                  coregen
                  ./
                  ./tmp/
                  ./tmp/_cg/
               
               
                  xc7z020
                  zynq
                  clg400
                  -2
               
               
                  BusFormatAngleBracketNotRipped
                  Verilog
                  true
                  Other
                  false
                  false
                  false
                  Ngc
                  false
               
               
                  Behavioral
                  Verilog
                  false
               
               
                  2012-06-23+13:35
               
            
         
      
   
   
      
         
            coregen
            ./
            ./tmp/
            ./tmp/_cg/
         
         
            xc7z020
            zynq
            clg400
            -2
         
         
            BusFormatAngleBracketNotRipped
            Verilog
            true
            Other
            false
            false
            false
            Ngc
            false
         
         
            Behavioral
            Verilog
            false
         
      
   

 
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[/] [bustap-jtag/] [trunk/] [rtl/] [xilinx/] [coregen/] [coregen.cgc] - Blame information for rev 18

Line No.	Rev	Author	Line
1	18	ash_riple
2
3			`xilinx.com`
4			`project`
5			`coregen`
6			`1.0`
7
8
9			`chipscope_icon`
10
11
12			`chipscope_icon`
13			`false`
14			`3`
15			`true`
16			`external`
17			`false`
18			`false`
19			`USER1`
20			`false`
21
22
23
24
25			`coregen`
26			`./`
27			`./tmp/`
28			`./tmp/_cg/`
29
30
31			`xc7z020`
32			`zynq`
33			`clg400`
34			`-2`
35
36
37			`BusFormatAngleBracketNotRipped`
38			`Verilog`
39			`true`
40			`Other`