Subversion Repositories bustap-jtag

# Date: Mon Nov 19 08:26:59 2012

SET addpads = false

SET asysymbol = true

SET busformat = BusFormatAngleBracketNotRipped

SET createndf = false

SET designentry = Verilog

SET device = xc7z020

SET devicefamily = zynq

SET flowvendor = Other

SET formalverification = false

SET foundationsym = false

SET implementationfiletype = Ngc

SET package = clg400

SET removerpms = false

SET simulationfiles = Behavioral

SET speedgrade = -2

SET verilogsim = true

SET vhdlsim = false

SET workingdirectory = .\tmp\

# CRC:  7162d0b