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[/] [bustap-jtag/] [trunk/] [rtl/] [xilinx/] [pcores/] [bustap_jtag_v1_00_a/] [data/] [bustap_jtag_v2_1_0.pao] - Blame information for rev 18

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1 18 ash_riple
## -- DISCLAIMER OF LIABILITY
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## --
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## -- This file contains proprietary and confidential information of
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## -- Xilinx, Inc. ("Xilinx"), that is distributed under a license
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## -- from Xilinx, and may be used, copied and/or disclosed only
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## -- pursuant to the terms of a valid license agreement with Xilinx.
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## -- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
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## -- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
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## -- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
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## -- Materials will be uninterrupted or error-free, or that defects
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## -- in the Materials will be corrected. Furthermore, Xilinx does
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## -- results of the use, of the Materials in terms of correctness,
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## -- accuracy, reliability or otherwise.
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## --
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## -- Xilinx products are not designed or intended to be fail-safe,
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## -- or for use in any application requiring fail-safe performance,
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## -- such as life-support or safety devices or systems, Class III
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## -- lead to death, personal injury or severe property or
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## -- applications"). Customer assumes the sole risk and liability
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## -- of any use of Xilinx products in critical applications,
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## -- subject only to applicable laws and regulations governing
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## -- limitations on product liability.
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## --
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## -- Copyright 2009 Xilinx, Inc.
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## -- All rights reserved.
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## --
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## -- This disclaimer and copyright notice must be retained as part
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## -- of this file at all times.
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##
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###############################################################################
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##
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## bustap_jtag_v2_1_0.pao
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##
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## Peripheral Analyze Order File
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##
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##
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###############################################################################
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# Global `define
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vlgincdir bustap_jtag_v1_00_a .
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# Source files
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lib bustap_jtag_v1_00_a bustap_jtag.v verilog
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lib bustap_jtag_v1_00_a ../../../../../up_monitor.v verilog
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lib bustap_jtag_v1_00_a ../../../../../xilinx/chipscope_vio_adda_fifo.v verilog
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lib bustap_jtag_v1_00_a ../../../../../xilinx/chipscope_vio_adda_trig.v verilog
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lib bustap_jtag_v1_00_a ../../../../../xilinx/chipscope_vio_addr_mask.v verilog
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lib bustap_jtag_v1_00_a ../../../../../xilinx/coregen/scfifo.v verilog
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lib bustap_jtag_v1_00_a ../../../../../xilinx/coregen/chipscope_vio_fifo.v verilog
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lib bustap_jtag_v1_00_a ../../../../../xilinx/coregen/chipscope_vio_trig.v verilog
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lib bustap_jtag_v1_00_a ../../../../../xilinx/coregen/chipscope_vio_mask.v verilog
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