URL https://opencores.org/ocsvn/camellia/camellia/trunk

Subversion Repositories camellia

[/] [camellia/] [web_uploads/] [camellia_core_tb.vhd] - Blame information for rev 6

Details | Compare with Previous | View Log


-- Testbech for Camellia Algorithm Implementation
-- purpose : testbench file
-- file: camellia_core_tb.vhd
-- Ahmad Rifqi H (13200013)
-- 2004/Sept/20
 
 
LIBRARY work  ;
LIBRARY ieee  ;
USE IEEE.numeric_std.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE IEEE.std_logic_textio.ALL;
USE std.textio.ALL;
USE work.camellia_package.all  ;
USE ieee.std_logic_arith.all  ;
USE ieee.std_logic_1164.all  ;
ENTITY camellia_core_tb  IS
END ;
 
ARCHITECTURE camellia_core_tb_arch OF camellia_core_tb IS
  CONSTANT      CLK_PER         : time := 45 ns;
  FILE key_file  : text IS in
       "KAT_vectors/key.txt"; -- plaintext
  FILE plain_file  : text IS in
       "KAT_vectors/plaintext.txt"; -- plaintext
  FILE cipher_file : text IS in
       "KAT_vectors/ciphertext.txt"; -- input ciphertext
  FILE cipher_o_file : text IS out
       "KAT_vectors/out.txt"; -- output ciphertext
 
  SIGNAL out_ready   :  std_logic  ;
  SIGNAL proc   :  std_logic  ;
  SIGNAL input_ready   :  std_logic  ;
  SIGNAL clock   :  std_logic  := '0';
  SIGNAL input   :  std_logic_vector (0 to 127)  ;
  SIGNAL key_ready   :  std_logic  ;
  SIGNAL inv   :  std_logic  ;
  SIGNAL data_output   :  std_logic_vector (0 to 127)  ;
  SIGNAL reset   :  std_logic  ;
  COMPONENT camellia_core
    PORT (
      out_ready  : out std_logic ;
      proc  : in std_logic ;
      input_ready  : in std_logic ;
      clock  : in std_logic ;
      input  : in std_logic_vector (0 to 127) ;
      key_ready  : in std_logic ;
      inv  : in std_logic ;
      data_output  : out std_logic_vector (0 to 127) ;
      reset  : in std_logic );
  END COMPONENT ;
BEGIN
  DUT  : camellia_core
    PORT MAP (
      out_ready   => out_ready  ,
      proc   => proc  ,
      input_ready   => input_ready  ,
      clock   => clock  ,
      input   => input  ,
      key_ready   => key_ready  ,
      inv   => inv  ,
      data_output   => data_output  ,
      reset   => reset   ) ;
 
      PROCESS
           BEGIN
              WAIT for CLK_PER / 2;
                                clock <= NOT clock;
           END PROCESS;
 PROCESS
                VARIABLE tmp_data_in                    : std_logic_vector (0 to 127);
                VARIABLE tmp_key, tmp_cipher                    : std_logic_vector (0 to 127);
                VARIABLE L1,L3,L4                                         : line;
                --VARIABLE counter                                      : integer := 0;
                BEGIN
 
                reset <= '1';
                inv <= '0';
                key_ready <= '0';
                input_ready <= '0';
                proc <= '0';
                wait for 2*CLK_PER;
                reset <= '0';
                WAIT FOR CLK_PER;
 
                FOR i IN 0 TO 41 LOOP
                                IF NOT (ENDFILE(key_file)) THEN
                                        READLINE(key_file, L3);
                                        HREAD(L3, tmp_key);
                                ELSE
                                        tmp_key := (OTHERS => 'X');
                                END if;
 
                                IF NOT (ENDFILE(plain_file)) THEN
                                        READLINE(plain_file, L1);
                                        HREAD(L1, tmp_data_in);
                                ELSE
                                        tmp_data_in := (OTHERS => 'X');
                                END if;
 
                                IF NOT (ENDFILE(cipher_file)) THEN
                                        READLINE(cipher_file, L4);
                                        HREAD(L4, tmp_cipher);
                                ELSE
                                        tmp_cipher := (OTHERS => 'X');
                                END if;
 
                        reset <= '1';---------ENCRYPTION-------
                        inv <= '0';
                        WAIT FOR CLK_PER;
                        reset <= '0';
                        WAIT FOR CLK_PER;
                        input <= tmp_key;
                        key_ready <= '1';
                        WAIT FOR CLK_PER;
                        key_ready <= '0';
                        proc <= '1';
                        WAIT FOR 1*CLK_PER;
                        proc <= '0';
                        input <= tmp_data_in;
                        WAIT FOR 1*CLK_PER;
                        input_ready <= '1';
                        WAIT FOR 1*CLK_PER;
                        input_ready <= '0';
                        proc <= '1';
                        WAIT FOR CLK_PER;
                        proc <= '0';
                        wait for 5*CLK_PER;
 
                        reset <= '1';---------DECRYPTION-------
                        inv <= '1';
                        WAIT FOR CLK_PER;
                        reset <= '0';
                        WAIT FOR CLK_PER;
                        input <= tmp_key;
                        key_ready <= '1';
                        WAIT FOR CLK_PER;
                        key_ready <= '0';
                        proc <= '1';
                        WAIT FOR 1*CLK_PER;
                        proc <= '0';
                        input <= tmp_cipher;
                        WAIT FOR 1*CLK_PER;
                        input_ready <= '1';
                        WAIT FOR 1*CLK_PER;
                        input_ready <= '0';
                        proc <= '1';
                        WAIT FOR CLK_PER;
                        proc <= '0';
                        wait for 5*CLK_PER;
 
           END loop;
 
                reset <= '1';
                input <= (others => '0');
 
                WAIT;
        END PROCESS;
 
 
 
                PROCESS(clock)
                VARIABLE L2     : line;
                BEGIN
                        IF clock'EVENT AND clock = '1' THEN
                                IF out_ready = '1' THEN
                                        HWRITE(L2, data_output);
                                        WRITELINE(cipher_o_file, L2);
                                END if;
                        END if;
                END PROCESS;
 
END ;
 

Line No.	Rev	Author	Line
1	6	root	`-- Testbech for Camellia Algorithm Implementation`
2			`-- purpose : testbench file`
3			`-- file: camellia_core_tb.vhd`
4			`-- Ahmad Rifqi H (13200013)`
5			`-- 2004/Sept/20`
6
7
8			`LIBRARY work ;`
9			`LIBRARY ieee ;`
10			`USE IEEE.numeric_std.ALL;`
11			`USE IEEE.std_logic_unsigned.ALL;`
12			`USE IEEE.std_logic_textio.ALL;`
13			`USE std.textio.ALL;`
14			`USE work.camellia_package.all ;`
15			`USE ieee.std_logic_arith.all ;`
16			`USE ieee.std_logic_1164.all ;`
17			`ENTITY camellia_core_tb IS`
18			`END ;`
19
20			`ARCHITECTURE camellia_core_tb_arch OF camellia_core_tb IS`
21			`CONSTANT CLK_PER : time := 45 ns;`
22			`FILE key_file : text IS in`
23			`"KAT_vectors/key.txt"; -- plaintext`
24			`FILE plain_file : text IS in`
25			`"KAT_vectors/plaintext.txt"; -- plaintext`
26			`FILE cipher_file : text IS in`
27			`"KAT_vectors/ciphertext.txt"; -- input ciphertext`
28			`FILE cipher_o_file : text IS out`
29			`"KAT_vectors/out.txt"; -- output ciphertext`
30
31			`SIGNAL out_ready : std_logic ;`
32			`SIGNAL proc : std_logic ;`
33			`SIGNAL input_ready : std_logic ;`
34			`SIGNAL clock : std_logic := '0';`
35			`SIGNAL input : std_logic_vector (0 to 127) ;`
36			`SIGNAL key_ready : std_logic ;`
37			`SIGNAL inv : std_logic ;`
38			`SIGNAL data_output : std_logic_vector (0 to 127) ;`
39			`SIGNAL reset : std_logic ;`
40			`COMPONENT camellia_core`
41			`PORT (`
42			`out_ready : out std_logic ;`
43			`proc : in std_logic ;`
44			`input_ready : in std_logic ;`
45			`clock : in std_logic ;`
46			`input : in std_logic_vector (0 to 127) ;`
47			`key_ready : in std_logic ;`
48			`inv : in std_logic ;`
49			`data_output : out std_logic_vector (0 to 127) ;`
50			`reset : in std_logic );`
51			`END COMPONENT ;`
52			`BEGIN`
53			`DUT : camellia_core`
54			`PORT MAP (`
55			`out_ready => out_ready ,`
56			`proc => proc ,`
57			`input_ready => input_ready ,`
58			`clock => clock ,`
59			`input => input ,`
60			`key_ready => key_ready ,`
61			`inv => inv ,`
62			`data_output => data_output ,`
63			`reset => reset ) ;`
64
65			`PROCESS`
66			`BEGIN`
67			`WAIT for CLK_PER / 2;`
68			`clock <= NOT clock;`
69			`END PROCESS;`
70			`PROCESS`
71			`VARIABLE tmp_data_in : std_logic_vector (0 to 127);`
72			`VARIABLE tmp_key, tmp_cipher : std_logic_vector (0 to 127);`
73			`VARIABLE L1,L3,L4 : line;`
74			`--VARIABLE counter : integer := 0;`
75			`BEGIN`
76
77			`reset <= '1';`
78			`inv <= '0';`
79			`key_ready <= '0';`
80			`input_ready <= '0';`
81			`proc <= '0';`
82			`wait for 2*CLK_PER;`
83			`reset <= '0';`
84			`WAIT FOR CLK_PER;`
85
86			`FOR i IN 0 TO 41 LOOP`
87			`IF NOT (ENDFILE(key_file)) THEN`
88			`READLINE(key_file, L3);`
89			`HREAD(L3, tmp_key);`
90			`ELSE`
91			`tmp_key := (OTHERS => 'X');`
92			`END if;`
93
94			`IF NOT (ENDFILE(plain_file)) THEN`
95			`READLINE(plain_file, L1);`
96			`HREAD(L1, tmp_data_in);`
97			`ELSE`
98			`tmp_data_in := (OTHERS => 'X');`
99			`END if;`
100
101			`IF NOT (ENDFILE(cipher_file)) THEN`
102			`READLINE(cipher_file, L4);`
103			`HREAD(L4, tmp_cipher);`
104			`ELSE`
105			`tmp_cipher := (OTHERS => 'X');`
106			`END if;`
107
108			`reset <= '1';---------ENCRYPTION-------`
109			`inv <= '0';`
110			`WAIT FOR CLK_PER;`
111			`reset <= '0';`
112			`WAIT FOR CLK_PER;`
113			`input <= tmp_key;`
114			`key_ready <= '1';`
115			`WAIT FOR CLK_PER;`
116			`key_ready <= '0';`
117			`proc <= '1';`
118			`WAIT FOR 1*CLK_PER;`
119			`proc <= '0';`
120			`input <= tmp_data_in;`
121			`WAIT FOR 1*CLK_PER;`
122			`input_ready <= '1';`
123			`WAIT FOR 1*CLK_PER;`
124			`input_ready <= '0';`
125			`proc <= '1';`
126			`WAIT FOR CLK_PER;`
127			`proc <= '0';`
128			`wait for 5*CLK_PER;`
129
130			`reset <= '1';---------DECRYPTION-------`
131			`inv <= '1';`
132			`WAIT FOR CLK_PER;`
133			`reset <= '0';`
134			`WAIT FOR CLK_PER;`
135			`input <= tmp_key;`
136			`key_ready <= '1';`
137			`WAIT FOR CLK_PER;`
138			`key_ready <= '0';`
139			`proc <= '1';`
140			`WAIT FOR 1*CLK_PER;`
141			`proc <= '0';`
142			`input <= tmp_cipher;`
143			`WAIT FOR 1*CLK_PER;`
144			`input_ready <= '1';`
145			`WAIT FOR 1*CLK_PER;`
146			`input_ready <= '0';`
147			`proc <= '1';`
148			`WAIT FOR CLK_PER;`
149			`proc <= '0';`
150			`wait for 5*CLK_PER;`
151
152			`END loop;`
153
154			`reset <= '1';`
155			`input <= (others => '0');`
156
157			`WAIT;`
158			`END PROCESS;`
159
160
161
162			`PROCESS(clock)`
163			`VARIABLE L2 : line;`
164			`BEGIN`
165			`IF clock'EVENT AND clock = '1' THEN`
166			`IF out_ready = '1' THEN`
167			`HWRITE(L2, data_output);`
168			`WRITELINE(cipher_o_file, L2);`
169			`END if;`
170			`END if;`
171			`END PROCESS;`
172
173			`END ;`
174

Browse

Tools

Subversion Repositories camellia

[/] [camellia/] [web_uploads/] [camellia_core_tb.vhd] - Blame information for rev 6