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[/] [cde/] [trunk/] [ip/] [pad/] [rtl/] [verilog/] [pad_in_dig.v] - Blame information for rev 2
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jt_eaton |
/**********************************************************************/
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/* */
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/* */
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/* Copyright (c) 2012 Ouabache Design Works */
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/* */
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/* All Rights Reserved Worldwide */
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/* */
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/* Licensed under the Apache License,Version2.0 (the'License'); */
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/* you may not use this file except in compliance with the License. */
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/* You may obtain a copy of the License at */
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/* */
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/* http://www.apache.org/licenses/LICENSE-2.0 */
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/* */
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/* Unless required by applicable law or agreed to in */
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/* writing, software distributed under the License is */
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/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */
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/* OR CONDITIONS OF ANY KIND, either express or implied. */
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/* See the License for the specific language governing */
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/* permissions and limitations under the License. */
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/**********************************************************************/
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module
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cde_pad_in_dig
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#(parameter WIDTH=1)
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(
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input wire [WIDTH-1:0] PAD,
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output wire [WIDTH-1:0] pad_in
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);
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assign pad_in = PAD;
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endmodule
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