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[/] [cde/] [trunk/] [ip/] [pad/] [rtl/] [xml/] [cde_pad_in_dig.xml] - Blame information for rev 2

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
pad
in_dig
 
 
 
 

 
 pad_ring
  
  
  
    
      
        PAD_in
        PAD
        
      
 
    
 
 
 
 
 pad
  
  
  
    
      
        pad_in
        pad_in
        
      
 
    
 
 
 
 
 
 

 
 
 
 
 

       
 
 
 
              
              sim*simulation*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn*synthesis*
              Verilog
              
                     
                            fs-syn
                     
              
 
             
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              *documentation*
              Verilog
              
 
 
      
 

WIDTH1

 
 
 

 
PAD
wire
in
WIDTH-10

 
pad_in
wire
out
WIDTH-10

 
 
 
 
 
 
 
 

 

 
 
 
 
 

 
   
      fs-sim
 
       
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
 
    
 
      fs-lint
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
    
 
 
 
 

 
 
 
 
 
 
 
 
 


Line No.	Rev	Author	Line
1	2	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`pad`
15			`in_dig`
16
17
18
19
20
21
22			`pad_ring`
23
24
25
26
27
28			`PAD_in`
29			`PAD`
30
31
32
33
34
35
36
37
38			`pad`
39
40
41
42
43
44			`pad_in`
45			`pad_in`
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68			`simsimulation`
69			`Verilog`
70
71
72			`fs-sim`
73
74
75
76
77			`synsynthesis`
78			`Verilog`
79
80
81			`fs-syn`
82
83
84
85
86			`doc`
87
88
89			`spirit:library="Testbench"`
90			`spirit:name="toolflow"`
91			`spirit:version="documentation"/>`
92
93			`documentation`
94			`Verilog`
95
96
97
98
99
100
101			`WIDTH1`
102
103
104
105
106
107
108			`PAD`
109			`wire`
110			`in`
111			`WIDTH-10`
112
113
114			`pad_in`
115			`wire`
116			`out`
117			`WIDTH-10`
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138			`fs-sim`
139
140
141			`dest_dir`
142			`../verilog/`
143			`verilogSourcelibraryDir`
144
145
146
147
148
149
150			`fs-syn`
151
152			`dest_dir`
153			`../verilog/`
154			`verilogSourcelibraryDir`
155
156
157
158
159
160
161
162
163
164
165			`fs-lint`
166
167			`dest_dir`
168			`../verilog/`
169			`verilogSourcelibraryDir`
170
171
172
173
174
175
176
177
178
179
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[/] [cde/] [trunk/] [ip/] [pad/] [rtl/] [xml/] [cde_pad_in_dig.xml] - Blame information for rev 2