OpenCores
URL https://opencores.org/ocsvn/cde/cde/trunk

Subversion Repositories cde

[/] [cde/] [trunk/] [ip/] [pad/] [rtl/] [xml/] [cde_pad_od_dig.xml] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 jt_eaton
2
5
6
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
7
xmlns:socgen="http://opencores.org"
8
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
9
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
10
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
11
 
12
opencores.org
13
cde
14
pad
15
od_dig
16
 
17
 
18
 
19
 
20
 
21
 
22
23
 
24
 pad_ring
25
  
26
  
27
  
28
    
29
      
30
        PAD_io
31
        PAD
32
      
33
 
34
    
35
 
36
 
37
 
38
 
39
 pad
40
  
41
  
42
  
43
    
44
      
45
        pad_oe
46
        pad_oe
47
      
48
      
49
        pad_in
50
        pad_in
51
      
52
 
53
    
54
 
55
 
56
 
57
 
58
 
59
 
60
61
 
62
 
63
 
64
 
65
 
66
 
67
 
68
69
       
70
 
71
 
72
 
73
              
74
              sim*simulation*
75
              Verilog
76
              
77
                     
78
                            fs-sim
79
                     
80
              
81
 
82
              
83
              syn*synthesis*
84
              Verilog
85
              
86
                     
87
                            fs-syn
88
                     
89
              
90
 
91
 
92
 
93
             
94
              doc
95
              
96
              
97
                                   spirit:library="Testbench"
98
                                   spirit:name="toolflow"
99
                                   spirit:version="documentation"/>
100
              
101
              *documentation*
102
              Verilog
103
              
104
 
105
 
106
      
107
 
108
 
109
 
110
 
111
112
 
113
PAD
114
wire
115
inout
116
117
 
118
pad_in
119
wire
120
out
121
122
 
123
pad_oe
124
wire
125
in
126
127
 
128
 
129
130
 
131
132
 
133
 
134
 
135
 
136
137
 
138
   
139
      fs-sim
140
 
141
 
142
      
143
        dest_dir
144
        ../verilog/
145
        verilogSourcelibraryDir
146
      
147
 
148
  
149
 
150
 
151
   
152
      fs-syn
153
 
154
      
155
        dest_dir
156
        ../verilog/syn/
157
        verilogSourcelibraryDir
158
      
159
 
160
 
161
 
162
   
163
 
164
 
165
    
166
 
167
      fs-lint
168
      
169
        dest_dir
170
        ../verilog/syn/
171
        verilogSourcelibraryDir
172
      
173
 
174
    
175
 
176
 
177
 
178
 
179
 
180
 
181
182
 
183
 
184
 
185
 
186
 
187
 
188
 
189
 
190

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.