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[/] [cde/] [trunk/] [ip/] [pad/] [rtl/] [xml/] [cde_pad_out_dig.xml] - Blame information for rev 2

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
pad
out_dig
 
 
 
 
 

 
 pad_ring
  
  
  
    
      
        PAD_out
        PAD
        
      
 
    
 
 
 
 
 pad
  
  
  
    
      
        pad_out
        pad_out
      
      
    
 
 
 
 
 
 

 
 
 
 
 

       
 
 
              
              sim*simulation*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn*synthesis*
              Verilog
              
                     
                            fs-syn
                     
              
 
                
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              *documentation*
              Verilog
              
 
 
 
      
 
 

WIDTH1

 
 

 
PAD
wire
out
WIDTH-10

 
pad_out
wire
in
WIDTH-10

 

 

 
 
 
 
 
 
 

 
   
      fs-sim
 
 
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 

 
 
 
 
 
 
 


Line No.	Rev	Author	Line
1	2	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`pad`
15			`out_dig`
16
17
18
19
20
21
22
23			`pad_ring`
24
25
26
27
28
29			`PAD_out`
30			`PAD`
31
32
33
34
35
36
37
38
39			`pad`
40
41
42
43
44
45			`pad_out`
46			`pad_out`
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67			`simsimulation`
68			`Verilog`
69
70
71			`fs-sim`
72
73
74
75
76			`synsynthesis`
77			`Verilog`
78
79
80			`fs-syn`
81
82
83
84
85			`doc`
86
87
88			`spirit:library="Testbench"`
89			`spirit:name="toolflow"`
90			`spirit:version="documentation"/>`
91
92			`documentation`
93			`Verilog`
94
95
96
97
98
99
100
101
102			`WIDTH1`
103
104
105
106
107
108			`PAD`
109			`wire`
110			`out`
111			`WIDTH-10`
112
113
114			`pad_out`
115			`wire`
116			`in`
117			`WIDTH-10`
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133			`fs-sim`
134
135
136
137			`dest_dir`
138			`../verilog/`
139			`verilogSourcelibraryDir`
140
141
142
143
144
145
146			`fs-syn`
147
148
149			`dest_dir`
150			`../verilog/`
151			`verilogSourcelibraryDir`
152
153
154
155
156
157
158
159
160
161			`fs-lint`
162
163			`dest_dir`
164			`../verilog/`
165			`verilogSourcelibraryDir`
166
167
168
169
170
171
172
173
174
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[/] [cde/] [trunk/] [ip/] [pad/] [rtl/] [xml/] [cde_pad_out_dig.xml] - Blame information for rev 2