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[/] [cde/] [trunk/] [ip/] [sram/] [rtl/] [verilog/] [lint/] [sram_be.v] - Blame information for rev 2

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 module
  cde_sram_be
    #( parameter
      ADDR=10,
      WIDTH=8,
      WORDS=1024,
      WRITETHRU=0,
      DEFAULT={WIDTH{1'b1}},
      INIT_FILE="NONE",
      INSTANCE_NAME="U1")
     (
 input   wire                 be,
 input   wire                 clk,
 input   wire                 cs,
 input   wire                 rd,
 input   wire                 wr,
 input   wire    [ ADDR-1 :  0]        addr,
 input   wire    [ WIDTH-1 :  0]        wdata,
 output   reg    [ WIDTH-1 :  0]        rdata);
  // Simple loop back for linting and code coverage
  always@(posedge clk)
        if( rd && cs ) rdata             <= wdata;
        else           rdata             <= DEFAULT;
  endmodule

Line No.	Rev	Author	Line
1	2	jt_eaton	`module`
2			`cde_sram_be`
3			`#( parameter`
4			`ADDR=10,`
5			`WIDTH=8,`
6			`WORDS=1024,`
7			`WRITETHRU=0,`
8			`DEFAULT={WIDTH{1'b1}},`
9			`INIT_FILE="NONE",`
10			`INSTANCE_NAME="U1")`
11			`(`
12			`input wire be,`
13			`input wire clk,`
14			`input wire cs,`
15			`input wire rd,`
16			`input wire wr,`
17			`input wire [ ADDR-1 : 0] addr,`
18			`input wire [ WIDTH-1 : 0] wdata,`
19			`output reg [ WIDTH-1 : 0] rdata);`
20			`// Simple loop back for linting and code coverage`
21			`always@(posedge clk)`
22			`if( rd && cs ) rdata <= wdata;`
23			`else rdata <= DEFAULT;`
24			`endmodule`

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[/] [cde/] [trunk/] [ip/] [sram/] [rtl/] [verilog/] [lint/] [sram_be.v] - Blame information for rev 2