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[/] [cde/] [trunk/] [ip/] [sram/] [rtl/] [xml/] [sram_def.xml] - Blame information for rev 2

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
sram
def
 
 
 
 
 
 

       
 
              
              sim*simulation*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn*synthesis*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              lintlint
              Verilog
              
                     
                            fs-lint
                     
              
 
 
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              *documentation*
              Verilog
              
 
 
 
 
      
 
 
 

ADDR0
WIDTH0
WORDS0
WRITETHRU0
DEFAULT{WIDTH{1'bx}}
INIT_FILE"NONE"
INSTANCE_NAME"U1"

 

 
clk
wire
in

 
cs
wire
in

 
wr
wire
in

 
rd
wire
in

 
 
addr
wire
in
ADDR-10

 
 
wdata
wire
in
WIDTH-10

 
rdata
reg
out
WIDTH-10

 
 
 

 

 
 
 
 
 
 
 

 
 
 
 
   
      fs-sim
 
 
 
       
        dest_dir../verilog/
        verilogSourcelibraryDir
      
 
 
 
  
 
 
   
      fs-syn
 
 
 
       
        dest_dir../verilog/
        verilogSourcelibraryDir
      
 
 
 
 
   
 
 
 
   
      fs-lint
 
 
       
        dest_dir../verilog/lint/
        verilogSourcelibraryDir
      
 
 
 
 
   
 
 
 
 
 

 
 
 
 
 
 
 
 
 


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[/] [cde/] [trunk/] [ip/] [sram/] [rtl/] [xml/] [sram_def.xml] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`sram`
15			`def`
16
17
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23
24
25
26			`simsimulation`
27			`Verilog`
28
29
30			`fs-sim`
31
32
33
34
35			`synsynthesis`
36			`Verilog`
37
38
39			`fs-syn`
40
41
42
43
44
45			`lintlint`
46			`Verilog`
47
48
49			`fs-lint`
50
51
52
53
54
55
56
57
58			`doc`
59
60
61			`spirit:library="Testbench"`
62			`spirit:name="toolflow"`
63			`spirit:version="documentation"/>`
64
65			`documentation`
66			`Verilog`
67
68
69
70
71
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73
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75
76
77			`ADDR0`
78			`WIDTH0`
79			`WORDS0`
80			`WRITETHRU0`
81			`DEFAULT{WIDTH{1'bx}}`
82			`INIT_FILE"NONE"`
83			`INSTANCE_NAME"U1"`
84
85
86
87
88			`clk`
89			`wire`
90			`in`
91
92
93			`cs`
94			`wire`
95			`in`
96
97
98			`wr`
99			`wire`
100			`in`
101
102
103			`rd`
104			`wire`
105			`in`
106
107
108
109			`addr`
110			`wire`
111			`in`
112			`ADDR-10`
113
114
115
116			`wdata`
117			`wire`
118			`in`
119			`WIDTH-10`
120
121
122			`rdata`
123			`reg`
124			`out`
125			`WIDTH-10`
126
127
128
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137
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143
144
145
146			`fs-sim`
147
148
149
150
151			`dest_dir../verilog/`
152			`verilogSourcelibraryDir`
153
154
155
156
157
158
159
160
161			`fs-syn`
162
163
164
165
166			`dest_dir../verilog/`
167			`verilogSourcelibraryDir`
168
169
170
171
172
173
174
175
176
177
178			`fs-lint`
179
180
181
182			`dest_dir../verilog/lint/`
183			`verilogSourcelibraryDir`
184
185
186
187
188
189
190
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