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[/] [cde/] [trunk/] [ip/] [sram/] [rtl/] [xml/] [sram_dp.xml] - Blame information for rev 2

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
sram
dp
 
 
 
 
 
 
 
 

       
 
 
              
              sim*simulation*
              Verilog
                     
                            fs-sim
                     
              
 
              
              syn*synthesis*
              Verilog
                     
                            fs-syn
                     
              
 
              
              lintlint
              Verilog
                     
                            fs-lint
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              *documentation*
              Verilog
              
 
 
 
 
 
 
      
 
 
 

 
ADDR0
WIDTH0
WORDS0
WRITETHRU0
DEFAULT{WIDTH{1'bx}}
INIT_FILE"NONE"
INSTANCE_NAME"U1"

 
 
 

 
clk
wire
in

 
cs
wire
in

 
wr
wire
in

 
rd
wire
in

 
 
waddr
wire
in
ADDR-10

 
raddr
wire
in
ADDR-10

 
 
wdata
wire
in
WIDTH-10

 
rdata
reg
out
WIDTH-10

 
 
 

 

 
 
 
 
 
 

 
 
 
   
      fs-sim
 
       
        dest_dir../verilog/
        verilogSourcelibraryDir
      
 
 
 
  
 
 
   
      fs-syn
 
 
       
        dest_dir../verilog/
        verilogSourcelibraryDir
      
 
 
   
 
 
 
 
 
   
      fs-lint
 
 
 
       
        dest_dir../verilog/lint/
        verilogSourcelibraryDir
      
 
 
   
 
 
 
 
 
 
 
 
 

 
 
 
 
 
 
 
 
 


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[/] [cde/] [trunk/] [ip/] [sram/] [rtl/] [xml/] [sram_dp.xml] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`sram`
15			`dp`
16
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26
27
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29			`simsimulation`
30			`Verilog`
31
32			`fs-sim`
33
34
35
36
37			`synsynthesis`
38			`Verilog`
39
40			`fs-syn`
41
42
43
44
45			`lintlint`
46			`Verilog`
47
48			`fs-lint`
49
50
51
52
53
54			`doc`
55
56
57			`spirit:library="Testbench"`
58			`spirit:name="toolflow"`
59			`spirit:version="documentation"/>`
60
61			`documentation`
62			`Verilog`
63
64
65
66
67
68
69
70
71
72
73
74
75
76			`ADDR0`
77			`WIDTH0`
78			`WORDS0`
79			`WRITETHRU0`
80			`DEFAULT{WIDTH{1'bx}}`
81			`INIT_FILE"NONE"`
82			`INSTANCE_NAME"U1"`
83
84
85
86
87
88
89			`clk`
90			`wire`
91			`in`
92
93
94			`cs`
95			`wire`
96			`in`
97
98
99			`wr`
100			`wire`
101			`in`
102
103
104			`rd`
105			`wire`
106			`in`
107
108
109
110			`waddr`
111			`wire`
112			`in`
113			`ADDR-10`
114
115
116			`raddr`
117			`wire`
118			`in`
119			`ADDR-10`
120
121
122
123			`wdata`
124			`wire`
125			`in`
126			`WIDTH-10`
127
128
129			`rdata`
130			`reg`
131			`out`
132			`WIDTH-10`
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151			`fs-sim`
152
153
154			`dest_dir../verilog/`
155			`verilogSourcelibraryDir`
156
157
158
159
160
161
162
163
164			`fs-syn`
165
166
167
168			`dest_dir../verilog/`
169			`verilogSourcelibraryDir`
170
171
172
173
174
175
176
177
178
179
180			`fs-lint`
181
182
183
184
185			`dest_dir../verilog/lint/`
186			`verilogSourcelibraryDir`
187
188
189
190
191
192
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195
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