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[/] [complex-gaussian-pseudo-random-number-generator/] [trunk/] [urng/] [MT_GET.vhd] - Blame information for rev 2

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--/////////////////////////MT_GET BLOCK///////////////////////////////
--Purpose: to produce functionality equivalent to following C code:
--         
--
--Created by: Minzhen Ren
--Last Modified by: Minzhen Ren
--Last Modified Date: Auguest 30, 2010
--Lately Updates: 
--/////////////////////////////////////////////////////////////////
library ieee;
        use ieee.std_logic_1164.all;
        use ieee.std_logic_unsigned.all;
        use ieee.numeric_std.all;
        use ieee.math_real.all;
 
entity MT_GET is
        generic(
                DATA_WIDTH : Natural := 32
        );
        port(
                signal CLK              : in  std_logic;
                signal RESET            : in  std_logic;
                signal SEED_IN          : in  std_logic_vector( DATA_WIDTH-1 downto 0 );
                signal PAUSE            : in  std_logic;
                signal DONE_INIT        : out std_logic;
                signal OUT_SIG          : out std_logic;
                signal OUTPUT           : out std_logic_vector( DATA_WIDTH-1 downto 0 )
        );
end MT_GET;
 
architecture BEHAVE of MT_GET is
        --contant
        signal M_CONST : std_logic_vector( 9 downto 0 );
        signal N_CONST : std_logic_vector( 9 downto 0 );
        signal MN_DIFF : std_logic_vector( 9 downto 0 );
        signal M_MINUS : std_logic_vector( 9 downto 0 );
        signal N_MINUS : std_logic_vector( 9 downto 0 );
 
        --MT_SET interface
        signal SEED : std_logic_vector( DATA_WIDTH-1 downto 0 );
        signal WRITE_DATA : std_logic_vector( DATA_WIDTH-1 downto 0 );
        signal IDLE_SIG : std_logic;
 
        --Memory interface
        signal ADDR_MAX   : std_logic_vector( 8 downto 0 );
        signal WR_ENABLE0 : std_logic;
        signal WR_ADDR0   : std_logic_vector( 8 downto 0 );
        signal WR_ADDR0_Q       : std_logic_vector( 8 downto 0 );
        signal WR_ADDR0_QQ      : std_logic_vector( 8 downto 0 );
        signal WR_ADDR0_QQQ : std_logic_vector( 8 downto 0 );
        signal WR_ADDR0_QQQQ : std_logic_vector( 8 downto 0 );
        signal RD_ENABLE0 : std_logic;
        signal RD_ADDR0   : std_logic_vector( 8 downto 0 );
        signal MEM0_IN    : std_logic_vector( DATA_WIDTH-1 downto 0 );
        signal MEM0_OUT   : std_logic_vector( DATA_WIDTH-1 downto 0 );
        signal WR_ENABLE1 : std_logic;
        signal WR_ADDR1   : std_logic_vector( 8 downto 0 );
        signal RD_ENABLE1 : std_logic;
        signal RD_ADDR1   : std_logic_vector( 8 downto 0 );
        signal MEM1_IN    : std_logic_vector( DATA_WIDTH-1 downto 0 );
        signal MEM1_OUT   : std_logic_vector( DATA_WIDTH-1 downto 0 );
        signal DATA_MT_GEN : std_logic_vector( DATA_WIDTH-1 downto 0 );
        signal ADDR_SHF_IN  : std_logic_vector( 9 downto 0 );
        signal ADDR_SHF_OUT : std_logic_vector( 9 downto 0 );
        signal OPRAND1 : std_logic_vector( DATA_WIDTH-1 downto 0 );
        signal OPRAND2 : std_logic_vector( DATA_WIDTH-1 downto 0 );
        signal OPRAND3 : std_logic_vector( DATA_WIDTH-1 downto 0 );
 
        --Counter
        signal KK : std_logic_vector( 9 downto 0 );
        signal INNER_STATE : std_logic_vector( 2 downto 0 );
        signal KK_MAX : std_logic_vector( 9 downto 0 );
 
        --Control signal
        signal MEM_SEL : std_logic;
 
        --State Machine
        type STATE_TYPE is (INITIAL, MEM_INIT, MT_GEN, PAUSE_STATE);
        signal CS : STATE_TYPE;
        signal NS : STATE_TYPE;
 
        component MT_SET is
                generic(
                        DATA_WIDTH : Natural := 32
                );
                port(
                        signal CLK   : in  std_logic;
                        signal RESET : in  std_logic;
                        signal IDLE_SIG : in std_logic;
                        signal S_IN  : in  std_logic_vector( DATA_WIDTH-1 downto 0 );
                        signal S_OUT : out std_logic_vector( DATA_WIDTH-1 downto 0 )
                );
        end component;
 
        component dp_mem is
                generic (
                  Addr_Wdth : Natural := 9;
                  Bit_Wdth  : Natural := 32
                );
            port (Clock         : in  Std_Logic;
                          Write_Enable  : in  Std_Logic;
                          Write_Address : in  Std_Logic_Vector(Addr_Wdth-1 downto 0);
                          Read_Enable   : in  Std_Logic;
                          Read_Address  : in  Std_Logic_Vector(Addr_Wdth-1 downto 0);
                          Data_In       : in  Std_Logic_Vector(Bit_Wdth-1 downto 0);
                          Data_Out      : out Std_Logic_Vector(Bit_Wdth-1 downto 0));
        end component;
 
        component MT_PATH is
                generic(
                        DATA_WIDTH : Natural := 32
                );
                port(
                        signal OPRAND1 : in  std_logic_vector( DATA_WIDTH-1 downto 0 );
                        signal OPRAND2 : in  std_logic_vector( DATA_WIDTH-1 downto 0 );
                        signal OPRAND3 : in  std_logic_vector( DATA_WIDTH-1 downto 0 );
                        signal CLK     : in  std_logic;
                        signal RESET   : in  std_logic;
                        signal OUTPUT  : out std_logic_vector( DATA_WIDTH-1 downto 0 )
                );
        end component;
 
        component MT_SHIFTING is
                generic(
                        DATA_WIDTH : Natural := 32
                );
                port(
                        signal INPUT  : in  std_logic_vector( DATA_WIDTH-1 downto 0 );
                        signal OUTPUT : out std_logic_vector( DATA_WIDTH-1 downto 0 )
                );
        end component;
 
        begin
 
        MT_BLK : MT_SET
        port map(
                S_IN    => SEED,
                S_OUT   => WRITE_DATA,
                CLK     => CLK,
                RESET   => RESET,
                IDLE_SIG => IDLE_SIG
        );
 
        MEM0 : dp_mem
        port map(
                Clock                   => CLK,
                Write_Enable    => WR_ENABLE0,
                Write_Address   => WR_ADDR0,
                Read_Enable     => RD_ENABLE0,
                Read_Address    => RD_ADDR0,
                Data_In                 => MEM0_IN,
                Data_Out                => MEM0_OUT
        );
 
        MEM1 : dp_mem
        port map(
                Clock                   => CLK,
                Write_Enable    => WR_ENABLE1,
                Write_Address   => WR_ADDR1,
                Read_Enable     => RD_ENABLE1,
                Read_Address    => RD_ADDR1,
                Data_In                 => MEM1_IN,
                Data_Out                => MEM1_OUT
        );
 
        CURRENT_STATE : process(CLK, RESET)
        begin
                if RESET = '1' then
                        CS <= INITIAL;
                elsif CLK='1' and CLK'event then
                        CS <= NS;
                end if;
        end process;
 
        NEXT_STATE : process(CS, KK, N_MINUS, INNER_STATE, PAUSE)
        begin
                if CS = INITIAL then
                        NS <= MEM_INIT;
                elsif CS = MEM_INIT then
                        if KK = N_MINUS and INNER_STATE(2) = '1' then
                                NS <= MT_GEN;
                        else
                                NS <= CS;
                        end if;
                elsif CS <= MT_GEN then
                        if PAUSE = '1' then
                                NS <= PAUSE_STATE;
                        else
                                NS <= MT_GEN;
                        end if;
                elsif CS <= PAUSE_STATE then
                        if PAUSE = '0' then
                                NS <= MT_GEN;
                        else
                                NS <= PAUSE_STATE;
                        end if;
                else
                        NS <= INITIAL;
                end if;
        end process;
 
        COUNTER_PROC : process(CLK, RESET)
        begin
                if RESET = '1' then
                        KK <= (others => '0');
                elsif CLK'event and CLK='1' then
                        if CS = INITIAL then
                                KK <= (others => '0');
                        elsif CS = MEM_INIT then
                                if INNER_STATE(2) = '1' and KK /= N_MINUS then
                                        KK <= KK + 1;
                                elsif INNER_STATE(2) = '1' and KK = N_MINUS then
                                        KK <= (others => '0');
                                else
                                        KK <= KK;
                                end if;
                        elsif CS = MT_GEN then
                                if INNER_STATE = "011" and KK /= N_MINUS then
                                        KK <= KK + 1;
                                elsif INNER_STATE = "011" and KK = N_MINUS then
                                        KK <= (others => '0');
                                end if;
                        elsif CS = PAUSE_STATE then
                                KK <= KK;
                        else
                                KK <= (others => '0');
                        end if;
                end if;
        end process;
 
        INNER_STATE_COUNTER : process(CLK, RESET)
        begin
                if RESET = '1' then
                        INNER_STATE <= (others => '0');
                elsif CLK'event and CLK='1' then
                        if CS = INITIAL then
                                INNER_STATE <= (others => '0');
                        elsif CS = MEM_INIT then
                                if INNER_STATE(2) = '0' then
                                        INNER_STATE <= INNER_STATE + '1';
                                else
                                        INNER_STATE <= "001";
                                end if;
                        elsif CS = MT_GEN then
                                if INNER_STATE < "011" then
                                        INNER_STATE <= INNER_STATE + '1';
                                else
                                        INNER_STATE <= "001";
                                end if;
                        elsif CS = PAUSE_STATE then
                                INNER_STATE <= "001";
                        else
                                INNER_STATE <= (others => '0');
                        end if;
                end if;
        end process;
 
        IDLE_SIG <= '0' when CS = MEM_INIT and RESET = '0' else '1';
 
        --constants
        N_CONST <= "1001110000"; --624
        M_CONST <= "0110001101"; --397
        MN_DIFF <= "0011100011"; --227
        N_MINUS <= "1001101111"; --623
        M_MINUS <= "0110001100"; --396
        --N_MM    <= "1001101101"; --621
 
        SEED <= "00000000000000000001000100000101" when SEED_IN = 0 else SEED_IN; --default seed
        KK_MAX <= "1001101111"; --623
        ADDR_MAX <= "100110111"; --311
 
        --memory control
        MEM_SEL <= '0' when KK(0) = '0' and CS = MEM_INIT else
                           '1' when KK(0) = '1' and CS = MEM_INIT else
                           '0' when ((to_integer(unsigned(KK))) mod 2) = 0 and RESET = '0' and CS = MT_GEN else
                           '1' when RESET = '0' and CS = MT_GEN else
                   '0';
 
        WR_ENABLE0      <= '1' when (CS = MEM_INIT and MEM_SEL = '0') or (CS = MT_GEN and INNER_STATE = "011" and MEM_SEL = '0')
                                else '0';
        WR_ENABLE1      <= '1' when (CS = MEM_INIT and MEM_SEL = '1') or (CS = MT_GEN and INNER_STATE = "011" and MEM_SEL = '1')
                                else '0';
        RD_ENABLE0      <= '1' when (NS = MT_GEN)
                                else '0';
        RD_ENABLE1      <= '1' when (NS = MT_GEN)
                                else '0';
 
        MEM0_IN <=  WRITE_DATA when MEM_SEL = '0' and CS = MEM_INIT
                                else DATA_MT_GEN when MEM_SEL = '0' and CS = MT_GEN and INNER_STATE = "011"
                                else ( others => '0' );
        MEM1_IN <=  WRITE_DATA when MEM_SEL = '1' and (CS = MEM_INIT or (CS = MT_GEN and INNER_STATE = "001"))
                                else DATA_MT_GEN when MEM_SEL = '1' and CS = MT_GEN and INNER_STATE = "011"
                                else ( others => '0' );
 
        MEM0_WR_PROC : process(CLK, RESET)
        begin
                if RESET = '1' then
                        WR_ADDR0 <= (others => '0');
                elsif CLK = '1' and CLK'event then
                        if CS = MEM_INIT then
                                if INNER_STATE(2) = '1' and MEM_SEL = '0' and WR_ADDR0 /= ADDR_MAX then
                                        WR_ADDR0 <= WR_ADDR0 + 1;
                                elsif INNER_STATE(2) = '1' and MEM_SEL = '0' and WR_ADDR0 = ADDR_MAX then
                                        WR_ADDR0 <= (others => '0');
                                else
                                        WR_ADDR0 <= WR_ADDR0;
                                end if;
                        elsif CS = MT_GEN then
                                if WR_ADDR0 /= ADDR_MAX and INNER_STATE = "011" and MEM_SEL = '0' then
                                        WR_ADDR0 <= WR_ADDR0 + 1;
                                elsif WR_ADDR0 = ADDR_MAX and MEM_SEL = '0' and INNER_STATE = "011" then
                                        WR_ADDR0 <= (others => '0');
                                else
                                        WR_ADDR0 <= WR_ADDR0;
                                end if;
                        elsif CS = PAUSE_STATE then
                                WR_ADDR0 <= WR_ADDR0;
                        else
                                WR_ADDR0 <= (others => '0');
                        end if;
                end if;
        end process;
 
        MEM0_WR_DELAY : process (CLK, RESET)
        begin
                if RESET = '1' then
                        WR_ADDR0_Q <= (others => '0');
                        WR_ADDR0_QQ <= (others => '0');
                        WR_ADDR0_QQQ <= (others => '0');
                        WR_ADDR0_QQQQ <= (others => '0');
                elsif CLK='1' and CLK'event then
                        WR_ADDR0_Q <= WR_ADDR0;
                        WR_ADDR0_QQ <= WR_ADDR0_Q;
                        WR_ADDR0_QQQ <= WR_ADDR0_QQ;
                        WR_ADDR0_QQQQ <= WR_ADDR0_QQQ;
                end if;
        end process;
 
        WR_ADDR1 <= WR_ADDR0_QQQQ when CS = MEM_INIT else
                                WR_ADDR0_QQQ when CS = MT_GEN;
 
        ADDR_SHF_IN <= KK + M_CONST when KK < MN_DIFF and CS = MT_GEN else
                                   KK - MN_DIFF when (KK >= MN_DIFF and KK < N_MINUS) and CS = MT_GEN else
                                   M_MINUS when KK = N_MINUS and CS = MT_GEN
                                   else (others => '0');
 
        ADDR_SHF_OUT <= '0' & ADDR_SHF_IN(9 downto 1);
 
        MEM0_RD_PROC : process(CS, INNER_STATE, MEM_SEL, ADDR_SHF_OUT, WR_ADDR0)
        begin
                if CS = MT_GEN then
                        if INNER_STATE = "001" then
                                RD_ADDR0 <= WR_ADDR0;
                        elsif INNER_STATE = "010" and MEM_SEL = '1' then
                                RD_ADDR0 <= ADDR_SHF_OUT( 8 downto 0 );
            else
                            RD_ADDR0<= WR_ADDR0;
                        end if;
                else
                        RD_ADDR0 <= (others => '0');
                end if;
        end process;
 
        MEM1_RD_PROC : process(CS, INNER_STATE, MEM_SEL, ADDR_SHF_OUT, WR_ADDR1)
        begin
                if CS = MT_GEN then
                        if INNER_STATE = "001" then
                        RD_ADDR1 <= WR_ADDR1;
                        elsif INNER_STATE = "010" and MEM_SEL = '0' then
                                RD_ADDR1 <= ADDR_SHF_OUT( 8 downto 0 );
                        else
                            RD_ADDR1 <= WR_ADDR1;
                        end if;
                else
                        RD_ADDR1 <= (others => '0');
                end if;
        end process;
 
        OPRAND1 <= MEM0_OUT when MEM_SEL = '0' and CS = MT_GEN and INNER_STATE = "010"
                                else MEM1_OUT when MEM_SEL = '1' and CS = MT_GEN and INNER_STATE = "010"
                                else (others =>'0');
 
        OPRAND2 <= MEM0_OUT when MEM_SEL = '1' and CS = MT_GEN and INNER_STATE = "010"
                                else MEM1_OUT when MEM_SEL = '0' and CS = MT_GEN and INNER_STATE = "010"
                                else (others=>'0');
 
        OPRAND3 <= MEM0_OUT when MEM_SEL = '1' and CS = MT_GEN and INNER_STATE = "011"
                                else MEM1_OUT when MEM_SEL = '0' and CS = MT_GEN and INNER_STATE = "011"
                                else (others =>'0');
 
 
        MT_DATAPATH : MT_PATH
        port map(
                OPRAND1 => OPRAND1,
                OPRAND2 => OPRAND2,
                OPRAND3 => OPRAND3,
                CLK => CLK,
                RESET => RESET,
                OUTPUT => DATA_MT_GEN
        );
 
        MT_RN_GEN : MT_SHIFTING
        port map(
                INPUT   => DATA_MT_GEN,
                OUTPUT  => OUTPUT
        );
 
        DONE_INIT <= '0' when NS = MEM_INIT else '1';
        OUT_SIG <= '1' when CS = MT_GEN and (INNER_STATE = "010" or INNER_STATE = "011") else '0';
 
end BEHAVE;

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Subversion Repositories complex-gaussian-pseudo-random-number-generator

[/] [complex-gaussian-pseudo-random-number-generator/] [trunk/] [urng/] [MT_GET.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	cowboyor	`--/////////////////////////MT_GET BLOCK///////////////////////////////`
2			`--Purpose: to produce functionality equivalent to following C code:`
3			`--`
4			`--`
5			`--Created by: Minzhen Ren`
6			`--Last Modified by: Minzhen Ren`
7			`--Last Modified Date: Auguest 30, 2010`
8			`--Lately Updates:`
9			`--/////////////////////////////////////////////////////////////////`
10			`library ieee;`
11			`use ieee.std_logic_1164.all;`
12			`use ieee.std_logic_unsigned.all;`
13			`use ieee.numeric_std.all;`
14			`use ieee.math_real.all;`
15
16			`entity MT_GET is`
17			`generic(`
18			`DATA_WIDTH : Natural := 32`
19			`);`
20			`port(`
21			`signal CLK : in std_logic;`
22			`signal RESET : in std_logic;`
23			`signal SEED_IN : in std_logic_vector( DATA_WIDTH-1 downto 0 );`
24			`signal PAUSE : in std_logic;`
25			`signal DONE_INIT : out std_logic;`
26			`signal OUT_SIG : out std_logic;`
27			`signal OUTPUT : out std_logic_vector( DATA_WIDTH-1 downto 0 )`
28			`);`
29			`end MT_GET;`
30
31			`architecture BEHAVE of MT_GET is`
32			`--contant`
33			`signal M_CONST : std_logic_vector( 9 downto 0 );`
34			`signal N_CONST : std_logic_vector( 9 downto 0 );`
35			`signal MN_DIFF : std_logic_vector( 9 downto 0 );`
36			`signal M_MINUS : std_logic_vector( 9 downto 0 );`
37			`signal N_MINUS : std_logic_vector( 9 downto 0 );`
38
39			`--MT_SET interface`
40			`signal SEED : std_logic_vector( DATA_WIDTH-1 downto 0 );`
41			`signal WRITE_DATA : std_logic_vector( DATA_WIDTH-1 downto 0 );`
42			`signal IDLE_SIG : std_logic;`
43
44			`--Memory interface`
45			`signal ADDR_MAX : std_logic_vector( 8 downto 0 );`
46			`signal WR_ENABLE0 : std_logic;`
47			`signal WR_ADDR0 : std_logic_vector( 8 downto 0 );`
48			`signal WR_ADDR0_Q : std_logic_vector( 8 downto 0 );`
49			`signal WR_ADDR0_QQ : std_logic_vector( 8 downto 0 );`
50			`signal WR_ADDR0_QQQ : std_logic_vector( 8 downto 0 );`
51			`signal WR_ADDR0_QQQQ : std_logic_vector( 8 downto 0 );`
52			`signal RD_ENABLE0 : std_logic;`
53			`signal RD_ADDR0 : std_logic_vector( 8 downto 0 );`
54			`signal MEM0_IN : std_logic_vector( DATA_WIDTH-1 downto 0 );`
55			`signal MEM0_OUT : std_logic_vector( DATA_WIDTH-1 downto 0 );`
56			`signal WR_ENABLE1 : std_logic;`
57			`signal WR_ADDR1 : std_logic_vector( 8 downto 0 );`
58			`signal RD_ENABLE1 : std_logic;`
59			`signal RD_ADDR1 : std_logic_vector( 8 downto 0 );`
60			`signal MEM1_IN : std_logic_vector( DATA_WIDTH-1 downto 0 );`
61			`signal MEM1_OUT : std_logic_vector( DATA_WIDTH-1 downto 0 );`
62			`signal DATA_MT_GEN : std_logic_vector( DATA_WIDTH-1 downto 0 );`
63			`signal ADDR_SHF_IN : std_logic_vector( 9 downto 0 );`
64			`signal ADDR_SHF_OUT : std_logic_vector( 9 downto 0 );`
65			`signal OPRAND1 : std_logic_vector( DATA_WIDTH-1 downto 0 );`
66			`signal OPRAND2 : std_logic_vector( DATA_WIDTH-1 downto 0 );`
67			`signal OPRAND3 : std_logic_vector( DATA_WIDTH-1 downto 0 );`
68
69			`--Counter`
70			`signal KK : std_logic_vector( 9 downto 0 );`
71			`signal INNER_STATE : std_logic_vector( 2 downto 0 );`
72			`signal KK_MAX : std_logic_vector( 9 downto 0 );`
73
74			`--Control signal`
75			`signal MEM_SEL : std_logic;`
76
77			`--State Machine`
78			`type STATE_TYPE is (INITIAL, MEM_INIT, MT_GEN, PAUSE_STATE);`
79			`signal CS : STATE_TYPE;`
80			`signal NS : STATE_TYPE;`
81
82			`component MT_SET is`
83			`generic(`
84			`DATA_WIDTH : Natural := 32`
85			`);`
86			`port(`
87			`signal CLK : in std_logic;`
88			`signal RESET : in std_logic;`
89			`signal IDLE_SIG : in std_logic;`
90			`signal S_IN : in std_logic_vector( DATA_WIDTH-1 downto 0 );`
91			`signal S_OUT : out std_logic_vector( DATA_WIDTH-1 downto 0 )`
92			`);`
93			`end component;`
94
95			`component dp_mem is`
96			`generic (`
97			`Addr_Wdth : Natural := 9;`
98			`Bit_Wdth : Natural := 32`
99			`);`
100			`port (Clock : in Std_Logic;`
101			`Write_Enable : in Std_Logic;`
102			`Write_Address : in Std_Logic_Vector(Addr_Wdth-1 downto 0);`
103			`Read_Enable : in Std_Logic;`
104			`Read_Address : in Std_Logic_Vector(Addr_Wdth-1 downto 0);`
105			`Data_In : in Std_Logic_Vector(Bit_Wdth-1 downto 0);`
106			`Data_Out : out Std_Logic_Vector(Bit_Wdth-1 downto 0));`
107			`end component;`
108
109			`component MT_PATH is`
110			`generic(`
111			`DATA_WIDTH : Natural := 32`
112			`);`
113			`port(`
114			`signal OPRAND1 : in std_logic_vector( DATA_WIDTH-1 downto 0 );`
115			`signal OPRAND2 : in std_logic_vector( DATA_WIDTH-1 downto 0 );`
116			`signal OPRAND3 : in std_logic_vector( DATA_WIDTH-1 downto 0 );`
117			`signal CLK : in std_logic;`
118			`signal RESET : in std_logic;`
119			`signal OUTPUT : out std_logic_vector( DATA_WIDTH-1 downto 0 )`
120			`);`
121			`end component;`
122
123			`component MT_SHIFTING is`
124			`generic(`
125			`DATA_WIDTH : Natural := 32`
126			`);`
127			`port(`
128			`signal INPUT : in std_logic_vector( DATA_WIDTH-1 downto 0 );`
129			`signal OUTPUT : out std_logic_vector( DATA_WIDTH-1 downto 0 )`
130			`);`
131			`end component;`
132
133			`begin`
134
135			`MT_BLK : MT_SET`
136			`port map(`
137			`S_IN => SEED,`
138			`S_OUT => WRITE_DATA,`
139			`CLK => CLK,`
140			`RESET => RESET,`
141			`IDLE_SIG => IDLE_SIG`
142			`);`
143
144			`MEM0 : dp_mem`
145			`port map(`
146			`Clock => CLK,`
147			`Write_Enable => WR_ENABLE0,`
148			`Write_Address => WR_ADDR0,`
149			`Read_Enable => RD_ENABLE0,`
150			`Read_Address => RD_ADDR0,`
151			`Data_In => MEM0_IN,`
152			`Data_Out => MEM0_OUT`
153			`);`
154
155			`MEM1 : dp_mem`
156			`port map(`
157			`Clock => CLK,`
158			`Write_Enable => WR_ENABLE1,`
159			`Write_Address => WR_ADDR1,`
160			`Read_Enable => RD_ENABLE1,`
161			`Read_Address => RD_ADDR1,`
162			`Data_In => MEM1_IN,`
163			`Data_Out => MEM1_OUT`
164			`);`
165
166			`CURRENT_STATE : process(CLK, RESET)`
167			`begin`
168			`if RESET = '1' then`
169			`CS <= INITIAL;`
170			`elsif CLK='1' and CLK'event then`
171			`CS <= NS;`
172			`end if;`
173			`end process;`
174
175			`NEXT_STATE : process(CS, KK, N_MINUS, INNER_STATE, PAUSE)`
176			`begin`
177			`if CS = INITIAL then`
178			`NS <= MEM_INIT;`
179			`elsif CS = MEM_INIT then`
180			`if KK = N_MINUS and INNER_STATE(2) = '1' then`
181			`NS <= MT_GEN;`
182			`else`
183			`NS <= CS;`
184			`end if;`
185			`elsif CS <= MT_GEN then`
186			`if PAUSE = '1' then`
187			`NS <= PAUSE_STATE;`
188			`else`
189			`NS <= MT_GEN;`
190			`end if;`
191			`elsif CS <= PAUSE_STATE then`
192			`if PAUSE = '0' then`
193			`NS <= MT_GEN;`
194			`else`
195			`NS <= PAUSE_STATE;`
196			`end if;`
197			`else`
198			`NS <= INITIAL;`
199			`end if;`
200			`end process;`
201
202			`COUNTER_PROC : process(CLK, RESET)`
203			`begin`
204			`if RESET = '1' then`
205			`KK <= (others => '0');`
206			`elsif CLK'event and CLK='1' then`
207			`if CS = INITIAL then`
208			`KK <= (others => '0');`
209			`elsif CS = MEM_INIT then`
210			`if INNER_STATE(2) = '1' and KK /= N_MINUS then`
211			`KK <= KK + 1;`
212			`elsif INNER_STATE(2) = '1' and KK = N_MINUS then`
213			`KK <= (others => '0');`
214			`else`
215			`KK <= KK;`
216			`end if;`
217			`elsif CS = MT_GEN then`
218			`if INNER_STATE = "011" and KK /= N_MINUS then`
219			`KK <= KK + 1;`
220			`elsif INNER_STATE = "011" and KK = N_MINUS then`
221			`KK <= (others => '0');`
222			`end if;`
223			`elsif CS = PAUSE_STATE then`
224			`KK <= KK;`
225			`else`
226			`KK <= (others => '0');`
227			`end if;`
228			`end if;`
229			`end process;`
230
231			`INNER_STATE_COUNTER : process(CLK, RESET)`
232			`begin`
233			`if RESET = '1' then`
234			`INNER_STATE <= (others => '0');`
235			`elsif CLK'event and CLK='1' then`
236			`if CS = INITIAL then`
237			`INNER_STATE <= (others => '0');`
238			`elsif CS = MEM_INIT then`
239			`if INNER_STATE(2) = '0' then`
240			`INNER_STATE <= INNER_STATE + '1';`
241			`else`
242			`INNER_STATE <= "001";`
243			`end if;`
244			`elsif CS = MT_GEN then`
245			`if INNER_STATE < "011" then`
246			`INNER_STATE <= INNER_STATE + '1';`
247			`else`
248			`INNER_STATE <= "001";`
249			`end if;`
250			`elsif CS = PAUSE_STATE then`
251			`INNER_STATE <= "001";`
252			`else`
253			`INNER_STATE <= (others => '0');`
254			`end if;`
255			`end if;`
256			`end process;`
257
258			`IDLE_SIG <= '0' when CS = MEM_INIT and RESET = '0' else '1';`
259
260			`--constants`
261			`N_CONST <= "1001110000"; --624`
262			`M_CONST <= "0110001101"; --397`
263			`MN_DIFF <= "0011100011"; --227`
264			`N_MINUS <= "1001101111"; --623`
265			`M_MINUS <= "0110001100"; --396`
266			`--N_MM <= "1001101101"; --621`
267
268			`SEED <= "00000000000000000001000100000101" when SEED_IN = 0 else SEED_IN; --default seed`
269			`KK_MAX <= "1001101111"; --623`
270			`ADDR_MAX <= "100110111"; --311`
271
272			`--memory control`
273			`MEM_SEL <= '0' when KK(0) = '0' and CS = MEM_INIT else`
274			`'1' when KK(0) = '1' and CS = MEM_INIT else`
275			`'0' when ((to_integer(unsigned(KK))) mod 2) = 0 and RESET = '0' and CS = MT_GEN else`
276			`'1' when RESET = '0' and CS = MT_GEN else`
277			`'0';`
278
279			`WR_ENABLE0 <= '1' when (CS = MEM_INIT and MEM_SEL = '0') or (CS = MT_GEN and INNER_STATE = "011" and MEM_SEL = '0')`
280			`else '0';`
281			`WR_ENABLE1 <= '1' when (CS = MEM_INIT and MEM_SEL = '1') or (CS = MT_GEN and INNER_STATE = "011" and MEM_SEL = '1')`
282			`else '0';`
283			`RD_ENABLE0 <= '1' when (NS = MT_GEN)`
284			`else '0';`
285			`RD_ENABLE1 <= '1' when (NS = MT_GEN)`
286			`else '0';`
287
288			`MEM0_IN <= WRITE_DATA when MEM_SEL = '0' and CS = MEM_INIT`
289			`else DATA_MT_GEN when MEM_SEL = '0' and CS = MT_GEN and INNER_STATE = "011"`
290			`else ( others => '0' );`
291			`MEM1_IN <= WRITE_DATA when MEM_SEL = '1' and (CS = MEM_INIT or (CS = MT_GEN and INNER_STATE = "001"))`
292			`else DATA_MT_GEN when MEM_SEL = '1' and CS = MT_GEN and INNER_STATE = "011"`
293			`else ( others => '0' );`
294
295			`MEM0_WR_PROC : process(CLK, RESET)`
296			`begin`
297			`if RESET = '1' then`
298			`WR_ADDR0 <= (others => '0');`
299			`elsif CLK = '1' and CLK'event then`
300			`if CS = MEM_INIT then`
301			`if INNER_STATE(2) = '1' and MEM_SEL = '0' and WR_ADDR0 /= ADDR_MAX then`
302			`WR_ADDR0 <= WR_ADDR0 + 1;`
303			`elsif INNER_STATE(2) = '1' and MEM_SEL = '0' and WR_ADDR0 = ADDR_MAX then`
304			`WR_ADDR0 <= (others => '0');`
305			`else`
306			`WR_ADDR0 <= WR_ADDR0;`
307			`end if;`
308			`elsif CS = MT_GEN then`
309			`if WR_ADDR0 /= ADDR_MAX and INNER_STATE = "011" and MEM_SEL = '0' then`
310			`WR_ADDR0 <= WR_ADDR0 + 1;`
311			`elsif WR_ADDR0 = ADDR_MAX and MEM_SEL = '0' and INNER_STATE = "011" then`
312			`WR_ADDR0 <= (others => '0');`
313			`else`
314			`WR_ADDR0 <= WR_ADDR0;`
315			`end if;`
316			`elsif CS = PAUSE_STATE then`
317			`WR_ADDR0 <= WR_ADDR0;`
318			`else`
319			`WR_ADDR0 <= (others => '0');`
320			`end if;`
321			`end if;`
322			`end process;`
323
324			`MEM0_WR_DELAY : process (CLK, RESET)`
325			`begin`
326			`if RESET = '1' then`
327			`WR_ADDR0_Q <= (others => '0');`
328			`WR_ADDR0_QQ <= (others => '0');`
329			`WR_ADDR0_QQQ <= (others => '0');`
330			`WR_ADDR0_QQQQ <= (others => '0');`
331			`elsif CLK='1' and CLK'event then`
332			`WR_ADDR0_Q <= WR_ADDR0;`
333			`WR_ADDR0_QQ <= WR_ADDR0_Q;`
334			`WR_ADDR0_QQQ <= WR_ADDR0_QQ;`
335			`WR_ADDR0_QQQQ <= WR_ADDR0_QQQ;`
336			`end if;`
337			`end process;`
338
339			`WR_ADDR1 <= WR_ADDR0_QQQQ when CS = MEM_INIT else`
340			`WR_ADDR0_QQQ when CS = MT_GEN;`
341
342			`ADDR_SHF_IN <= KK + M_CONST when KK < MN_DIFF and CS = MT_GEN else`
343			`KK - MN_DIFF when (KK >= MN_DIFF and KK < N_MINUS) and CS = MT_GEN else`
344			`M_MINUS when KK = N_MINUS and CS = MT_GEN`
345			`else (others => '0');`
346
347			`ADDR_SHF_OUT <= '0' & ADDR_SHF_IN(9 downto 1);`
348
349			`MEM0_RD_PROC : process(CS, INNER_STATE, MEM_SEL, ADDR_SHF_OUT, WR_ADDR0)`
350			`begin`
351			`if CS = MT_GEN then`
352			`if INNER_STATE = "001" then`
353			`RD_ADDR0 <= WR_ADDR0;`
354			`elsif INNER_STATE = "010" and MEM_SEL = '1' then`
355			`RD_ADDR0 <= ADDR_SHF_OUT( 8 downto 0 );`
356			`else`
357			`RD_ADDR0<= WR_ADDR0;`
358			`end if;`
359			`else`
360			`RD_ADDR0 <= (others => '0');`
361			`end if;`
362			`end process;`
363
364			`MEM1_RD_PROC : process(CS, INNER_STATE, MEM_SEL, ADDR_SHF_OUT, WR_ADDR1)`
365			`begin`
366			`if CS = MT_GEN then`
367			`if INNER_STATE = "001" then`
368			`RD_ADDR1 <= WR_ADDR1;`
369			`elsif INNER_STATE = "010" and MEM_SEL = '0' then`
370			`RD_ADDR1 <= ADDR_SHF_OUT( 8 downto 0 );`
371			`else`
372			`RD_ADDR1 <= WR_ADDR1;`
373			`end if;`
374			`else`
375			`RD_ADDR1 <= (others => '0');`
376			`end if;`
377			`end process;`
378
379			`OPRAND1 <= MEM0_OUT when MEM_SEL = '0' and CS = MT_GEN and INNER_STATE = "010"`
380			`else MEM1_OUT when MEM_SEL = '1' and CS = MT_GEN and INNER_STATE = "010"`
381			`else (others =>'0');`
382
383			`OPRAND2 <= MEM0_OUT when MEM_SEL = '1' and CS = MT_GEN and INNER_STATE = "010"`
384			`else MEM1_OUT when MEM_SEL = '0' and CS = MT_GEN and INNER_STATE = "010"`
385			`else (others=>'0');`
386
387			`OPRAND3 <= MEM0_OUT when MEM_SEL = '1' and CS = MT_GEN and INNER_STATE = "011"`
388			`else MEM1_OUT when MEM_SEL = '0' and CS = MT_GEN and INNER_STATE = "011"`
389			`else (others =>'0');`
390
391
392			`MT_DATAPATH : MT_PATH`
393			`port map(`
394			`OPRAND1 => OPRAND1,`
395			`OPRAND2 => OPRAND2,`
396			`OPRAND3 => OPRAND3,`
397			`CLK => CLK,`
398			`RESET => RESET,`
399			`OUTPUT => DATA_MT_GEN`
400			`);`
401
402			`MT_RN_GEN : MT_SHIFTING`
403			`port map(`
404			`INPUT => DATA_MT_GEN,`
405			`OUTPUT => OUTPUT`
406			`);`
407
408			`DONE_INIT <= '0' when NS = MEM_INIT else '1';`
409			`OUT_SIG <= '1' when CS = MT_GEN and (INNER_STATE = "010" or INNER_STATE = "011") else '0';`
410
411			`end BEHAVE;`