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[/] [cryptography/] [trunk/] [decryption/] [decryptor.vhd.bak] - Blame information for rev 4

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 
entity decryptor is
 
port   (
         plaintext_d :out std_logic_vector(15 downto 0);-- 16 bit Plaintext output of decryptor
         ready_d           :out std_logic;     -- 1 bit ready output of decryptor
        ciphertext        :in std_logic_vector(15 downto 0);-- 16 bit ciphertext input to decrytpor which is output of encryptor
         round_keys_d:in std_logic_vector(15 downto 0);--  16 bit roundkeys given to decryptor
         start_d                   :in std_logic;
         reset              :in std_logic;
         clock              :in std_logic
       );
 
end  decryptor;
 
 
Architecture arch_decryptor of decryptor is
 
component multiplier
port( B  :in std_logic_vector(15 downto 0);
    Product :out std_logic_vector(15 downto 0)
    );
end component;
-- constants for the plain text fsm
 
constant   idle:std_logic_vector(3 downto 0):= "0000";
constant out_A :std_logic_vector(3 downto 0):= "0001";
constant out_B :std_logic_vector(3 downto 0):= "0010";
constant out_C :std_logic_vector(3 downto 0):= "0011";
constant out_D :std_logic_vector(3 downto 0):= "0100";
 
 
 
 
--ct1, ttemp and utemp are temprary registers to hold the values of t, u and C.
--signal round_keys_d_saved:std_logic_vector(15 downto 0);
signal ready_d_pre: std_logic; -- ready_d_pre is used to trigger the plaintext fsm (earlier version of ready_d)
 
signal  state:std_logic_vector(5 downto 0); --state of primary fsm
signal state_out:std_logic_vector(3 downto 0); -- state of plaintext fsm
 
signal sig3,sig4:integer range 0 TO 15;
 
signal last_round ,cleanup : std_logic;
signal A_final,B_final,C_final,D_final:std_logic_vector(15 downto 0);
signal utemp1,ttemp1    :std_logic_vector(15 downto 0);-------a_new
signal A, B, C, D :std_logic_vector(15 downto 0);
signal product1,product2  : std_logic_vector(15 downto 0);
---key constant------
 
        constant p:std_logic_vector(15 downto 0):= "1011011111100001";
        constant q:std_logic_vector(15 downto 0):= "1001111000110111";
 
        type s_tp is array(43 downto 0) of std_logic_vector(15 downto 0);
                        signal s :s_tp;
        type l_tp is array(42 downto 0) of std_logic_vector(15 downto 0);
                        signal l :l_tp;
 
 
 
begin
 
a1: multiplier port map (B,product1);
b1: multiplier port map (D,product2);
 
 
        sig3<=conv_integer(unsigned(utemp1(3 downto 0)));
        sig4<=conv_integer(unsigned(ttemp1(3 downto 0)));
 
 
        ----key algo----
 
 
                                        s(0) <= P ;                                             --   initialize constant array
                                        l(0)<=(round_keys_d + s(0));
                                        s(1)<=(l(0)+ s(0)+ q);
                                        l(1)<=( l(0)+s(1));
                                        s(2)<=(l(1)+ s(1)+ q);
                                        l(2)<=( l(1)+s(2));
                                        s(3)<=(l(2)+ s(2)+ q);
                                        l(3)<=( l(2)+s(3));
                                        s(4)<=(l(3)+ s(3)+ q);
                                        l(4)<=( l(3)+s(4));
                                        s(5)<=(l(4)+ s(4)+ q);
                                        l(5)<=( l(4)+s(5));
                                        s(6)<=(l(5)+ s(5)+ q);
                                        l(6)<=( l(5)+s(6));
                                        s(7)<=(l(6)+ s(6)+ q);
                                        l(7)<=( l(6)+s(7));
                                        s(8)<=(l(7)+ s(7)+ q);
                                        l(8)<=( l(7)+s(8));
                                        s(9)<=(l(8)+ s(8)+ q);
                                        l(9)<=( l(8)+s(9));
                                        s(10)<=(l(9)+ s(9)+ q);
                                        l(10)<=( l(9)+s(10 ));
                                        s(11)<=(l(10)+ s(10)+ q);
                                        l(11)<=( l(10)+s(11));
                                        s(12)<=(l(11)+ s(11)+ q);
                                        l(12)<=( l(11)+s(12));
                                        s(13)<=(l(12)+ s(12)+ q);
                                        l(13)<=( l(12)+s(13));
                                        s(14)<=(l(13)+ s(13)+ q);
                                        l(14)<=( l(13)+s(14));
                                        s(15)<=(l(14)+ s(14)+ q);
                                        l(15)<=( l(14)+s(15));
                                        s(16)<=(l(15)+ s(15)+ q);
                                        l(16)<=( l(15)+s(16));
                                        s(17)<=(l(16)+ s(16)+ q);
                                        l(17)<=( l(16)+s(17));
                                        s(18)<=(l(17)+ s(17)+ q);
                                        l(18)<=( l(17)+s(18));
                                        s(19)<=(l(18)+ s(18)+ q);
                                        l(19)<=( l(18)+s(19));
                                        s(20)<=(l(19)+ s(19)+ q);
                                        l(20)<=( l(19)+s(20));
                                        s(21)<=(l(20)+ s(20)+ q);
                                        l(21)<=( l(20)+s(21));
                                        s(22)<=(l(21)+ s(21)+ q);
                                        l(22)<=( l(21)+s(22));
                                        s(23)<=(l(22)+ s(22)+ q);
                                        l(23)<=( l(22)+s(23));
                                        s(24)<=(l(23)+ s(23)+ q);
                                        l(24)<=( l(23)+s(24));
                                        s(25)<=(l(24)+ s(24)+ q);
                                        l(25)<=( l(24)+s(25));
                                        s(26)<=(l(25)+ s(25)+ q);
                                        l(26)<=( l(25)+s(26));
                                        s(27)<=(l(26)+ s(26)+ q);
                                        l(27)<=( l(26)+s(27));
                                        s(28)<=(l(27)+ s(27)+ q);
                                        l(28)<=( l(27)+s(28));
                                        s(29)<=(l(28)+ s(28)+ q);
                                        l(29)<=( l(23)+s(24));
                                        s(30)<=(l(29)+ s(29)+ q);
                                        l(30)<=( l(29)+s(30));
                                        s(31)<=(l(30)+ s(30)+ q);
                                        l(31)<=( l(30)+s(31));
                                        s(32)<=(l(31)+ s(31)+ q);
                                        l(32)<=( l(31)+s(32));
                                        s(33)<=(l(32)+ s(32)+ q);
                                        l(33)<=( l(32)+s(33));
                                        s(34)<=(l(33)+ s(33)+ q);
                                        l(34)<=( l(33)+s(34));
                                        s(35)<=(l(34)+ s(34)+ q);
                                        l(35)<=( l(34)+s(35));
                                        s(36)<=(l(35)+ s(35)+ q);
                                        l(36)<=( l(35)+s(36));
                                        s(37)<=(l(36)+ s(36)+ q);
                                        l(37)<=( l(36)+s(37));
                                        s(38)<=(l(37)+ s(37)+ q);
                                        l(38)<=( l(37)+s(38));
                                        s(39)<=(l(38)+ s(38)+ q);
                                        l(39)<=( l(33)+s(34));
                                        s(40)<=(l(39)+ s(39)+ q);
                                        l(40)<=( l(39)+s(40));
                                        s(40)<=(l(39)+ s(39)+ q);
                                        l(41)<=( l(40)+s(40));
                                        s(41)<=(l(40)+ s(40)+ q);
                                        l(42)<=( l(41)+s(41));
                                        s(42)<=(l(41)+ s(41)+ q);
                                        s(43)<=(l(42)+ s(42)+ q);
 
 
 
process(clock,reset,ciphertext,sig3,sig4)
 
 
variable tempA,tempB,tempC,tempD :std_logic_vector(15 downto 0);
variable temp_AD,temp_BA,temp_CB,temp_DC :std_logic_vector(15 downto 0);
VARIABLE t,u,t_pre,u_pre:std_logic_vector( 15 downto 0);--temporary VARIABLE used for calculation of A, C, t and u
VARIABLE A_pre_2,C_pre_2,A_pre ,C_pre  :std_logic_vector(15 downto 0);
 
variable cnt: std_logic_vector(6 downto 0):="0000000";
 
 
begin
        if (reset='1') then
 
                state <= "000001"; -- reset state
                ready_d <= '0';
 
                cnt :=(others=>'0');
 
                A := (others=>'0');
                B := (others=>'0');
                C := (others=>'0');
                D := (others=>'0');
                ready_d <= '0';
                                        TEMPA:=(others=>'0');
                                        TEMPB:=(others=>'0');
                                        TEMPC:=(others=>'0');
                                        TEMPD:=(others=>'0');
                                        temp_AD:= (others=>'0');
                                        temp_BA:= (others=>'0');
                                        temp_CB:= (others=>'0');
                                        temp_DC:= (others=>'0');
 
 
        elsif(clock'event and clock='1') then
 
          case state is  --synopsys parallel_case
                when"000001"=>
 
                        if (start_d = '0') then
                               state <= "000001";
                        else
                                state <= "000010";
                                ready_d <= '1';
                    end if;
 
 
               when "000010"=>
 
                        state <= "000011";
                        A := ciphertext;--read ciphertext into A
                        ready_d <= '0';
 
                when "000011"=>
 
                        state <= "000100";
                        B := ciphertext; -- read ciphertext into B
                        ready_d <= '0';
 
 
                when "000100"=>
 
                        state <= "000101";
                        C := ciphertext;  -- read ciphertext  into C
                        ready_d <= '0';
 
 
                when "000101"=>
 
                        state <= "000110";
                        D :=  ciphertext;--assign ciphertext to D
                        A :=  A - s(42); -- Use round keys to calculate new value of A
                        C :=  C - s(43); -- read ciphertext - roundkeys into C
                        ready_d <= '0';
 
 
               when "000110"=>  -- begin calculation of plaintext loop from r downto 1
                                        state <= "001000";
                                 TEMPA:=A;
                                 TEMPB:=B;
                                 TEMPC:=C;
                                 TEMPD:=D;
  --swap the value of A, B ,C and D  so that new value of A,B ,C AND D can be used.
                                temp_AD:= tempA xor tempD;
                                A:= temp_AD xor tempA;
 
                                temp_BA:= tempB xor tempA;
                                B:= temp_BA xor tempB;
 
                                temp_CB:= tempC xor tempB;
                                C:= temp_CB xor tempC;
 
                                temp_DC:= tempD xor tempC;
                                D:= temp_DC xor tempD;
 
                         ready_d <= '0';
 
 
                when "001000"=>
 
                        STATE <="001001";
 
 
                                t_pre := product1;
 
 
                                u_pre := product2;
 
                                t:= t_pre(11 downto 0) & t_pre(15 downto 12);
                                ttemp1<=t;
 
 
                                u:= u_pre(11 downto 0)& u_pre(15 downto 12);
                                utemp1<=u;
 
                                 ready_d <= '0';
 
 
 
                when "001001"=>
 
                        state <= "001010";
 
                        for i in 1 to 20 loop
                              A_pre_2 := (A - s(2*i));                  -- A = A-S[2i]
                        C_pre_2 := (C - s(2*i+1));      -- C = C - S[2i+1]
                        end loop ;
                        ready_d <= '0';
 
                                                                --sig3<=conv_integer(unsigned(u(3 downto 0)));
                        A_pre   :=A_pre_2(sig3-1 downto 0) & A_pre_2(15 downto sig3);
 
                        A := (A_pre xor t);                     -- A = ((A-S[2i] >>>u) xor  t
                                                                        --sig4<=conv_integer(unsigned(t(3 downto 0)));
                        C_pre:=C_pre_2(sig4-1 downto 0)& C_pre_2(15 downto sig4);
 
                        C := (C_pre xor u); -- C = ((C-S[2i+1]>>>t) xor u
 
                when "001010"=>
 
                        state <= "000001";
                                        if(cnt<19 )then
                                                cnt:=cnt+1      ;
                                                state <="000110";
                                        else
                                                last_round <='1';
                                                state<="001011";
                                                cnt:="0000000" ;
                                                end if;
 
 
 
 
 
               when "001011"=>
 
                        state <= "001100";
                        D := D - s(1); -- Calculate final value of D
                        ready_d <= '0';
 
 
 
                when "001100" =>
 
                        state <= "001101";
                        B := B - s(0); -- Calculate final value of B
                        ready_d <= '1'; -- set ready_d signal high as decryption process is over
 
                        cleanup<='1';
                        ready_d_pre <= '1';-- Assign ready_d_pre high which essentially starts up second FSM.
 
                when "001101" =>
 
                        if(cleanup='1') then
                                A_final <= A;
                                B_final <= B;
                                C_final <= C;
                                D_final <= D;
                        else
                                A_final <= A_final ;
                                B_final <= B_final ;
                                C_final <= C_final ;
                                D_final <= D_final ;
                        end if;
 
 
                when others=>
                        state <= "000001";
                        ready_d <= '1';
                        A := (others=>'0');
                        B := (others=>'0');
                        C := (others=>'0');
                        D := (others=>'0');
 
                end case;
        end if;
end process;
 
 
process(clock,reset,ready_d_pre,A_final,B_final,C_final,D_final)
        begin
                if (reset='1') then
 
                        state_out <= idle;
                        plaintext_d <= (others=>'0');
 
                elsif (clock'event and clock='1') then
 
                        case state_out is --synopsys parallel_case
                        when idle=>
 
                                if (ready_d_pre='1') then
                                        state_out <= out_A;
                                else
                                        state_out <= idle;
                                plaintext_d <= (others=>'0');
                                end if;
                        when out_A=>
 
                                state_out <= out_B;
                                plaintext_d <= A_final; -- Output plaintext as A
 
 
                        when out_B=>
 
                                state_out <= out_C;
                                plaintext_d <= B_final; -- Output plaintext as B
 
                        when out_C=>
 
                                state_out <= out_D;
                                plaintext_d <= C_final;  -- Output plaintext as C
 
                       when out_D=>
 
                                state_out <= idle;
                                plaintext_d <= D_final; -- Output plaintext as D
 
                        when others=>
 
                                state_out <= idle;
                                plaintext_d <= (others=>'0');
 
                        end case;
                end if;
        end process;
 
end arch_decryptor ;
 
 
 
 
 
 
 

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[/] [cryptography/] [trunk/] [decryption/] [decryptor.vhd.bak] - Blame information for rev 4

Line No.	Rev	Author	Line
1	4	marcus.erl	`library IEEE;`
2			`use IEEE.STD_LOGIC_1164.ALL;`
3			`use IEEE.STD_LOGIC_ARITH.ALL;`
4			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
5
6
7			`entity decryptor is`
8
9			`port (`
10			`plaintext_d :out std_logic_vector(15 downto 0);-- 16 bit Plaintext output of decryptor`
11			`ready_d :out std_logic; -- 1 bit ready output of decryptor`
12			`ciphertext :in std_logic_vector(15 downto 0);-- 16 bit ciphertext input to decrytpor which is output of encryptor`
13			`round_keys_d:in std_logic_vector(15 downto 0);-- 16 bit roundkeys given to decryptor`
14			`start_d :in std_logic;`
15			`reset :in std_logic;`
16			`clock :in std_logic`
17			`);`
18
19			`end decryptor;`
20
21
22			`Architecture arch_decryptor of decryptor is`
23
24			`component multiplier`
25			`port( B :in std_logic_vector(15 downto 0);`
26			`Product :out std_logic_vector(15 downto 0)`
27			`);`
28			`end component;`
29			`-- constants for the plain text fsm`
30
31			`constant idle:std_logic_vector(3 downto 0):= "0000";`
32			`constant out_A :std_logic_vector(3 downto 0):= "0001";`
33			`constant out_B :std_logic_vector(3 downto 0):= "0010";`
34			`constant out_C :std_logic_vector(3 downto 0):= "0011";`
35			`constant out_D :std_logic_vector(3 downto 0):= "0100";`
36
37
38
39
40			`--ct1, ttemp and utemp are temprary registers to hold the values of t, u and C.`
41			`--signal round_keys_d_saved:std_logic_vector(15 downto 0);`
42			`signal ready_d_pre: std_logic; -- ready_d_pre is used to trigger the plaintext fsm (earlier version of ready_d)`
43
44			`signal state:std_logic_vector(5 downto 0); --state of primary fsm`
45			`signal state_out:std_logic_vector(3 downto 0); -- state of plaintext fsm`
46
47			`signal sig3,sig4:integer range 0 TO 15;`
48
49			`signal last_round ,cleanup : std_logic;`
50			`signal A_final,B_final,C_final,D_final:std_logic_vector(15 downto 0);`
51			`signal utemp1,ttemp1 :std_logic_vector(15 downto 0);-------a_new`
52			`signal A, B, C, D :std_logic_vector(15 downto 0);`
53			`signal product1,product2 : std_logic_vector(15 downto 0);`
54			`---key constant------`
55
56			`constant p:std_logic_vector(15 downto 0):= "1011011111100001";`
57			`constant q:std_logic_vector(15 downto 0):= "1001111000110111";`
58
59			`type s_tp is array(43 downto 0) of std_logic_vector(15 downto 0);`
60			`signal s :s_tp;`
61			`type l_tp is array(42 downto 0) of std_logic_vector(15 downto 0);`
62			`signal l :l_tp;`
63
64
65
66			`begin`
67
68			`a1: multiplier port map (B,product1);`
69			`b1: multiplier port map (D,product2);`
70
71
72			`sig3<=conv_integer(unsigned(utemp1(3 downto 0)));`
73			`sig4<=conv_integer(unsigned(ttemp1(3 downto 0)));`
74
75
76			`----key algo----`
77
78
79			`s(0) <= P ; -- initialize constant array`
80			`l(0)<=(round_keys_d + s(0));`
81			`s(1)<=(l(0)+ s(0)+ q);`
82			`l(1)<=( l(0)+s(1));`
83			`s(2)<=(l(1)+ s(1)+ q);`
84			`l(2)<=( l(1)+s(2));`
85			`s(3)<=(l(2)+ s(2)+ q);`
86			`l(3)<=( l(2)+s(3));`
87			`s(4)<=(l(3)+ s(3)+ q);`
88			`l(4)<=( l(3)+s(4));`
89			`s(5)<=(l(4)+ s(4)+ q);`
90			`l(5)<=( l(4)+s(5));`
91			`s(6)<=(l(5)+ s(5)+ q);`
92			`l(6)<=( l(5)+s(6));`
93			`s(7)<=(l(6)+ s(6)+ q);`
94			`l(7)<=( l(6)+s(7));`
95			`s(8)<=(l(7)+ s(7)+ q);`
96			`l(8)<=( l(7)+s(8));`
97			`s(9)<=(l(8)+ s(8)+ q);`
98			`l(9)<=( l(8)+s(9));`
99			`s(10)<=(l(9)+ s(9)+ q);`
100			`l(10)<=( l(9)+s(10 ));`
101			`s(11)<=(l(10)+ s(10)+ q);`
102			`l(11)<=( l(10)+s(11));`
103			`s(12)<=(l(11)+ s(11)+ q);`
104			`l(12)<=( l(11)+s(12));`
105			`s(13)<=(l(12)+ s(12)+ q);`
106			`l(13)<=( l(12)+s(13));`
107			`s(14)<=(l(13)+ s(13)+ q);`
108			`l(14)<=( l(13)+s(14));`
109			`s(15)<=(l(14)+ s(14)+ q);`
110			`l(15)<=( l(14)+s(15));`
111			`s(16)<=(l(15)+ s(15)+ q);`
112			`l(16)<=( l(15)+s(16));`
113			`s(17)<=(l(16)+ s(16)+ q);`
114			`l(17)<=( l(16)+s(17));`
115			`s(18)<=(l(17)+ s(17)+ q);`
116			`l(18)<=( l(17)+s(18));`
117			`s(19)<=(l(18)+ s(18)+ q);`
118			`l(19)<=( l(18)+s(19));`
119			`s(20)<=(l(19)+ s(19)+ q);`
120			`l(20)<=( l(19)+s(20));`
121			`s(21)<=(l(20)+ s(20)+ q);`
122			`l(21)<=( l(20)+s(21));`
123			`s(22)<=(l(21)+ s(21)+ q);`
124			`l(22)<=( l(21)+s(22));`
125			`s(23)<=(l(22)+ s(22)+ q);`
126			`l(23)<=( l(22)+s(23));`
127			`s(24)<=(l(23)+ s(23)+ q);`
128			`l(24)<=( l(23)+s(24));`
129			`s(25)<=(l(24)+ s(24)+ q);`
130			`l(25)<=( l(24)+s(25));`
131			`s(26)<=(l(25)+ s(25)+ q);`
132			`l(26)<=( l(25)+s(26));`
133			`s(27)<=(l(26)+ s(26)+ q);`
134			`l(27)<=( l(26)+s(27));`
135			`s(28)<=(l(27)+ s(27)+ q);`
136			`l(28)<=( l(27)+s(28));`
137			`s(29)<=(l(28)+ s(28)+ q);`
138			`l(29)<=( l(23)+s(24));`
139			`s(30)<=(l(29)+ s(29)+ q);`
140			`l(30)<=( l(29)+s(30));`
141			`s(31)<=(l(30)+ s(30)+ q);`
142			`l(31)<=( l(30)+s(31));`
143			`s(32)<=(l(31)+ s(31)+ q);`
144			`l(32)<=( l(31)+s(32));`
145			`s(33)<=(l(32)+ s(32)+ q);`
146			`l(33)<=( l(32)+s(33));`
147			`s(34)<=(l(33)+ s(33)+ q);`
148			`l(34)<=( l(33)+s(34));`
149			`s(35)<=(l(34)+ s(34)+ q);`
150			`l(35)<=( l(34)+s(35));`
151			`s(36)<=(l(35)+ s(35)+ q);`
152			`l(36)<=( l(35)+s(36));`
153			`s(37)<=(l(36)+ s(36)+ q);`
154			`l(37)<=( l(36)+s(37));`
155			`s(38)<=(l(37)+ s(37)+ q);`
156			`l(38)<=( l(37)+s(38));`
157			`s(39)<=(l(38)+ s(38)+ q);`
158			`l(39)<=( l(33)+s(34));`
159			`s(40)<=(l(39)+ s(39)+ q);`
160			`l(40)<=( l(39)+s(40));`
161			`s(40)<=(l(39)+ s(39)+ q);`
162			`l(41)<=( l(40)+s(40));`
163			`s(41)<=(l(40)+ s(40)+ q);`
164			`l(42)<=( l(41)+s(41));`
165			`s(42)<=(l(41)+ s(41)+ q);`
166			`s(43)<=(l(42)+ s(42)+ q);`
167
168
169
170			`process(clock,reset,ciphertext,sig3,sig4)`
171
172
173			`variable tempA,tempB,tempC,tempD :std_logic_vector(15 downto 0);`
174			`variable temp_AD,temp_BA,temp_CB,temp_DC :std_logic_vector(15 downto 0);`
175			`VARIABLE t,u,t_pre,u_pre:std_logic_vector( 15 downto 0);--temporary VARIABLE used for calculation of A, C, t and u`
176			`VARIABLE A_pre_2,C_pre_2,A_pre ,C_pre :std_logic_vector(15 downto 0);`
177
178			`variable cnt: std_logic_vector(6 downto 0):="0000000";`
179
180
181			`begin`
182			`if (reset='1') then`
183
184			`state <= "000001"; -- reset state`
185			`ready_d <= '0';`
186
187			`cnt :=(others=>'0');`
188
189			`A := (others=>'0');`
190			`B := (others=>'0');`
191			`C := (others=>'0');`
192			`D := (others=>'0');`
193			`ready_d <= '0';`
194			`TEMPA:=(others=>'0');`
195			`TEMPB:=(others=>'0');`
196			`TEMPC:=(others=>'0');`
197			`TEMPD:=(others=>'0');`
198			`temp_AD:= (others=>'0');`
199			`temp_BA:= (others=>'0');`
200			`temp_CB:= (others=>'0');`
201			`temp_DC:= (others=>'0');`
202
203
204			`elsif(clock'event and clock='1') then`
205
206			`case state is --synopsys parallel_case`
207			`when"000001"=>`
208
209			`if (start_d = '0') then`
210			`state <= "000001";`
211			`else`
212			`state <= "000010";`
213			`ready_d <= '1';`
214			`end if;`
215
216
217			`when "000010"=>`
218
219			`state <= "000011";`
220			`A := ciphertext;--read ciphertext into A`
221			`ready_d <= '0';`
222
223			`when "000011"=>`
224
225			`state <= "000100";`
226			`B := ciphertext; -- read ciphertext into B`
227			`ready_d <= '0';`
228
229
230			`when "000100"=>`
231
232			`state <= "000101";`
233			`C := ciphertext; -- read ciphertext into C`
234			`ready_d <= '0';`
235
236
237			`when "000101"=>`
238
239			`state <= "000110";`
240			`D := ciphertext;--assign ciphertext to D`
241			`A := A - s(42); -- Use round keys to calculate new value of A`
242			`C := C - s(43); -- read ciphertext - roundkeys into C`
243			`ready_d <= '0';`
244
245
246			`when "000110"=> -- begin calculation of plaintext loop from r downto 1`
247			`state <= "001000";`
248			`TEMPA:=A;`
249			`TEMPB:=B;`
250			`TEMPC:=C;`
251			`TEMPD:=D;`
252			`--swap the value of A, B ,C and D so that new value of A,B ,C AND D can be used.`
253			`temp_AD:= tempA xor tempD;`
254			`A:= temp_AD xor tempA;`
255
256			`temp_BA:= tempB xor tempA;`
257			`B:= temp_BA xor tempB;`
258
259			`temp_CB:= tempC xor tempB;`
260			`C:= temp_CB xor tempC;`
261
262			`temp_DC:= tempD xor tempC;`
263			`D:= temp_DC xor tempD;`
264
265			`ready_d <= '0';`
266
267
268			`when "001000"=>`
269
270			`STATE <="001001";`
271
272
273			`t_pre := product1;`
274
275
276			`u_pre := product2;`
277
278			`t:= t_pre(11 downto 0) & t_pre(15 downto 12);`
279			`ttemp1<=t;`
280
281
282			`u:= u_pre(11 downto 0)& u_pre(15 downto 12);`
283			`utemp1<=u;`
284
285			`ready_d <= '0';`
286
287
288
289			`when "001001"=>`
290
291			`state <= "001010";`
292
293			`for i in 1 to 20 loop`
294			`A_pre_2 := (A - s(2*i)); -- A = A-S[2i]`
295			`C_pre_2 := (C - s(2*i+1)); -- C = C - S[2i+1]`
296			`end loop ;`
297			`ready_d <= '0';`
298
299			`--sig3<=conv_integer(unsigned(u(3 downto 0)));`
300			`A_pre :=A_pre_2(sig3-1 downto 0) & A_pre_2(15 downto sig3);`
301
302			`A := (A_pre xor t); -- A = ((A-S[2i] >>>u) xor t`
303			`--sig4<=conv_integer(unsigned(t(3 downto 0)));`
304			`C_pre:=C_pre_2(sig4-1 downto 0)& C_pre_2(15 downto sig4);`
305
306			`C := (C_pre xor u); -- C = ((C-S[2i+1]>>>t) xor u`
307
308			`when "001010"=>`
309
310			`state <= "000001";`
311			`if(cnt<19 )then`
312			`cnt:=cnt+1 ;`
313			`state <="000110";`
314			`else`
315			`last_round <='1';`
316			`state<="001011";`
317			`cnt:="0000000" ;`
318			`end if;`
319
320
321
322
323
324			`when "001011"=>`
325
326			`state <= "001100";`
327			`D := D - s(1); -- Calculate final value of D`
328			`ready_d <= '0';`
329
330
331
332			`when "001100" =>`
333
334			`state <= "001101";`
335			`B := B - s(0); -- Calculate final value of B`
336			`ready_d <= '1'; -- set ready_d signal high as decryption process is over`
337
338			`cleanup<='1';`
339			`ready_d_pre <= '1';-- Assign ready_d_pre high which essentially starts up second FSM.`
340
341			`when "001101" =>`
342
343			`if(cleanup='1') then`
344			`A_final <= A;`
345			`B_final <= B;`
346			`C_final <= C;`
347			`D_final <= D;`
348			`else`
349			`A_final <= A_final ;`
350			`B_final <= B_final ;`
351			`C_final <= C_final ;`
352			`D_final <= D_final ;`
353			`end if;`
354
355
356			`when others=>`
357			`state <= "000001";`
358			`ready_d <= '1';`
359			`A := (others=>'0');`
360			`B := (others=>'0');`
361			`C := (others=>'0');`
362			`D := (others=>'0');`
363
364			`end case;`
365			`end if;`
366			`end process;`
367
368
369			`process(clock,reset,ready_d_pre,A_final,B_final,C_final,D_final)`
370			`begin`
371			`if (reset='1') then`
372
373			`state_out <= idle;`
374			`plaintext_d <= (others=>'0');`
375
376			`elsif (clock'event and clock='1') then`
377
378			`case state_out is --synopsys parallel_case`
379			`when idle=>`
380
381			`if (ready_d_pre='1') then`
382			`state_out <= out_A;`
383			`else`
384			`state_out <= idle;`
385			`plaintext_d <= (others=>'0');`
386			`end if;`
387			`when out_A=>`
388
389			`state_out <= out_B;`
390			`plaintext_d <= A_final; -- Output plaintext as A`
391
392
393			`when out_B=>`
394
395			`state_out <= out_C;`
396			`plaintext_d <= B_final; -- Output plaintext as B`
397
398			`when out_C=>`
399
400			`state_out <= out_D;`
401			`plaintext_d <= C_final; -- Output plaintext as C`
402
403			`when out_D=>`
404
405			`state_out <= idle;`
406			`plaintext_d <= D_final; -- Output plaintext as D`
407
408			`when others=>`
409
410			`state_out <= idle;`
411			`plaintext_d <= (others=>'0');`
412
413			`end case;`
414			`end if;`
415			`end process;`
416
417			`end arch_decryptor ;`
418
419
420
421
422
423
424