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[/] [cryptography/] [trunk/] [encryption/] [encry.vhd.bak] - Blame information for rev 4

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----------------------------------------------------------------------------------
-- Description:Implements the RC6 encryption algorithm.
--                                      Everything based on a positive edge of clock and
--                                      an asynchronous reset.
--
--                                      Module contains two finite state machines.
--
--                                      One fsm controls the calculation of the various
--                                      rounds. Another fsm is responsible for outputting
--                                      the ciphertext so the encryptor can accept plain
--                                      text while cipher text is still in the process of
--                                      going out.
--
--                                      We assume the number of rounds to be 20.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- encryptor module declaration
 
entity encryptor  is
 
port  (
         plaintext_e :in std_logic_vector(15 downto 0);-- 16 bit Plaintext output of decryptor
         round_keyse :in std_logic_vector(15 downto 0);--  16 bit roundkeys given to decryptor
              start_e:in std_logic;  --1 bit ready signal for encryptor
               reset :in std_logic;  --reset
               clock :in std_logic ; --clock
             ready_e :out std_logic; -- 1 bit ready output of decryptor
           ciphertext: out std_logic_vector(15 downto 0)-- 16 bit ciphertext input to decrytpor which is output of encryptor
 
       );
 
end  encryptor;
 
 
Architecture arch_encryptor of encryptor is
 
-------wallace tree
 
component multiplier
port( B  :in std_logic_vector(15 downto 0);
    Product :out std_logic_vector(15 downto 0)
    );
end component;
 
--------  constant for key generation.
 
constant p:std_logic_vector(15 downto 0):= "1011011111100001";------constant value p
constant q:std_logic_vector(15 downto 0):= "1001111000110111";------constant value q
 
type s_tp is array(43 downto 0) of std_logic_vector(15 downto 0);--array of 44 * 16
signal s :s_tp;
 
type l_tp is array(42 downto 0) of std_logic_vector(15 downto 0);--array of 43 *16
signal l :l_tp;
 
 
 
--------- constants for the plain text fsm
 
constant out_idle:std_logic_vector(3 downto 0):= "0000";
constant   out_A :std_logic_vector(3 downto 0):= "0001";
constant   out_B :std_logic_vector(3 downto 0):= "0010";
constant   out_C :std_logic_vector(3 downto 0):= "0011";
constant   out_D :std_logic_vector(3 downto 0):= "0100";
 
 
 
--------- signals needed for internal connections
 
signal cleanup_A,cleanup_C ,start_d1,last_round: std_logic;
signal next_state_out: std_logic_vector( 3 downto 0);
signal state:std_logic_vector(5 downto 0); --state of primary fsm
signal state_out:std_logic_vector(3 downto 0); -- state of plaintext fsm
signal utemp1,ttemp1:std_logic_vector(15 downto 0);
 
signal sig3,sig4:INTEGER RANGE 0 TO 15;
 
signal A_final,B_final,C_final,D_final:std_logic_vector(15 downto 0);
signal product1,product2  : std_logic_vector(15 downto 0);
 
begin
 
 sig3<=conv_integer(unsigned(utemp1(3 downto 0)));
 sig4<=conv_integer(unsigned(ttemp1(3 downto 0)));
                                --------key generation operation------
 
                                        s(0) <= P ; -- initialize constant array
                                        l(0)<=(round_keyse +s(0));
                                        s(1)<=(l(0)+ s(0)+ q);
                                        l(1)<=( l(0)+s(1));
                                        s(2)<=(l(1)+ s(1)+ q);
                                        l(2)<=( l(1)+s(2));
                                        s(3)<=(l(2)+ s(2)+ q);
                                        l(3)<=( l(2)+s(3));
                                        s(4)<=(l(3)+ s(3)+ q);
                                        l(4)<=( l(3)+s(4));
                                        s(5)<=(l(4)+ s(4)+ q);
                                        l(5)<=( l(4)+s(5));
                                        s(6)<=(l(5)+ s(5)+ q);
                                        l(6)<=( l(5)+s(6));
                                        s(7)<=(l(6)+ s(6)+ q);
                                        l(7)<=( l(6)+s(7));
                                        s(8)<=(l(7)+ s(7)+ q);
                                        l(8)<=( l(7)+s(8));
                                        s(9)<=(l(8)+s(8)+ q);
                                        l(9)<=( l(8)+s(9));
                                        s(10)<=(l(9)+s(9)+ q);
                                        l(10)<=( l(9)+s(10 ));
                                        s(11)<=(l(10)+s(10)+ q);
                                        l(11)<=( l(10)+s(11));
                                        s(12)<=(l(11)+ s(11)+ q);
                                        l(12)<=( l(11)+s(12));
                                        s(13)<=(l(12)+s(12)+ q);
                                        l(13)<=( l(12)+s(13));
                                        s(14)<=(l(13)+ s(13)+ q);
                                        l(14)<=( l(13)+s(14));
                                        s(15)<=(l(14)+ s(14)+ q);
                                        l(15)<=( l(14)+s(15));
                                        s(16)<=(l(15)+ s(15)+ q);
                                        l(16)<=( l(15)+s(16));
                                        s(17)<=(l(16)+ s(16)+ q);
                                        l(17)<=( l(16)+s(17));
                                        s(18)<=(l(17)+ s(17)+ q);
                                        l(18)<=( l(17)+s(18));
                                        s(19)<=(l(18)+ s(18)+ q);
                                        l(19)<=( l(18)+s(19));
                                        s(20)<=(l(19)+ s(19)+ q);
                                        l(20)<=( l(19)+s(20));
                                        s(21)<=(l(20)+ s(20)+ q);
                                        l(21)<=( l(20)+s(21));
                                        s(22)<=(l(21)+ s(21)+ q);
                                        l(22)<=( l(21)+s(22));
                                        s(23)<=(l(22)+ s(22)+ q);
                                        l(23)<=( l(22)+s(23));
                                        s(24)<=(l(23)+ s(23)+ q);
                                        l(24)<=( l(23)+s(24));
                                        s(25)<=(l(24)+ s(24)+ q);
                                        l(25)<=( l(24)+s(25));
                                        s(26)<=(l(25)+ s(25)+ q);
                                        l(26)<=( l(25)+s(26));
                                        s(27)<=(l(26)+ s(26)+ q);
                                        l(27)<=( l(26)+s(27));
                                        s(28)<=(l(27)+ s(27)+ q);
                                        l(28)<=( l(27)+s(28));
                                        s(29)<=(l(28)+ s(28)+ q);
                                        l(29)<=( l(23)+s(24));
                                        s(30)<=(l(29)+ s(29)+ q);
                                        l(30)<=( l(29)+s(30));
                                        s(31)<=(l(30)+ s(30)+ q);
                                        l(31)<=( l(30)+s(31));
                                        s(32)<=(l(31)+ s(31)+ q);
                                        l(32)<=( l(31)+s(32));
                                        s(33)<=(l(32)+ s(32)+ q);
                                        l(33)<=( l(32)+s(33));
                                        s(34)<=(l(33)+ s(33)+ q);
                                        l(34)<=( l(33)+s(34));
                                        s(35)<=(l(34)+ s(34)+ q);
                                        l(35)<=( l(34)+s(35));
                                        s(36)<=(l(35)+ s(35)+ q);
                                        l(36)<=( l(35)+s(36));
                                        s(37)<=(l(36)+ s(36)+ q);
                                        l(37)<=( l(36)+s(37));
                                        s(38)<=(l(37)+ s(37)+ q);
                                        l(38)<=( l(37)+s(38));
                                        s(39)<=(l(38)+ s(38)+ q);
                                        l(39)<=( l(33)+s(34));
                                        s(40)<=(l(39)+ s(39)+ q);
                                        l(40)<=( l(39)+s(40));
                                        s(40)<=(l(39)+ s(39)+ q);
                                        l(41)<=( l(40)+s(40));
                                        s(41)<=(l(40)+ s(40)+ q);
                                        l(42)<=( l(41)+s(41));
                                        s(42)<=(l(41)+ s(41)+ q);
                                        s(43)<=(l(42)+ s(42)+ q);
--------fsm for input --------
 
process(clock,reset,plaintext_e,sig3,sig4)
 
-----internal variable declaration
 
variable A,B,C,D,t_pre,u_pre:std_logic_vector(15 downto 0);
 
VARIABLE  t,u,A_temp2,C_temp2,A_temp1,C_temp1:std_logic_vector( 15 downto 0);
variable tempA,tempB,tempC,tempD :std_logic_vector(15 downto 0);
variable temp_AB,temp_BC,temp_CD,temp_DA :std_logic_vector(15 downto 0);
variable cnt: std_logic_vector(6 downto 0):="0000000";
 
begin
 
 
 
 
 
        if (reset='1') then
 
                state <= "000001"; -- reset state
                ready_e <= '0';
                cnt:=(others=>'0');
                A := (others=>'0');
                B := (others=>'0');
                C := (others=>'0');
                D := (others=>'0');
                ready_e <= '0';
 
        elsif(clock'event and clock='1') then
 
          case state is  --synopsys parallel_case
                when"000001"=>
 
                        if (start_e = '0') then
                                state <= "000001";
                        else
                                state <= "000010";
                        ready_e <= '1';
                        end if;
 
 
                when "000010"=>
 
                        state <= "000011";
                        A := plaintext_e;--read ciphertext into A
                        ready_e <= '0';
 
                when "000011"=>
 
                        state <= "000100";
                        B := plaintext_e; -- read ciphertext into B
                        ready_e <= '0';
 
 
                when "000100"=>
 
                        state <= "000101";
                        C := plaintext_e ; -- read ciphertext - into C
                        B := B+ s(0) ;-- Use round keys to calculate new value of B
                        ready_e<= '0';
 
 
                when "000101"=>
 
                        state <= "000110";
                        D :=  plaintext_e;--assign ciphertext to D
                        ready_e <= '0';
 
 
                when "000110"=>  -- begin calculation of plaintext loop from r downto 1
 
                        state<= "000111" ;
 
                       D := D + s(1); -- Use round keys to calculate new value of D
 
 
                        ready_e <='0';
 
                when "000111" =>
 
                        STATE <="001000";
 
                        --t= (B * (2B+1))
 
                        t_pre := product1;
 
 
                        --t= (D * (2D+1))
 
                        u_pre := product2;
 
                        t:= t_pre(11 downto 0)& t_pre(15 downto 12);
 
                                ttemp1<=t;
                                --t= (B * (2B+1)) <<<4
 
                  u:= u_pre(11 downto 0)& u_pre(15 downto 12);
 
                                utemp1<=u;
                                --u= (D * (2D+1)) <<<4
 
                        A_temp1 := (A xor t);
                        C_temp1 := (C xor u);
 
 
 
                 when "001000" =>
 
                  state <="001001" ;
 
 
 
 
 
                        A_temp2:=A_temp1(15-sig3 downto 0)& A_temp1(15 downto 15-sig3+1);
                                ---rotate (A xor t) << u
 
                        C_temp2:=C_temp1(15-sig4 downto 0)& C_temp1(15 downto 15-sig4+1);
                                ---rotate (c xor u) << t
 
 
                        for  i  in 1 to 20 loop
                                A := (A_temp2 + s(2*i));
                                C := (C_temp2 + s(2*i+1));
                        end loop;
 
 
                 when "001001"=>
                        state <="001010";
                                                -------swap operation---------
                                                        TEMPA:=A;
                                        TEMPB:=B;
                                        TEMPC:=C;
                                        TEMPD:=D;
 
                                        temp_AB:= tempA xor tempB;
                                        A:= temp_AB xor tempA;
 
                                        temp_BC:= tempB xor tempC;
                                        B:= temp_BC xor tempB;
 
                                        temp_CD:= tempC xor tempD;
                                        C:= temp_CD xor tempC;
 
                                        temp_DA:= tempD xor tempA;
                                        D:= temp_DA xor tempD;
 
                                                        ready_e <= '0';
 
                WHEN "001010" =>
                                  ------start counter------
                                        if(cnt<19)then
                                                cnt:=cnt+1      ;
                                                state <="000111";
                                        else
                                                state<="001011";
                                                cnt:="0000000" ;
                                                last_round <='1';
                                        end if;
 
 
 
                when "001011" =>
 
                        state <= "001100";
                  if (last_round ='1') then
                        -- calculate last A value
                        cleanup_A <= '1';
                        -- calculate last C value
                        cleanup_C <= '1';
                 else
                        cleanup_A <= '0';
                        cleanup_C <= '0';
                end if;
 
                when "001100" =>
 
                state <= "000001";
 
 
                --rounds are over
                --now do the cleanup
                if (cleanup_A='1') then
                        A_final <= A + s(42); --A_temp2 + round_keys_e_saved;
                        B_final <= B;--B_temp2;
                        D_final <= D;--D_temp2;
                else
                        A_final <= A_final;
                        B_final <= B_final;
                        D_final <= D_final;
                end if;
 
                if (cleanup_C='1') then
                        C_final <= C + s(43);
                        start_d1 <= '1';
                else
                        C_final <= C_final;
                        start_d1 <= '0';
                end if;
 
                when others =>
                                                state <="000001"        ;
 
   end case;
end if;
end process;
 
 
 
-- current state logic for output FSM
process(clock,reset )
begin
        -- if reset stay idle
        -- else output based on
        --state
        if (reset='1') then
                state_out <= out_idle;
        elsif(clock'event and clock='1') then
                state_out <= next_state_out;
        end if;
end process;
 
 
-- next state, output logic for output FSM
process(state_out,start_d1,A_final,B_final,C_final,D_final)
begin
                case state_out is --synopsys parallel_case
                when out_idle=>
 
                        -- wait for start_d
                        if (start_d1='1') then
                                next_state_out <= out_A;
                        else
                                next_state_out <= out_idle;
                                ciphertext <= (others=>'0');
                        end if;
                when out_A=>
 
                        next_state_out <= out_B;
                        -- output A
                        ciphertext <= A_final;----------ouput cipher text 1
 
                when out_B=>
 
                        next_state_out <= out_C;
                        -- output B
                        ciphertext <= B_final;----------ouput cipher text 2
 
                when out_C=>
 
                        next_state_out <= out_D;
                        -- output C
                        ciphertext <= C_final;----------ouput cipher text 3
 
                when out_D=>
 
                        next_state_out <= out_idle;
                        -- output D
                        ciphertext <= D_final;----------ouput cipher text 4
 
                when others=>
 
                        next_state_out <= out_idle;
                        ciphertext <= (others=>'0');
 
                end case;
 
-----------------------complete output come after 93 clock---------------------
 
end process;
end arch_encryptor ;

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[/] [cryptography/] [trunk/] [encryption/] [encry.vhd.bak] - Blame information for rev 4

Line No.	Rev	Author	Line
1	4	marcus.erl	`----------------------------------------------------------------------------------`
2			`-- Description:Implements the RC6 encryption algorithm.`
3			`-- Everything based on a positive edge of clock and`
4			`-- an asynchronous reset.`
5			`--`
6			`-- Module contains two finite state machines.`
7			`--`
8			`-- One fsm controls the calculation of the various`
9			`-- rounds. Another fsm is responsible for outputting`
10			`-- the ciphertext so the encryptor can accept plain`
11			`-- text while cipher text is still in the process of`
12			`-- going out.`
13			`--`
14			`-- We assume the number of rounds to be 20.`
15			`----------------------------------------------------------------------------------`
16			`library IEEE;`
17			`use IEEE.STD_LOGIC_1164.ALL;`
18			`use IEEE.STD_LOGIC_ARITH.ALL;`
19			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
20
21			`-- encryptor module declaration`
22
23			`entity encryptor is`
24
25			`port (`
26			`plaintext_e :in std_logic_vector(15 downto 0);-- 16 bit Plaintext output of decryptor`
27			`round_keyse :in std_logic_vector(15 downto 0);-- 16 bit roundkeys given to decryptor`
28			`start_e:in std_logic; --1 bit ready signal for encryptor`
29			`reset :in std_logic; --reset`
30			`clock :in std_logic ; --clock`
31			`ready_e :out std_logic; -- 1 bit ready output of decryptor`
32			`ciphertext: out std_logic_vector(15 downto 0)-- 16 bit ciphertext input to decrytpor which is output of encryptor`
33
34			`);`
35
36			`end encryptor;`
37
38
39			`Architecture arch_encryptor of encryptor is`
40
41			`-------wallace tree`
42
43			`component multiplier`
44			`port( B :in std_logic_vector(15 downto 0);`
45			`Product :out std_logic_vector(15 downto 0)`
46			`);`
47			`end component;`
48
49			`-------- constant for key generation.`
50
51			`constant p:std_logic_vector(15 downto 0):= "1011011111100001";------constant value p`
52			`constant q:std_logic_vector(15 downto 0):= "1001111000110111";------constant value q`
53
54			`type s_tp is array(43 downto 0) of std_logic_vector(15 downto 0);--array of 44 * 16`
55			`signal s :s_tp;`
56
57			`type l_tp is array(42 downto 0) of std_logic_vector(15 downto 0);--array of 43 *16`
58			`signal l :l_tp;`
59
60
61
62			`--------- constants for the plain text fsm`
63
64			`constant out_idle:std_logic_vector(3 downto 0):= "0000";`
65			`constant out_A :std_logic_vector(3 downto 0):= "0001";`
66			`constant out_B :std_logic_vector(3 downto 0):= "0010";`
67			`constant out_C :std_logic_vector(3 downto 0):= "0011";`
68			`constant out_D :std_logic_vector(3 downto 0):= "0100";`
69
70
71
72			`--------- signals needed for internal connections`
73
74			`signal cleanup_A,cleanup_C ,start_d1,last_round: std_logic;`
75			`signal next_state_out: std_logic_vector( 3 downto 0);`
76			`signal state:std_logic_vector(5 downto 0); --state of primary fsm`
77			`signal state_out:std_logic_vector(3 downto 0); -- state of plaintext fsm`
78			`signal utemp1,ttemp1:std_logic_vector(15 downto 0);`
79
80			`signal sig3,sig4:INTEGER RANGE 0 TO 15;`
81
82			`signal A_final,B_final,C_final,D_final:std_logic_vector(15 downto 0);`
83			`signal product1,product2 : std_logic_vector(15 downto 0);`
84
85			`begin`
86
87			`sig3<=conv_integer(unsigned(utemp1(3 downto 0)));`
88			`sig4<=conv_integer(unsigned(ttemp1(3 downto 0)));`
89			`--------key generation operation------`
90
91			`s(0) <= P ; -- initialize constant array`
92			`l(0)<=(round_keyse +s(0));`
93			`s(1)<=(l(0)+ s(0)+ q);`
94			`l(1)<=( l(0)+s(1));`
95			`s(2)<=(l(1)+ s(1)+ q);`
96			`l(2)<=( l(1)+s(2));`
97			`s(3)<=(l(2)+ s(2)+ q);`
98			`l(3)<=( l(2)+s(3));`
99			`s(4)<=(l(3)+ s(3)+ q);`
100			`l(4)<=( l(3)+s(4));`
101			`s(5)<=(l(4)+ s(4)+ q);`
102			`l(5)<=( l(4)+s(5));`
103			`s(6)<=(l(5)+ s(5)+ q);`
104			`l(6)<=( l(5)+s(6));`
105			`s(7)<=(l(6)+ s(6)+ q);`
106			`l(7)<=( l(6)+s(7));`
107			`s(8)<=(l(7)+ s(7)+ q);`
108			`l(8)<=( l(7)+s(8));`
109			`s(9)<=(l(8)+s(8)+ q);`
110			`l(9)<=( l(8)+s(9));`
111			`s(10)<=(l(9)+s(9)+ q);`
112			`l(10)<=( l(9)+s(10 ));`
113			`s(11)<=(l(10)+s(10)+ q);`
114			`l(11)<=( l(10)+s(11));`
115			`s(12)<=(l(11)+ s(11)+ q);`
116			`l(12)<=( l(11)+s(12));`
117			`s(13)<=(l(12)+s(12)+ q);`
118			`l(13)<=( l(12)+s(13));`
119			`s(14)<=(l(13)+ s(13)+ q);`
120			`l(14)<=( l(13)+s(14));`
121			`s(15)<=(l(14)+ s(14)+ q);`
122			`l(15)<=( l(14)+s(15));`
123			`s(16)<=(l(15)+ s(15)+ q);`
124			`l(16)<=( l(15)+s(16));`
125			`s(17)<=(l(16)+ s(16)+ q);`
126			`l(17)<=( l(16)+s(17));`
127			`s(18)<=(l(17)+ s(17)+ q);`
128			`l(18)<=( l(17)+s(18));`
129			`s(19)<=(l(18)+ s(18)+ q);`
130			`l(19)<=( l(18)+s(19));`
131			`s(20)<=(l(19)+ s(19)+ q);`
132			`l(20)<=( l(19)+s(20));`
133			`s(21)<=(l(20)+ s(20)+ q);`
134			`l(21)<=( l(20)+s(21));`
135			`s(22)<=(l(21)+ s(21)+ q);`
136			`l(22)<=( l(21)+s(22));`
137			`s(23)<=(l(22)+ s(22)+ q);`
138			`l(23)<=( l(22)+s(23));`
139			`s(24)<=(l(23)+ s(23)+ q);`
140			`l(24)<=( l(23)+s(24));`
141			`s(25)<=(l(24)+ s(24)+ q);`
142			`l(25)<=( l(24)+s(25));`
143			`s(26)<=(l(25)+ s(25)+ q);`
144			`l(26)<=( l(25)+s(26));`
145			`s(27)<=(l(26)+ s(26)+ q);`
146			`l(27)<=( l(26)+s(27));`
147			`s(28)<=(l(27)+ s(27)+ q);`
148			`l(28)<=( l(27)+s(28));`
149			`s(29)<=(l(28)+ s(28)+ q);`
150			`l(29)<=( l(23)+s(24));`
151			`s(30)<=(l(29)+ s(29)+ q);`
152			`l(30)<=( l(29)+s(30));`
153			`s(31)<=(l(30)+ s(30)+ q);`
154			`l(31)<=( l(30)+s(31));`
155			`s(32)<=(l(31)+ s(31)+ q);`
156			`l(32)<=( l(31)+s(32));`
157			`s(33)<=(l(32)+ s(32)+ q);`
158			`l(33)<=( l(32)+s(33));`
159			`s(34)<=(l(33)+ s(33)+ q);`
160			`l(34)<=( l(33)+s(34));`
161			`s(35)<=(l(34)+ s(34)+ q);`
162			`l(35)<=( l(34)+s(35));`
163			`s(36)<=(l(35)+ s(35)+ q);`
164			`l(36)<=( l(35)+s(36));`
165			`s(37)<=(l(36)+ s(36)+ q);`
166			`l(37)<=( l(36)+s(37));`
167			`s(38)<=(l(37)+ s(37)+ q);`
168			`l(38)<=( l(37)+s(38));`
169			`s(39)<=(l(38)+ s(38)+ q);`
170			`l(39)<=( l(33)+s(34));`
171			`s(40)<=(l(39)+ s(39)+ q);`
172			`l(40)<=( l(39)+s(40));`
173			`s(40)<=(l(39)+ s(39)+ q);`
174			`l(41)<=( l(40)+s(40));`
175			`s(41)<=(l(40)+ s(40)+ q);`
176			`l(42)<=( l(41)+s(41));`
177			`s(42)<=(l(41)+ s(41)+ q);`
178			`s(43)<=(l(42)+ s(42)+ q);`
179			`--------fsm for input --------`
180
181			`process(clock,reset,plaintext_e,sig3,sig4)`
182
183			`-----internal variable declaration`
184
185			`variable A,B,C,D,t_pre,u_pre:std_logic_vector(15 downto 0);`
186
187			`VARIABLE t,u,A_temp2,C_temp2,A_temp1,C_temp1:std_logic_vector( 15 downto 0);`
188			`variable tempA,tempB,tempC,tempD :std_logic_vector(15 downto 0);`
189			`variable temp_AB,temp_BC,temp_CD,temp_DA :std_logic_vector(15 downto 0);`
190			`variable cnt: std_logic_vector(6 downto 0):="0000000";`
191
192			`begin`
193
194
195
196
197
198			`if (reset='1') then`
199
200			`state <= "000001"; -- reset state`
201			`ready_e <= '0';`
202			`cnt:=(others=>'0');`
203			`A := (others=>'0');`
204			`B := (others=>'0');`
205			`C := (others=>'0');`
206			`D := (others=>'0');`
207			`ready_e <= '0';`
208
209			`elsif(clock'event and clock='1') then`
210
211			`case state is --synopsys parallel_case`
212			`when"000001"=>`
213
214			`if (start_e = '0') then`
215			`state <= "000001";`
216			`else`
217			`state <= "000010";`
218			`ready_e <= '1';`
219			`end if;`
220
221
222			`when "000010"=>`
223
224			`state <= "000011";`
225			`A := plaintext_e;--read ciphertext into A`
226			`ready_e <= '0';`
227
228			`when "000011"=>`
229
230			`state <= "000100";`
231			`B := plaintext_e; -- read ciphertext into B`
232			`ready_e <= '0';`
233
234
235			`when "000100"=>`
236
237			`state <= "000101";`
238			`C := plaintext_e ; -- read ciphertext - into C`
239			`B := B+ s(0) ;-- Use round keys to calculate new value of B`
240			`ready_e<= '0';`
241
242
243			`when "000101"=>`
244
245			`state <= "000110";`
246			`D := plaintext_e;--assign ciphertext to D`
247			`ready_e <= '0';`
248
249
250			`when "000110"=> -- begin calculation of plaintext loop from r downto 1`
251
252			`state<= "000111" ;`
253
254			`D := D + s(1); -- Use round keys to calculate new value of D`
255
256
257			`ready_e <='0';`
258
259			`when "000111" =>`
260
261			`STATE <="001000";`
262
263			`--t= (B * (2B+1))`
264
265			`t_pre := product1;`
266
267
268			`--t= (D * (2D+1))`
269
270			`u_pre := product2;`
271
272			`t:= t_pre(11 downto 0)& t_pre(15 downto 12);`
273
274			`ttemp1<=t;`
275			`--t= (B * (2B+1)) <<<4`
276
277			`u:= u_pre(11 downto 0)& u_pre(15 downto 12);`
278
279			`utemp1<=u;`
280			`--u= (D * (2D+1)) <<<4`
281
282			`A_temp1 := (A xor t);`
283			`C_temp1 := (C xor u);`
284
285
286
287			`when "001000" =>`
288
289			`state <="001001" ;`
290
291
292
293
294
295			`A_temp2:=A_temp1(15-sig3 downto 0)& A_temp1(15 downto 15-sig3+1);`
296			`---rotate (A xor t) << u`
297
298			`C_temp2:=C_temp1(15-sig4 downto 0)& C_temp1(15 downto 15-sig4+1);`
299			`---rotate (c xor u) << t`
300
301
302			`for i in 1 to 20 loop`
303			`A := (A_temp2 + s(2*i));`
304			`C := (C_temp2 + s(2*i+1));`
305			`end loop;`
306
307
308			`when "001001"=>`
309			`state <="001010";`
310			`-------swap operation---------`
311			`TEMPA:=A;`
312			`TEMPB:=B;`
313			`TEMPC:=C;`
314			`TEMPD:=D;`
315
316			`temp_AB:= tempA xor tempB;`
317			`A:= temp_AB xor tempA;`
318
319			`temp_BC:= tempB xor tempC;`
320			`B:= temp_BC xor tempB;`
321
322			`temp_CD:= tempC xor tempD;`
323			`C:= temp_CD xor tempC;`
324
325			`temp_DA:= tempD xor tempA;`
326			`D:= temp_DA xor tempD;`
327
328			`ready_e <= '0';`
329
330			`WHEN "001010" =>`
331			`------start counter------`
332			`if(cnt<19)then`
333			`cnt:=cnt+1 ;`
334			`state <="000111";`
335			`else`
336			`state<="001011";`
337			`cnt:="0000000" ;`
338			`last_round <='1';`
339			`end if;`
340
341
342
343			`when "001011" =>`
344
345			`state <= "001100";`
346			`if (last_round ='1') then`
347			`-- calculate last A value`
348			`cleanup_A <= '1';`
349			`-- calculate last C value`
350			`cleanup_C <= '1';`
351			`else`
352			`cleanup_A <= '0';`
353			`cleanup_C <= '0';`
354			`end if;`
355
356			`when "001100" =>`
357
358			`state <= "000001";`
359
360
361			`--rounds are over`
362			`--now do the cleanup`
363			`if (cleanup_A='1') then`
364			`A_final <= A + s(42); --A_temp2 + round_keys_e_saved;`
365			`B_final <= B;--B_temp2;`
366			`D_final <= D;--D_temp2;`
367			`else`
368			`A_final <= A_final;`
369			`B_final <= B_final;`
370			`D_final <= D_final;`
371			`end if;`
372
373			`if (cleanup_C='1') then`
374			`C_final <= C + s(43);`
375			`start_d1 <= '1';`
376			`else`
377			`C_final <= C_final;`
378			`start_d1 <= '0';`
379			`end if;`
380
381			`when others =>`
382			`state <="000001" ;`
383
384			`end case;`
385			`end if;`
386			`end process;`
387
388
389
390			`-- current state logic for output FSM`
391			`process(clock,reset )`
392			`begin`
393			`-- if reset stay idle`
394			`-- else output based on`
395			`--state`
396			`if (reset='1') then`
397			`state_out <= out_idle;`
398			`elsif(clock'event and clock='1') then`
399			`state_out <= next_state_out;`
400			`end if;`
401			`end process;`
402
403
404			`-- next state, output logic for output FSM`
405			`process(state_out,start_d1,A_final,B_final,C_final,D_final)`
406			`begin`
407			`case state_out is --synopsys parallel_case`
408			`when out_idle=>`
409
410			`-- wait for start_d`
411			`if (start_d1='1') then`
412			`next_state_out <= out_A;`
413			`else`
414			`next_state_out <= out_idle;`
415			`ciphertext <= (others=>'0');`
416			`end if;`
417			`when out_A=>`
418
419			`next_state_out <= out_B;`
420			`-- output A`
421			`ciphertext <= A_final;----------ouput cipher text 1`
422
423			`when out_B=>`
424
425			`next_state_out <= out_C;`
426			`-- output B`
427			`ciphertext <= B_final;----------ouput cipher text 2`
428
429			`when out_C=>`
430
431			`next_state_out <= out_D;`
432			`-- output C`
433			`ciphertext <= C_final;----------ouput cipher text 3`
434
435			`when out_D=>`
436
437			`next_state_out <= out_idle;`
438			`-- output D`
439			`ciphertext <= D_final;----------ouput cipher text 4`
440
441			`when others=>`
442
443			`next_state_out <= out_idle;`
444			`ciphertext <= (others=>'0');`
445
446			`end case;`
447
448			`-----------------------complete output come after 93 clock---------------------`
449
450			`end process;`
451			`end arch_encryptor ;`