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<b><font size=+2 face="Helvetica, Arial" color=#bf0000>Project Name: Discrete Cosine Transformer</font></b>
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<h3>Description</h3>
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<p class=MsoBodyText style='text-indent:.5in'>Recent advances in communications
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and networking technologies have made it possible that many applications use
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digital videos such as teleconferencing and multimedia communications. These
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applications require a very large bit-rate if being handled without
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compression. Most video compression standards such as HDTV, H.261, JPEG and
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MPEG use Discrete Cosine Transform (DCT) as a standard transform-coding scheme.<span
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style='mso-bidi-font-size:10.0pt;mso-bidi-font-family:Arial'><o:p></o:p></span></p>
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<p class=MsoBodyText style='text-indent:.5in'>Discrete Cosine Transform is decomposing the signal
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into weighted sums of cosine harmonics; unlike DCT, Discrete Fourier Transform
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decomposes the signal into weighted sums of orthogonal sines and cosines that
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when added together reproduce the original signal.</p>
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<p class=MsoBodyTextIndent style='text-indent:.5in'><span style='mso-bidi-font-size:
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10.0pt;mso-bidi-font-family:Arial'>FreeDCT-L
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is a low power architecture 1-Dimensional 8-point DCT/IDCT core that occupies
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minimal area for systems that do not require high-speed operation (e.g. Still
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Image Compression in digital cameras, Audio compression applications). The
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core’s operating resolution can be easily controlled. The main goal of
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designing the core was to minimize the size and power consumption. It uses
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about 3000 gates when implemented on FPGAs. After implementing the design using
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Alliance Series software for Xilinx XC4000E FPGA family, timing simulation
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results showed that the core can operate at a speed of 29 MHz. When
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implementing the design on ASIC 0.8-micron technology, timing simulation showed
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that the core will operate at a maximum frequency of 51 MHz. The core occupied
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an area of 1.1 mm<sup>2</sup> and contains 11,162 transistors.<o:p></o:p></span></p>
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<p class=MsoBodyTextIndent style='text-indent:.5in'><span style='mso-bidi-font-size:
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10.0pt;mso-bidi-font-family:Arial'>FreeDCT-M
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is a moderate speed 1-Dimensional IDCT core. It processes 12-bit words at a
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rate of 1 bit per clock cycle. The core will be suitable for MPEG
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decoding/encoding at the MP@ML</a> ( Main Profile / Main
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Level). The VHDL core associated with detailed explanation and documentation
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will be released later.<o:p></o:p></span></p>
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<h4>Current Status</h4>
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<p>Both cores associated with
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documentation are packed <a
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href="http://www.opencores.org/cores/dct/dct.zip">here</a> in a ZIP
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file, please feel free to send your opinions or suggestions regarding my work<o:p></o:p></span></p>
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<p><h4>Maintainer and Author</h4></p>
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<p>Sherif
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Taher Eid<span style="mso-spacerun: yes"> </span><o:p></o:p></span></p>
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<p>
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<a href="mailto:sherif_taher@ieee.org">sherif_taher@ieee.org</a><o:p></o:p></span></p>
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