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[/] [de1_olpcl2294_system/] [trunk/] [sim/] [models/] [wb_slave_model.v] - Blame information for rev 10

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1 10 qaztronic
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
27 7 qaztronic
 
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`timescale 1ns/10ps
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module wb_slave_model(  clk_i, rst_i, dat_o, dat_i, adr_i,
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                        cyc_i, stb_i, we_i, sel_i,
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                        ack_o, err_o, rty_o );
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  parameter DWIDTH    = 8;
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  parameter AWIDTH    = 8;
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  parameter ACK_DELAY = 2;
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  parameter SLAVE_RAM_INIT = "wb_slave_model.txt";
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  input                         clk_i;
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  input                         rst_i;
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  output [DWIDTH-1:0]           dat_o;
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  input  [DWIDTH-1:0]           dat_i;
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  input  [AWIDTH-1:0]           adr_i;
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  input                         cyc_i;
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  input                         stb_i;
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  input                         we_i;
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  input  [( (DWIDTH/8) - 1 ):0] sel_i;
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  output                        ack_o;
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  output                        err_o;
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  output                        rty_o;
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  // --------------------------------------------------------------------
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  //  slave ram
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  reg [7:0] ram[2**AWIDTH-1:0];
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  initial
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    $readmemh( SLAVE_RAM_INIT, ram );
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  // --------------------------------------------------------------------
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  //  
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  generate
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    case( DWIDTH )
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      8:        begin
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                  initial
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                    $display( "###- wb_slave_model(): WISHBONE 8 BIT SLAVE MODEL INSTANTIATED " );
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                  always @ (posedge clk_i)
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                    if (we_i & cyc_i & stb_i & sel_i[0])
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                      ram[adr_i] <= dat_i[7:0];
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                  assign dat_o = ram[adr_i];
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                end
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      16:       begin
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                  initial
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                    $display( "###- wb_slave_model(): WISHBONE 16 BIT SLAVE MODEL INSTANTIATED " );
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                  always @ (posedge clk_i)
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                    if (we_i & cyc_i & stb_i & sel_i[0])
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                      ram[{adr_i[AWIDTH-1:1], 1'b0}] <= dat_i[7:0];
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                  always @ (posedge clk_i)
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                    if (we_i & cyc_i & stb_i & sel_i[1])
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                      ram[{adr_i[AWIDTH-1:1], 1'b1}] <= dat_i[15:8];
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                  assign dat_o = { ram[{adr_i[AWIDTH-1:1], 1'b1}], ram[{adr_i[AWIDTH-1:1], 1'b0}] };
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                end
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      32:       begin
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                  initial
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                    $display( "###- wb_slave_model(): WISHBONE 32 BIT SLAVE MODEL INSTANTIATED " );
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                  always @ (posedge clk_i)
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                    if (we_i & cyc_i & stb_i & sel_i[0])
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                      ram[{adr_i[AWIDTH-1:2], 2'b00}] <= dat_i[7:0];
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                  always @ (posedge clk_i)
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                    if (we_i & cyc_i & stb_i & sel_i[1])
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                      ram[{adr_i[AWIDTH-1:2], 2'b01}] <= dat_i[15:8];
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                  always @ (posedge clk_i)
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                    if (we_i & cyc_i & stb_i & sel_i[2])
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                      ram[{adr_i[AWIDTH-1:2], 2'b10}] <= dat_i[23:16];
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                  always @ (posedge clk_i)
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                    if (we_i & cyc_i & stb_i & sel_i[3])
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                      ram[{adr_i[AWIDTH-1:2], 2'b11}] <= dat_i[31:24];
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                  assign dat_o = { ram[{adr_i[AWIDTH-1:2], 2'b11}], ram[{adr_i[AWIDTH-1:2], 2'b10}], ram[{adr_i[AWIDTH-1:2], 2'b01}], ram[{adr_i[AWIDTH-1:2], 2'b00}] };
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                end
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      default:  begin
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                  localparam SLAVE_SIZE = -1;
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                  initial
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                    begin
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                      $display( "!!!- wb_slave_model(): invalad DWIDTH parameter" );
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                      $stop();
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                    end
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                end
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    endcase
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  endgenerate
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  // --------------------------------------------------------------------
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  //  ack delay
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  reg ack_delayed;
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  initial
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    ack_delayed = 1'b0;
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  always @(posedge clk_i or cyc_i or stb_i)
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    begin
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      if(cyc_i & stb_i)
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        begin
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          ack_delayed = 1'b0;
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          repeat(ACK_DELAY) @(posedge clk_i);
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          if(cyc_i & stb_i)
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            ack_delayed = 1'b1;
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          else
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            ack_delayed = 1'b0;
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        end
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      else
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        ack_delayed = 1'b0;
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    end
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  // --------------------------------------------------------------------
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  //  assign outputs  
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  assign ack_o = ack_delayed;
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  assign err_o = 1'b0;
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  assign rty_o = 1'b0;
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161 2 qaztronic
endmodule

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