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URL https://opencores.org/ocsvn/de1_olpcl2294_system/de1_olpcl2294_system/trunk

Subversion Repositories de1_olpcl2294_system

[/] [de1_olpcl2294_system/] [trunk/] [sim/] [tests/] [debug/] [debug.mpf] - Blame information for rev 10

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Line No. Rev Author Line
1 8 qaztronic
; Copyright 1991-2009 Mentor Graphics Corporation
2 2 qaztronic
;
3
; All Rights Reserved.
4
;
5
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
6
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
7
;
8
 
9
[Library]
10
std = $MODEL_TECH/../std
11
ieee = $MODEL_TECH/../ieee
12
verilog = $MODEL_TECH/../verilog
13
vital2000 = $MODEL_TECH/../vital2000
14
std_developerskit = $MODEL_TECH/../std_developerskit
15
synopsys = $MODEL_TECH/../synopsys
16
modelsim_lib = $MODEL_TECH/../modelsim_lib
17
sv_std = $MODEL_TECH/../sv_std
18
 
19 8 qaztronic
; Altera Primitive libraries
20
;
21
; VHDL Section
22
;
23
altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf
24
altera = $MODEL_TECH/../altera/vhdl/altera
25
lpm = $MODEL_TECH/../altera/vhdl/220model
26
220model = $MODEL_TECH/../altera/vhdl/220model
27
max = $MODEL_TECH/../altera/vhdl/max
28
maxii = $MODEL_TECH/../altera/vhdl/maxii
29
stratix = $MODEL_TECH/../altera/vhdl/stratix
30
stratixii = $MODEL_TECH/../altera/vhdl/stratixii
31
stratixiigx = $MODEL_TECH/../altera/vhdl/stratixiigx
32
hardcopyii = $MODEL_TECH/../altera/vhdl/hardcopyii
33
hardcopyiii = $MODEL_TECH/../altera/vhdl/hardcopyiii
34
hardcopyiv = $MODEL_TECH/../altera/vhdl/hardcopyiv
35
cyclone = $MODEL_TECH/../altera/vhdl/cyclone
36
cycloneii = $MODEL_TECH/../altera/vhdl/cycloneii
37
cycloneiii = $MODEL_TECH/../altera/vhdl/cycloneiii
38
cycloneiiils = $MODEL_TECH/../altera/vhdl/cycloneiiils
39
sgate = $MODEL_TECH/../altera/vhdl/sgate
40
stratixgx = $MODEL_TECH/../altera/vhdl/stratixgx
41
altgxb = $MODEL_TECH/../altera/vhdl/altgxb
42
stratixgx_gxb = $MODEL_TECH/../altera/vhdl/stratixgx_gxb
43
stratixiigx_hssi = $MODEL_TECH/../altera/vhdl/stratixiigx_hssi
44
arriagx_hssi = $MODEL_TECH/../altera/vhdl/arriagx_hssi
45
arriaii = $MODEL_TECH/../altera/vhdl/arriaii
46
arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi
47
arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip
48
arriagx = $MODEL_TECH/../altera/vhdl/arriagx
49
altgxb_lib = $MODEL_TECH/../altera/vhdl/altgxb
50
stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv
51
stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi
52
stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip
53
cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv
54
cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi
55
cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip
56
hardcopyiv_hssi = $MODEL_TECH/../altera/vhdl/hardcopyiv_hssi
57
hardcopyiv_pcie_hip = $MODEL_TECH/../altera/vhdl/hardcopyiv_pcie_hip
58
;
59
; Verilog Section
60
;
61
altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf
62
altera_ver = $MODEL_TECH/../altera/verilog/altera
63
lpm_ver = $MODEL_TECH/../altera/verilog/220model
64
220model_ver = $MODEL_TECH/../altera/verilog/220model
65
max_ver = $MODEL_TECH/../altera/verilog/max
66
maxii_ver = $MODEL_TECH/../altera/verilog/maxii
67
stratix_ver = $MODEL_TECH/../altera/verilog/stratix
68
stratixii_ver = $MODEL_TECH/../altera/verilog/stratixii
69
stratixiigx_ver = $MODEL_TECH/../altera/verilog/stratixiigx
70
arriagx_ver = $MODEL_TECH/../altera/verilog/arriagx
71
hardcopyii_ver = $MODEL_TECH/../altera/verilog/hardcopyii
72
hardcopyiii_ver = $MODEL_TECH/../altera/verilog/hardcopyiii
73
hardcopyiv_ver = $MODEL_TECH/../altera/verilog/hardcopyiv
74
cyclone_ver = $MODEL_TECH/../altera/verilog/cyclone
75
cycloneii_ver = $MODEL_TECH/../altera/verilog/cycloneii
76
cycloneiii_ver = $MODEL_TECH/../altera/verilog/cycloneiii
77
cycloneiiils_ver = $MODEL_TECH/../altera/verilog/cycloneiiils
78
sgate_ver = $MODEL_TECH/../altera/verilog/sgate
79
stratixgx_ver = $MODEL_TECH/../altera/verilog/stratixgx
80
altgxb_ver = $MODEL_TECH/../altera/verilog/altgxb
81
stratixgx_gxb_ver = $MODEL_TECH/../altera/verilog/stratixgx_gxb
82
stratixiigx_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiigx_hssi
83
arriagx_hssi_ver = $MODEL_TECH/../altera/verilog/arriagx_hssi
84
arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii
85
arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi
86
arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip
87
stratixiii_ver = $MODEL_TECH/../altera/verilog/stratixiii
88
stratixiii = $MODEL_TECH/../altera/vhdl/stratixiii
89
stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv
90
stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi
91
stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip
92
cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv
93
cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi
94
cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip
95
hardcopyiv_hssi_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_hssi
96
hardcopyiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_pcie_hip
97
 
98 2 qaztronic
work = work
99 10 qaztronic
sim = C:/qaz/_CVS_WORK/units/de1_olpcl2294_system/libs/sim
100 2 qaztronic
[vcom]
101
; VHDL93 variable selects language version as the default.
102
; Default is VHDL-2002.
103
; Value of 0 or 1987 for VHDL-1987.
104
; Value of 1 or 1993 for VHDL-1993.
105
; Default or value of 2 or 2002 for VHDL-2002.
106
VHDL93 = 2002
107
 
108
; Show source line containing error. Default is off.
109
; Show_source = 1
110
 
111
; Turn off unbound-component warnings. Default is on.
112
; Show_Warning1 = 0
113
 
114
; Turn off process-without-a-wait-statement warnings. Default is on.
115
; Show_Warning2 = 0
116
 
117
; Turn off null-range warnings. Default is on.
118
; Show_Warning3 = 0
119
 
120
; Turn off no-space-in-time-literal warnings. Default is on.
121
; Show_Warning4 = 0
122
 
123
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
124
; Show_Warning5 = 0
125
 
126
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
127
; Optimize_1164 = 0
128
 
129
; Turn on resolving of ambiguous function overloading in favor of the
130
; "explicit" function declaration (not the one automatically created by
131
; the compiler for each type declaration). Default is off.
132
; The .ini file has Explicit enabled so that std_logic_signed/unsigned
133
; will match the behavior of synthesis tools.
134
Explicit = 1
135
 
136
; Turn off acceleration of the VITAL packages. Default is to accelerate.
137
; NoVital = 1
138
 
139
; Turn off VITAL compliance checking. Default is checking on.
140
; NoVitalCheck = 1
141
 
142
; Ignore VITAL compliance checking errors. Default is to not ignore.
143
; IgnoreVitalErrors = 1
144
 
145
; Turn off VITAL compliance checking warnings. Default is to show warnings.
146
; Show_VitalChecksWarnings = 0
147
 
148
; Keep silent about case statement static warnings.
149
; Default is to give a warning.
150
; NoCaseStaticError = 1
151
 
152
; Keep silent about warnings caused by aggregates that are not locally static.
153
; Default is to give a warning.
154
; NoOthersStaticError = 1
155
 
156
; Turn off inclusion of debugging info within design units.
157
; Default is to include debugging info.
158
; NoDebug = 1
159
 
160
; Turn off "Loading..." messages. Default is messages on.
161
; Quiet = 1
162
 
163
; Turn on some limited synthesis rule compliance checking. Checks only:
164
;    -- signals used (read) by a process must be in the sensitivity list
165
; CheckSynthesis = 1
166
 
167
; Activate optimizations on expressions that do not involve signals,
168
; waits, or function/procedure/task invocations. Default is off.
169
; ScalarOpts = 1
170
 
171
; Require the user to specify a configuration for all bindings,
172
; and do not generate a compile time default binding for the
173
; component. This will result in an elaboration error of
174
; 'component not bound' if the user fails to do so. Avoids the rare
175
; issue of a false dependency upon the unused default binding.
176
; RequireConfigForAllDefaultBinding = 1
177
 
178
; Inhibit range checking on subscripts of arrays. Range checking on
179
; scalars defined with subtypes is inhibited by default.
180
; NoIndexCheck = 1
181
 
182
; Inhibit range checks on all (implicit and explicit) assignments to
183
; scalar objects defined with subtypes.
184
; NoRangeCheck = 1
185
 
186 8 qaztronic
[vlog]
187 2 qaztronic
 
188
; Turn off inclusion of debugging info within design units.
189
; Default is to include debugging info.
190
; NoDebug = 1
191
 
192 8 qaztronic
; Turn off "loading..." messages. Default is messages on.
193 2 qaztronic
; Quiet = 1
194
 
195
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
196
; Default is off.
197
; Hazard = 1
198
 
199
; Turn on converting regular Verilog identifiers to uppercase. Allows case
200
; insensitivity for module names. Default is no conversion.
201
; UpCase = 1
202
 
203 8 qaztronic
; Turn on incremental compilation of modules. Default is off.
204
; Incremental = 1
205 2 qaztronic
 
206
; Turns on lint-style checking.
207
; Show_Lint = 1
208
 
209
[vsim]
210
; Simulator resolution
211
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
212 10 qaztronic
resolution = 1ps
213 2 qaztronic
 
214
; User time unit for run commands
215
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
216
; unit specified for Resolution. For example, if Resolution is 100ps,
217
; then UserTimeUnit defaults to ps.
218
; Should generally be set to default.
219
UserTimeUnit = default
220
 
221
; Default run length
222 10 qaztronic
RunLength = 40 us
223 2 qaztronic
 
224
; Maximum iterations that can be run without advancing simulation time
225
IterationLimit = 5000
226
 
227 8 qaztronic
; Directive to license manager:
228 2 qaztronic
; vhdl          Immediately reserve a VHDL license
229
; vlog          Immediately reserve a Verilog license
230
; plus          Immediately reserve a VHDL and Verilog license
231
; nomgc         Do not look for Mentor Graphics Licenses
232
; nomti         Do not look for Model Technology Licenses
233 8 qaztronic
; noqueue       Do not wait in the license queue when a license isn't available
234
; viewsim       Try for viewer license but accept simulator license(s) instead
235
;               of queuing for viewer license
236 2 qaztronic
; License = plus
237
 
238 8 qaztronic
; Stop the simulator after a VHDL/Verilog assertion message
239 2 qaztronic
; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal
240
BreakOnAssertion = 3
241
 
242 8 qaztronic
; Assertion Message Format
243 2 qaztronic
; %S - Severity Level
244
; %R - Report Message
245
; %T - Time of assertion
246
; %D - Delta
247
; %I - Instance or Region pathname (if available)
248 8 qaztronic
; %% - print '%' character
249
; AssertionFormat = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
250 2 qaztronic
 
251 8 qaztronic
; Assertion File - alternate file for storing VHDL/Verilog assertion messages
252
; AssertFile = assert.log
253 2 qaztronic
 
254 8 qaztronic
; Default radix for all windows and commands...
255 2 qaztronic
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
256
DefaultRadix = symbolic
257
 
258
; VSIM Startup command
259
; Startup = do startup.do
260
 
261
; File for saving command transcript
262
TranscriptFile = transcript
263
 
264
; File for saving command history
265
; CommandHistory = cmdhist.log
266
 
267
; Specify whether paths in simulator commands should be described
268
; in VHDL or Verilog format.
269
; For VHDL, PathSeparator = /
270
; For Verilog, PathSeparator = .
271
; Must not be the same character as DatasetSeparator.
272
PathSeparator = /
273
 
274
; Specify the dataset separator for fully rooted contexts.
275 8 qaztronic
; The default is ':'. For example, sim:/top
276 2 qaztronic
; Must not be the same character as PathSeparator.
277
DatasetSeparator = :
278
 
279
; Disable VHDL assertion messages
280
; IgnoreNote = 1
281
; IgnoreWarning = 1
282
; IgnoreError = 1
283
; IgnoreFailure = 1
284
 
285
; Default force kind. May be freeze, drive, deposit, or default
286
; or in other terms, fixed, wired, or charged.
287
; A value of "default" will use the signal kind to determine the
288
; force kind, drive for resolved signals, freeze for unresolved signals
289
; DefaultForceKind = freeze
290
 
291
; If zero, open files when elaborated; otherwise, open files on
292
; first read or write.  Default is 0.
293
; DelayFileOpen = 1
294
 
295
; Control VHDL files opened for write.
296
;   0 = Buffered, 1 = Unbuffered
297
UnbufferedOutput = 0
298
 
299
; Control the number of VHDL files open concurrently.
300
; This number should always be less than the current ulimit
301
; setting for max file descriptors.
302
;   0 = unlimited
303
ConcurrentFileLimit = 40
304
 
305
; Control the number of hierarchical regions displayed as
306
; part of a signal name shown in the Wave window.
307
; A value of zero tells VSIM to display the full name.
308
; The default is 0.
309
; WaveSignalNameWidth = 0
310
 
311
; Turn off warnings from the std_logic_arith, std_logic_unsigned
312
; and std_logic_signed packages.
313
; StdArithNoWarnings = 1
314
 
315
; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
316
; NumericStdNoWarnings = 1
317
 
318
; Control the format of the (VHDL) FOR generate statement label
319
; for each iteration.  Do not quote it.
320
; The format string here must contain the conversion codes %s and %d,
321
; in that order, and no other conversion codes.  The %s represents
322
; the generate_label; the %d represents the generate parameter value
323
; at a particular generate iteration (this is the position number if
324
; the generate parameter is of an enumeration type).  Embedded whitespace
325
; is allowed (but discouraged); leading and trailing whitespace is ignored.
326
; Application of the format must result in a unique scope name over all
327
; such names in the design so that name lookup can function properly.
328
; GenerateFormat = %s__%d
329
 
330
; Specify whether checkpoint files should be compressed.
331
; The default is 1 (compressed).
332
; CheckpointCompressMode = 0
333
 
334
; List of dynamically loaded objects for Verilog PLI applications
335
; Veriuser = veriuser.sl
336
 
337
; Specify default options for the restart command. Options can be one
338 8 qaztronic
; or more of: -force -nobreakpoint -nolist -nolog -nowave
339 2 qaztronic
; DefaultRestartOptions = -force
340
 
341 8 qaztronic
; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
342
; (> 500 megabyte memory footprint). Default is disabled.
343
; Specify number of megabytes to lock.
344
; LockedMemory = 1000
345
 
346 2 qaztronic
; Turn on (1) or off (0) WLF file compression.
347
; The default is 1 (compress WLF file).
348
; WLFCompress = 0
349
 
350
; Specify whether to save all design hierarchy (1) in the WLF file
351
; or only regions containing logged signals (0).
352
; The default is 0 (save only regions with logged signals).
353
; WLFSaveAllRegions = 1
354
 
355
; WLF file time limit.  Limit WLF file by time, as closely as possible,
356
; to the specified amount of simulation time.  When the limit is exceeded
357
; the earliest times get truncated from the file.
358
; If both time and size limits are specified the most restrictive is used.
359
; UserTimeUnits are used if time units are not specified.
360
; The default is 0 (no limit).  Example: WLFTimeLimit = {100 ms}
361
; WLFTimeLimit = 0
362
 
363
; WLF file size limit.  Limit WLF file size, as closely as possible,
364
; to the specified number of megabytes.  If both time and size limits
365
; are specified then the most restrictive is used.
366
; The default is 0 (no limit).
367
; WLFSizeLimit = 1000
368
 
369
; Specify whether or not a WLF file should be deleted when the
370
; simulation ends.  A value of 1 will cause the WLF file to be deleted.
371
; The default is 0 (do not delete WLF file when simulation ends).
372
; WLFDeleteOnQuit = 1
373
 
374 8 qaztronic
; Automatic SDF compilation
375
; Disables automatic compilation of SDF files in flows that support it.
376
; Default is on, uncomment to turn off.
377
; NoAutoSDFCompile = 1
378 2 qaztronic
 
379
[lmc]
380
 
381
[msg_system]
382
; Change a message severity or suppress a message.
383
; The format is:  = [,...]
384
; Examples:
385
;   note = 3009
386
;   warning = 3033
387
;   error = 3010,3016
388
;   fatal = 3016,3033
389
;   suppress = 3009,3016,3043
390
; The command verror  can be used to get the complete
391
; description of a message.
392
 
393 8 qaztronic
; Control transcripting of elaboration/runtime messages.
394
; The default is to have messages appear in the transcript and
395
; recorded in the wlf file (messages that are recorded in the
396
; wlf file can be viewed in the MsgViewer).  The other settings
397
; are to send messages only to the transcript or only to the
398
; wlf file.  The valid values are
399 2 qaztronic
;    both  {default}
400
;    tran  {transcript only}
401
;    wlf   {wlf file only}
402
; msgmode = both
403
[Project]
404 8 qaztronic
; Warning -- Do not edit the project properties directly.
405
;            Property names are dynamic in nature and property
406
;            values have special syntax.  Changing property data directly
407
;            can result in a corrupt MPF file.  All project properties
408
;            can be modified through project window dialogs.
409 2 qaztronic
Project_Version = 6
410
Project_DefaultLib = work
411
Project_SortMethod = unused
412 10 qaztronic
Project_Files_Count = 8
413
Project_File_0 = C:/qaz/_CVS_WORK/units/de1_olpcl2294_system/sim/tests/debug/the_test.v
414
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1296866265 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
415
Project_File_1 = C:/qaz/_CVS_WORK/units/de1_olpcl2294_system/src/mw_pll_sys_clk.v
416
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1297115878 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0
417
Project_File_2 = C:/qaz/_CVS_WORK/units/de1_olpcl2294_system/src/qaz_pic.v
418
Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1272304987 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0
419
Project_File_3 = C:/qaz/_CVS_WORK/units/de1_olpcl2294_system/src/top.v
420
Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1297192878 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src compile_order 7 cover_expr 0 dont_compile 0 cover_stmt 0
421
Project_File_4 = C:/qaz/_CVS_WORK/units/de1_olpcl2294_system/src/qaz_pll.v
422
Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1295636981 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src compile_order 5 cover_expr 0 dont_compile 0 cover_stmt 0
423
Project_File_5 = C:/qaz/_CVS_WORK/units/de1_olpcl2294_system/src/hex_led_encoder.v
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Project_File_6 = C:/qaz/_CVS_WORK/units/de1_olpcl2294_system/src/qaz_system.v
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Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1295634492 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src compile_order 6 cover_expr 0 dont_compile 0 cover_stmt 0
427
Project_File_7 = C:/qaz/_CVS_WORK/units/de1_olpcl2294_system/src/mw_pll_buffer.v
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Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1295636870 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0
429 2 qaztronic
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TEXT_CustomDoubleClick =
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UCDB_CustomDoubleClick =
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Project_Major_Version = 6
463 8 qaztronic
Project_Minor_Version = 5

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