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[/] [deslcore/] [trunk/] [rtl/] [key_schedule.vhd] - Blame information for rev 3

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Line No. Rev Author Line
1 3 entactogen
 
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-- Copyright (c) 2013 Antonio de la Piedra
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
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17 2 entactogen
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity key_schedule is
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        port(clk : in std_logic;
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                  rst : in std_logic;
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                  mode : in std_logic; -- 0 encrypt, 1 decrypt
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             key : in std_logic_vector(55 downto 0);
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                  key_out : out std_logic_vector(47 downto 0));
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end key_schedule;
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architecture Behavioral of key_schedule is
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        signal init_key_s : std_logic_vector(55 downto 0);
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        signal c_0_s : std_logic_vector(27 downto 0);
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        signal d_0_s : std_logic_vector(27 downto 0);
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        signal shift_s : std_logic_vector(15 downto 0);
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        signal key_pre_s : std_logic_vector(55 downto 0);
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        signal key_pre_delay_s : std_logic_vector(55 downto 0);
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begin
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        pr_seq: process(clk, rst, key, shift_s(15), mode)
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        begin
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                if rst = '1' then
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                        c_0_s <=  key(55 downto 28);
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                        d_0_s <=  key(27 downto 0);
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                elsif rising_edge(clk) then
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                        if shift_s(15) = '0' then
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                                if mode = '0' then
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                                        c_0_s <= c_0_s(26 downto 0) & c_0_s(27);
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                                        d_0_s <= d_0_s(26 downto 0) & d_0_s(27);
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                                else
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                                        c_0_s <= c_0_s(0) & c_0_s(27 downto 1);
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                                        d_0_s <= d_0_s(0) & d_0_s(27 downto 1);
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                                end if;
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                        else
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                                if mode = '0' then
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                                        c_0_s <= c_0_s(25 downto 0) & c_0_s(27 downto 26);
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                                        d_0_s <= d_0_s(25 downto 0) & d_0_s(27 downto 26);
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                                else
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                                        c_0_s <= c_0_s(1 downto 0) & c_0_s(27 downto 2);
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                                        d_0_s <= d_0_s(1 downto 0) & d_0_s(27 downto 2);
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                                end if;
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                        end if;
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                end if;
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        end process;
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        pr_shr: process(clk, rst, mode)
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        begin
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                if rst = '1' then
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                        if mode = '0' then
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                                shift_s <= "0011111101111110";
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                        else
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                                shift_s <= "0111111011111100";
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                        end if;
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                elsif rising_edge(clk) then
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                        shift_s <= shift_s(14 downto 0) & shift_s(15);
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                end if;
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        end process;
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        key_pre_s <= c_0_s & d_0_s;
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        pr_delay: process(clk, mode, key_pre_s)
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        begin
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                if rising_edge(clk) then
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                        if mode = '1' then
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                                key_pre_delay_s <= key_pre_s;
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                        end if;
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                end if;
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        end process;
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        key_out <= (key_pre_s (42)  & key_pre_s (39) & key_pre_s (45) & key_pre_s (32) & key_pre_s (55) & key_pre_s (51) & key_pre_s (53) & key_pre_s (28) &
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                                  key_pre_s (41) & key_pre_s (50)  & key_pre_s (35) & key_pre_s (46) & key_pre_s (33) & key_pre_s (37) & key_pre_s (44) & key_pre_s (52) &
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                                  key_pre_s (30) & key_pre_s (48) & key_pre_s (40)  & key_pre_s (49) & key_pre_s (29) & key_pre_s (36) & key_pre_s (43) & key_pre_s (54) &
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                                  key_pre_s (15)  & key_pre_s (4) & key_pre_s (25) & key_pre_s (19) & key_pre_s (9) & key_pre_s (1) & key_pre_s (26) & key_pre_s (16) &
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                                  key_pre_s (5) & key_pre_s (11)  & key_pre_s (23) & key_pre_s (8) & key_pre_s (12) & key_pre_s (7) & key_pre_s (17) & key_pre_s (0) &
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                                  key_pre_s (22) & key_pre_s (3) & key_pre_s (10)  & key_pre_s (14) & key_pre_s (6) & key_pre_s (20) & key_pre_s (27) & key_pre_s (24))
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                                  when mode = '0' else
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                                  (key_pre_delay_s (42)  & key_pre_delay_s (39) & key_pre_delay_s (45) & key_pre_delay_s (32) & key_pre_delay_s (55) & key_pre_delay_s (51) & key_pre_delay_s (53) & key_pre_delay_s (28) &
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                                  key_pre_delay_s (41) & key_pre_delay_s (50)  & key_pre_delay_s (35) & key_pre_delay_s (46) & key_pre_delay_s (33) & key_pre_delay_s (37) & key_pre_delay_s (44) & key_pre_delay_s (52) &
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                                  key_pre_delay_s (30) & key_pre_delay_s (48) & key_pre_delay_s (40)  & key_pre_delay_s (49) & key_pre_delay_s (29) & key_pre_delay_s (36) & key_pre_delay_s (43) & key_pre_delay_s (54) &
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                                  key_pre_delay_s (15)  & key_pre_delay_s (4) & key_pre_delay_s (25) & key_pre_delay_s (19) & key_pre_delay_s (9) & key_pre_delay_s (1) & key_pre_delay_s (26) & key_pre_delay_s (16) &
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                                  key_pre_delay_s (5) & key_pre_delay_s (11)  & key_pre_delay_s (23) & key_pre_delay_s (8) & key_pre_delay_s (12) & key_pre_delay_s (7) & key_pre_delay_s (17) & key_pre_delay_s (0) &
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                                  key_pre_delay_s (22) & key_pre_delay_s (3) & key_pre_delay_s (10)  & key_pre_delay_s (14) & key_pre_delay_s (6) & key_pre_delay_s (20) & key_pre_delay_s (27) & key_pre_delay_s (24));
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end Behavioral;
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