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[/] [dmt_tx/] [trunk/] [myhdl/] [test/] [test_queue.py] - Blame information for rev 33

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1 33 dannori 
 
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import unittest
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from myhdl import *
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from rtl.queue import queue, simple_reg
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class TestQueue(unittest.TestCase):
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  def test_simple_reg(self):
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    def bench():
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      width = 4
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      m = 2**(width-1)
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      # set some stimulus values, need to be in range of width
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      value1 = 7
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      value2 = -8
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      value3 = -3
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      clk, reset, w_en = [Signal(bool(0)) for i in range(3)]
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      d_i, d_o = [Signal(intbv(0, min=-m, max=m)) for i in range(2)]
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      simple_reg_inst = simple_reg(clk, reset, w_en, d_i, d_o)
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      @always(delay(10))
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      def clkgen():
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        clk.next = not clk
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      @instance
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      def stimulus():
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        # reset the reg
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        w_en.next = False
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        reset.next = True
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        yield clk.negedge
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        reset.next = False
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        yield clk.negedge
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        # write a value and expect it as output
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        w_en.next = True
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        d_i.next = value1
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        yield clk.negedge
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        # apply a new input value with w_en=False and expect the old
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        # output to remain
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        w_en.next = False
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        d_i.next = value2
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        yield clk.negedge
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        # apply a new input value with w_en=True and expect the output
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        # to change
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        w_en.next = True
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        d_i.next = value3
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        yield clk.negedge
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        # and now reset again with active w_en and expect the value to
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        # be 0
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        w_en.next = True
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        reset.next = True
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        yield clk.negedge
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        w_en.next = False
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        reset.next = False
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        yield clk.negedge
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        raise StopSimulation
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      @instance
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      def verify():
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        yield clk.negedge
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        self.assertEqual(reset, True)
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        yield clk.negedge
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        self.assertEqual(reset, False)
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        self.assertEqual(d_o, 0, '%d should be 0 at %d'%(d_o, now()))
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        # verify that the first value appears as output
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        yield clk.negedge
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        self.assertEqual(d_o, value1)
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        # expect still the old output value1 to remain
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        yield clk.negedge
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        self.assertEqual(d_o, value1)
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        # expect now the new input value3 as output
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        yield clk.negedge
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        self.assertEqual(d_o, value3)
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        # now expect the value to be reset, despite an active w_en
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        yield clk.negedge
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        self.assertEqual(d_o, 0)
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        # and still remain 0
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        yield clk.negedge
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        self.assertEqual(d_o, 0)
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      return instances()
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    tb = bench()
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    #tb = traceSignals(bench)
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    sim = Simulation(tb)
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    sim.run()
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  def test_queue(self):
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    def bench():
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      qlen = 3
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      width = 4
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      m = 2**(width-1)
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      value1 = -m
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      value2 = -1
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      value3 = m-1
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      value4 = 1
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      clk, reset, shift = [Signal(bool(0)) for i in range(3)]
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      d_i, d_o = [Signal(intbv(0, min=-m, max=m)) for i in range(2)]
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      queue_inst = queue(clk, reset, shift, d_i, d_o, qlen)
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      @always(delay(10))
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      def clkgen():
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        clk.next = not clk
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      @instance
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      def stimulus():
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        # apply reset
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        shift.next = False
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        reset.next = True
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        yield clk.negedge #1
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        reset.next = False
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        yield clk.negedge #2
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        #print 'stim #2 ', now()
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        ## Test the shift through
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        #
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        # fill in a different value for each register and expect the
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        # output value to change, considering the 0 values from reset.
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        # So when filling in value1, value2, value3, the expected
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        # output is 0, 0, value1, value2, value3
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        shift.next = True
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        d_i.next = value1
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        yield clk.negedge #3
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        d_i.next = value2
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        yield clk.negedge #4
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        d_i.next = value3
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        yield clk.negedge #5
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        #print 'stim #5 ', now()
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        # needed to shift the values out for verification and fill in
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        # value4, but only 2 times
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        d_i.next = value4
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        yield clk.negedge #6
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        yield clk.negedge #7
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        ## Hold values
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        # now hold, should see value3 3 times
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        shift.next = False
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        yield clk.negedge #8
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        yield clk.negedge #9
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        yield clk.negedge #10
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        yield clk.negedge #11
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        #print 'stim time sync: ', now()
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        ## Shift out again
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        # shifting out value4 vor verification and filling in value2
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        d_i.next = value2
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        shift.next = True
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        yield clk.negedge #12
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        #print 'stim #12 ', now()
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        yield clk.negedge #13
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        yield clk.negedge #14
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        ## Reset and then shift
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        # now reset and then shift, expecting qlen x 0 to come out
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        reset.next = True
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        yield clk.negedge #15
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        reset.next = False
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        yield clk.negedge #16
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        yield clk.negedge #17
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        yield clk.negedge #18
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        raise StopSimulation
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      @instance
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      def verify():
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        # verify that output is 0
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        yield clk.negedge #1
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        self.assertEqual(reset, True)
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        yield clk.negedge #2
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        #print 'veri #2 ', now()
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        self.assertEqual(reset, False)
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        self.assertEqual(shift, False)
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        self.assertEqual(d_o, 0, '%d should be 0 at %d'%(d_o, now()))
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        ## Test the shift through
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        # expecting 0, 0, value1, value2, value3
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        yield clk.negedge #3
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        self.assertEqual(shift, True)
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        self.assertEqual(d_o, 0, '%d should be 0 at %d'%(d_o, now()))
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        yield clk.negedge #4
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        self.assertEqual(d_o, 0, '%d should be 0 at %d'%(d_o, now()))
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        yield clk.negedge #5
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        #print 'verify #5 ', now()
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        self.assertEqual(d_o, value1)
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        yield clk.negedge #6
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        self.assertEqual(d_o, value2)
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        yield clk.negedge #7
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        self.assertEqual(d_o, value3)
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        ## Hold values (2 x value4, 1 x value3)
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        # now expect 3x value3 -- always output from last register, as
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        # no shifting is done
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        yield clk.negedge #8
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        self.assertEqual(d_o, value3)
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        yield clk.negedge #9
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        self.assertEqual(d_o, value3)
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        yield clk.negedge #10
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        self.assertEqual(d_o, value3)
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        yield clk.negedge #11
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        self.assertEqual(d_o, value3)
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        ## Shift out again
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        # should get 3x value4 -- this time shifting is active and
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        # values from all registers should get shifted out
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        #print 'verify time sync: ', now()
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        #self.assertEqual(shift, True)
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        yield clk.negedge #12
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        #print 'verify #12 ', now()
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        self.assertEqual(d_o, value4)
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        yield clk.negedge #13
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        self.assertEqual(d_o, value4)
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        ## Expect value2 from #12
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        yield clk.negedge #14
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        self.assertEqual(d_o, value2, '%d should be %d at %d'%(d_o, value2, now()))
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        #self.assertEqual(reset, True,
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        #    'reset is "%d" should be "True" at %d'%(reset, now()))
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        ## Reset and shift
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        # now expecting a reset and then qlen x 0
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        yield clk.negedge #15
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        self.assertEqual(d_o, 0, '%d should be 0 at %d'%(d_o, now()))
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        yield clk.negedge #16
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        self.assertEqual(d_o, 0, '%d should be 0 at %d'%(d_o, now()))
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        yield clk.negedge #17
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        self.assertEqual(d_o, 0, '%d should be 0 at %d'%(d_o, now()))
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      return instances()
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    tb = bench()
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    #tb = traceSignals(bench)
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    sim = Simulation(tb)
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    sim.run()
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