OpenCores
URL https://opencores.org/ocsvn/dvb_s2_ldpc_decoder/dvb_s2_ldpc_decoder/trunk

Subversion Repositories dvb_s2_ldpc_decoder

[/] [dvb_s2_ldpc_decoder/] [trunk/] [rtl/] [ldpc_muxreg.v] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 jcorley
//-------------------------------------------------------------------------
2
//
3
// File name    :  ldpc_muxreg.v
4
// Title        :
5
//              :
6
// Purpose      : Just a multiplexer and a register, but I added a level
7
//              : of hierarchy because design_vision was choking on the
8
//              : flat version
9
//
10
// ----------------------------------------------------------------------
11
// Revision History :
12
// ----------------------------------------------------------------------
13
//   Ver  :| Author   :| Mod. Date   :| Changes Made:
14
//   v1.0  | JTC      :| 2008/07/02  :|
15
// ----------------------------------------------------------------------
16
`timescale 1ns/10ps
17
 
18
module ldpc_muxreg #(
19
  parameter LLRWIDTH = 4,
20
  parameter NUMINPS  = 4,
21
  parameter MUXSIZE  = 4,
22
  parameter SELBITS  = 2
23
)(
24
  input clk,
25
  input rst,
26
 
27
  input[SELBITS-1:0]          sel,
28
  input[NUMINPS*LLRWIDTH-1:0] din,
29
  output[LLRWIDTH-1:0]        dout
30
);
31
 
32
// convert to 2-d array
33
wire[LLRWIDTH-1:0] din_2d[MUXSIZE-1:0];
34
 
35
generate
36
  genvar muxpos;
37
 
38
  for( muxpos=0; muxpos<MUXSIZE; muxpos=muxpos+1 )
39
  begin: muxto2d
40
    assign din_2d[muxpos] = din[muxpos*LLRWIDTH+LLRWIDTH-1 -: LLRWIDTH];
41
  end
42
endgenerate
43
 
44
// mux and register
45
reg[LLRWIDTH-1:0] mux_result;
46
 
47
assign dout = mux_result;
48
 
49
always @( posedge clk, posedge rst )
50
  if( rst )
51
    mux_result <= 0;
52
  else
53
    mux_result <= din_2d[sel];
54
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.