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[/] [dvb_s2_ldpc_decoder/] [trunk/] [rtl/] [ldpc_vncluster.v] - Blame information for rev 2

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//-------------------------------------------------------------------------
//
// File name    :  ldpc_vncluster.v
// Title        :
//              :
// Purpose      : A group of VN's and the associated RAM.  Clustering
//              : VN's around a RAM should reduce area in the ASIC
//              : implementation by using fewer, larger RAM's.  It should
//              : also ease placement by allowing placement of a number
//              : 
//
// ----------------------------------------------------------------------
// Revision History :
// ----------------------------------------------------------------------
//   Ver  :| Author   :| Mod. Date   :| Changes Made:
//   v1.0  | JTC      :| 2008/09/15  :|
// ----------------------------------------------------------------------
`timescale 1ns/10ps
 
module ldpc_vncluster #(
  parameter NUMVNS         = 3,
  parameter ENABLE_DISABLE = 1,
  parameter FOLDFACTOR     = 1,
  parameter LASTSHIFTWIDTH = 4,
  parameter LLRWIDTH       = 6
)(
  input clk,
  input rst,
 
  // LLR I/O
  input                       llr_access,
  input[7+FOLDFACTOR-1:0]     llr_addr,
  input                       llr_din_we,
  input[NUMVNS*LLRWIDTH-1:0]  llr_din,
  output[NUMVNS*LLRWIDTH-1:0] llr_dout,
 
  // message control
  input                   iteration,
  input                   first_half,
  input                   first_iteration,  // ignore upmsgs
  input                   we_vnmsg,
  input                   disable_vn,
  input[7+FOLDFACTOR-1:0] addr_vn,
 
  // message I/O
  input  wire[NUMVNS*LLRWIDTH-1:0] sh_cluster_msg,
  output wire[NUMVNS*LLRWIDTH-1:0] vn_cluster_msg
);
 
wire   zero;
assign zero = 0;
 
////////////////////////
// 2-d/1-d conversion //
////////////////////////
wire[LLRWIDTH-1:0] vn_msg[0:NUMVNS-1];
wire[LLRWIDTH-1:0] sh_msg[0:NUMVNS-1];
wire[LLRWIDTH-1:0] llr_din_2d[0:NUMVNS-1];
wire[LLRWIDTH-1:0] llr_dout_2d[0:NUMVNS-1];
 
generate
  genvar j;
 
  for( j=0; j<NUMVNS; j=j+1 )
  begin: convert1d2d
    assign vn_cluster_msg[LLRWIDTH*j+LLRWIDTH-1 -: LLRWIDTH] = vn_msg[j];
    assign sh_msg[j] = sh_cluster_msg[LLRWIDTH*j+LLRWIDTH-1 -: LLRWIDTH];
 
    assign llr_din_2d[j] = llr_din[LLRWIDTH*j+LLRWIDTH-1 -: LLRWIDTH];
    assign llr_dout[LLRWIDTH*j+LLRWIDTH-1 -: LLRWIDTH] = llr_dout_2d[j];
  end
endgenerate
 
//////////
// VN's //
//////////
wire                   llrram_we;
wire[7+FOLDFACTOR-1:0] vnram_wraddr;
wire[7+FOLDFACTOR-1:0] vnram_rdaddr;
wire[LLRWIDTH-1:0]     llrram_din[0:NUMVNS-1];
wire[LLRWIDTH-1:0]     llrram_dout[0:NUMVNS-1];
 
wire                 upmsg_we;
wire[2*LLRWIDTH+4:0] upmsg_din[0:NUMVNS-1];
wire[2*LLRWIDTH+4:0] upmsg_dout[0:NUMVNS-1];
 
wire upmsg_we_last;
 
generate
  genvar i;
 
  for( i=0; i<NUMVNS; i=i+1 )
  begin: varnodes
    // first
    if( i==0 )
    begin
      ldpc_vn #( .FOLDFACTOR(FOLDFACTOR),
                 .LLRWIDTH  (LLRWIDTH)
      ) ldpc_vn0i (
        .clk              (clk),
        .rst              (rst),
        .llr_access       (llr_access),
        .llr_addr         (llr_addr),
        .llr_din_we       (llr_din_we),
        .llr_din          (llr_din_2d[i]),
        .llr_dout         (llr_dout_2d[i]),
        .iteration        (iteration),
        .first_half       (first_half),
        .first_iteration  (first_iteration),
        .we_vnmsg         (we_vnmsg),
        .disable_vn(zero),
        .addr_vn          (addr_vn),
        .sh_msg           (sh_msg[i]),
        .vn_msg           (vn_msg[i]),
        .vnram_wraddr     (vnram_wraddr),
        .vnram_rdaddr     (vnram_rdaddr),
        .upmsg_we         (upmsg_we),
        .upmsg_din        (upmsg_din[i]),
        .upmsg_dout       (upmsg_dout[i])
      );
    end
 
    // last
    if( i==NUMVNS-1 )
    begin
      ldpc_vn #( .FOLDFACTOR(FOLDFACTOR),
                 .LLRWIDTH  (LLRWIDTH)
      ) ldpc_vnlasti (
        .clk              (clk),
        .rst              (rst),
        .llr_access       (llr_access),
        .llr_addr         (llr_addr),
        .llr_din_we       (llr_din_we),
        .llr_din          (llr_din_2d[i]),
        .llr_dout         (llr_dout_2d[i]),
        .iteration        (iteration),
        .first_half       (first_half),
        .first_iteration  (first_iteration),
        .we_vnmsg         (we_vnmsg),
        .disable_vn(disable_vn),
        .addr_vn          (addr_vn),
        .sh_msg           (sh_msg[i]),
        .vn_msg           (vn_msg[i]),
        .vnram_wraddr     (),
        .vnram_rdaddr     (),
        .upmsg_we         (upmsg_we_last),
        .upmsg_din        (upmsg_din[i]),
        .upmsg_dout       (upmsg_dout[i])
      );
    end
 
    if( (i!=0) && (i!=NUMVNS-1) )
    begin
      ldpc_vn #( .FOLDFACTOR(FOLDFACTOR),
                 .LLRWIDTH  (LLRWIDTH)
      ) ldpc_vni (
        .clk              (clk),
        .rst              (rst),
        .llr_access       (llr_access),
        .llr_addr         (llr_addr),
        .llr_din_we       (llr_din_we),
        .llr_din          (llr_din_2d[i]),
        .llr_dout         (llr_dout_2d[i]),
        .iteration        (iteration),
        .first_half       (first_half),
        .first_iteration  (first_iteration),
        .we_vnmsg         (we_vnmsg),
        .disable_vn(zero),
        .addr_vn          (addr_vn),
        .sh_msg           (sh_msg[i]),
        .vn_msg           (vn_msg[i]),
        .vnram_wraddr     (),
        .vnram_rdaddr     (),
        .upmsg_we         (),
        .upmsg_din        (upmsg_din[i]),
        .upmsg_dout       (upmsg_dout[i])
      );
    end
  end
endgenerate
 
// Combine RAM I/O's
wire[NUMVNS*(2*LLRWIDTH+5)-1:0] combined_din;
wire[NUMVNS*(2*LLRWIDTH+5)-1:0] combined_dout;
 
generate
  genvar k;
 
  for( k=0; k<NUMVNS; k=k+1 )
  begin: combine_all
    assign combined_din[k*(2*LLRWIDTH+5)+2*LLRWIDTH+4 -: 2*LLRWIDTH+5] = upmsg_din[k];
    assign upmsg_dout[k] = combined_dout[k*(2*LLRWIDTH+5)+2*LLRWIDTH+4 -: 2*LLRWIDTH+5];
  end
endgenerate
 
generate
  if( ENABLE_DISABLE )
  begin: split_rams
    ldpc_ram_behav #(
      .WIDTH    ((NUMVNS-1)*(2*LLRWIDTH+5)),
      .LOG2DEPTH(7+FOLDFACTOR)
    ) ldpc_vn_ram0i (
      .clk(clk),
      .we(upmsg_we),
      .din(combined_din[(NUMVNS-1)*(2*LLRWIDTH+5)-1 : 0]),
      .wraddr(vnram_wraddr),
      .rdaddr(vnram_rdaddr),
      .dout(combined_dout[(NUMVNS-1)*(2*LLRWIDTH+5)-1 : 0])
    );
 
    ldpc_ram_behav #(
      .WIDTH    (2*LLRWIDTH+5),
      .LOG2DEPTH(7+FOLDFACTOR)
    ) ldpc_vn_ramlasti (
      .clk(clk),
      .we(upmsg_we_last),
      .din(combined_din[NUMVNS*(2*LLRWIDTH+5)-1 -: 2*LLRWIDTH+5]),
      .wraddr(vnram_wraddr),
      .rdaddr(vnram_rdaddr),
      .dout(combined_dout[NUMVNS*(2*LLRWIDTH+5)-1 -: 2*LLRWIDTH+5])
    );
  end
  else
  begin: united_ram
    ldpc_ram_behav #(
      .WIDTH    (NUMVNS*(2*LLRWIDTH+5)),
      .LOG2DEPTH(7+FOLDFACTOR)
    ) ldpc_vn_rami (
      .clk   (clk),
      .we    (upmsg_we),
      .din   (combined_din),
      .wraddr(vnram_wraddr),
      .rdaddr(vnram_rdaddr),
      .dout  (combined_dout)
    );
  end
endgenerate
 
endmodule
 

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Subversion Repositories dvb_s2_ldpc_decoder

[/] [dvb_s2_ldpc_decoder/] [trunk/] [rtl/] [ldpc_vncluster.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	jcorley	`//-------------------------------------------------------------------------`
2			`//`
3			`// File name : ldpc_vncluster.v`
4			`// Title :`
5			`// :`
6			`// Purpose : A group of VN's and the associated RAM. Clustering`
7			`// : VN's around a RAM should reduce area in the ASIC`
8			`// : implementation by using fewer, larger RAM's. It should`
9			`// : also ease placement by allowing placement of a number`
10			`// :`
11			`//`
12			`// ----------------------------------------------------------------------`
13			`// Revision History :`
14			`// ----------------------------------------------------------------------`
15			`// Ver :\| Author :\| Mod. Date :\| Changes Made:`
16			`// v1.0 \| JTC :\| 2008/09/15 :\|`
17			`// ----------------------------------------------------------------------`
18			`timescale 1ns/10ps
19
20			`module ldpc_vncluster #(`
21			`parameter NUMVNS = 3,`
22			`parameter ENABLE_DISABLE = 1,`
23			`parameter FOLDFACTOR = 1,`
24			`parameter LASTSHIFTWIDTH = 4,`
25			`parameter LLRWIDTH = 6`
26			`)(`
27			`input clk,`
28			`input rst,`
29
30			`// LLR I/O`
31			`input llr_access,`
32			`input[7+FOLDFACTOR-1:0] llr_addr,`
33			`input llr_din_we,`
34			`input[NUMVNS*LLRWIDTH-1:0] llr_din,`
35			`output[NUMVNS*LLRWIDTH-1:0] llr_dout,`
36
37			`// message control`
38			`input iteration,`
39			`input first_half,`
40			`input first_iteration, // ignore upmsgs`
41			`input we_vnmsg,`
42			`input disable_vn,`
43			`input[7+FOLDFACTOR-1:0] addr_vn,`
44
45			`// message I/O`
46			`input wire[NUMVNS*LLRWIDTH-1:0] sh_cluster_msg,`
47			`output wire[NUMVNS*LLRWIDTH-1:0] vn_cluster_msg`
48			`);`
49
50			`wire zero;`
51			`assign zero = 0;`
52
53			`////////////////////////`
54			`// 2-d/1-d conversion //`
55			`////////////////////////`
56			`wire[LLRWIDTH-1:0] vn_msg[0:NUMVNS-1];`
57			`wire[LLRWIDTH-1:0] sh_msg[0:NUMVNS-1];`
58			`wire[LLRWIDTH-1:0] llr_din_2d[0:NUMVNS-1];`
59			`wire[LLRWIDTH-1:0] llr_dout_2d[0:NUMVNS-1];`
60
61			`generate`
62			`genvar j;`
63
64			`for( j=0; j<NUMVNS; j=j+1 )`
65			`begin: convert1d2d`
66			`assign vn_cluster_msg[LLRWIDTH*j+LLRWIDTH-1 -: LLRWIDTH] = vn_msg[j];`
67			`assign sh_msg[j] = sh_cluster_msg[LLRWIDTH*j+LLRWIDTH-1 -: LLRWIDTH];`
68
69			`assign llr_din_2d[j] = llr_din[LLRWIDTH*j+LLRWIDTH-1 -: LLRWIDTH];`
70			`assign llr_dout[LLRWIDTH*j+LLRWIDTH-1 -: LLRWIDTH] = llr_dout_2d[j];`
71			`end`
72			`endgenerate`
73
74			`//////////`
75			`// VN's //`
76			`//////////`
77			`wire llrram_we;`
78			`wire[7+FOLDFACTOR-1:0] vnram_wraddr;`
79			`wire[7+FOLDFACTOR-1:0] vnram_rdaddr;`
80			`wire[LLRWIDTH-1:0] llrram_din[0:NUMVNS-1];`
81			`wire[LLRWIDTH-1:0] llrram_dout[0:NUMVNS-1];`
82
83			`wire upmsg_we;`
84			`wire[2*LLRWIDTH+4:0] upmsg_din[0:NUMVNS-1];`
85			`wire[2*LLRWIDTH+4:0] upmsg_dout[0:NUMVNS-1];`
86
87			`wire upmsg_we_last;`
88
89			`generate`
90			`genvar i;`
91
92			`for( i=0; i<NUMVNS; i=i+1 )`
93			`begin: varnodes`
94			`// first`
95			`if( i==0 )`
96			`begin`
97			`ldpc_vn #( .FOLDFACTOR(FOLDFACTOR),`
98			`.LLRWIDTH (LLRWIDTH)`
99			`) ldpc_vn0i (`
100			`.clk (clk),`
101			`.rst (rst),`
102			`.llr_access (llr_access),`
103			`.llr_addr (llr_addr),`
104			`.llr_din_we (llr_din_we),`
105			`.llr_din (llr_din_2d[i]),`
106			`.llr_dout (llr_dout_2d[i]),`
107			`.iteration (iteration),`
108			`.first_half (first_half),`
109			`.first_iteration (first_iteration),`
110			`.we_vnmsg (we_vnmsg),`
111			`.disable_vn(zero),`
112			`.addr_vn (addr_vn),`
113			`.sh_msg (sh_msg[i]),`
114			`.vn_msg (vn_msg[i]),`
115			`.vnram_wraddr (vnram_wraddr),`
116			`.vnram_rdaddr (vnram_rdaddr),`
117			`.upmsg_we (upmsg_we),`
118			`.upmsg_din (upmsg_din[i]),`
119			`.upmsg_dout (upmsg_dout[i])`
120			`);`
121			`end`
122
123			`// last`
124			`if( i==NUMVNS-1 )`
125			`begin`
126			`ldpc_vn #( .FOLDFACTOR(FOLDFACTOR),`
127			`.LLRWIDTH (LLRWIDTH)`
128			`) ldpc_vnlasti (`
129			`.clk (clk),`
130			`.rst (rst),`
131			`.llr_access (llr_access),`
132			`.llr_addr (llr_addr),`
133			`.llr_din_we (llr_din_we),`
134			`.llr_din (llr_din_2d[i]),`
135			`.llr_dout (llr_dout_2d[i]),`
136			`.iteration (iteration),`
137			`.first_half (first_half),`
138			`.first_iteration (first_iteration),`
139			`.we_vnmsg (we_vnmsg),`
140			`.disable_vn(disable_vn),`
141			`.addr_vn (addr_vn),`
142			`.sh_msg (sh_msg[i]),`
143			`.vn_msg (vn_msg[i]),`
144			`.vnram_wraddr (),`
145			`.vnram_rdaddr (),`
146			`.upmsg_we (upmsg_we_last),`
147			`.upmsg_din (upmsg_din[i]),`
148			`.upmsg_dout (upmsg_dout[i])`
149			`);`
150			`end`
151
152			`if( (i!=0) && (i!=NUMVNS-1) )`
153			`begin`
154			`ldpc_vn #( .FOLDFACTOR(FOLDFACTOR),`
155			`.LLRWIDTH (LLRWIDTH)`
156			`) ldpc_vni (`
157			`.clk (clk),`
158			`.rst (rst),`
159			`.llr_access (llr_access),`
160			`.llr_addr (llr_addr),`
161			`.llr_din_we (llr_din_we),`
162			`.llr_din (llr_din_2d[i]),`
163			`.llr_dout (llr_dout_2d[i]),`
164			`.iteration (iteration),`
165			`.first_half (first_half),`
166			`.first_iteration (first_iteration),`
167			`.we_vnmsg (we_vnmsg),`
168			`.disable_vn(zero),`
169			`.addr_vn (addr_vn),`
170			`.sh_msg (sh_msg[i]),`
171			`.vn_msg (vn_msg[i]),`
172			`.vnram_wraddr (),`
173			`.vnram_rdaddr (),`
174			`.upmsg_we (),`
175			`.upmsg_din (upmsg_din[i]),`
176			`.upmsg_dout (upmsg_dout[i])`
177			`);`
178			`end`
179			`end`
180			`endgenerate`
181
182			`// Combine RAM I/O's`
183			`wire[NUMVNS(2LLRWIDTH+5)-1:0] combined_din;`
184			`wire[NUMVNS(2LLRWIDTH+5)-1:0] combined_dout;`
185
186			`generate`
187			`genvar k;`
188
189			`for( k=0; k<NUMVNS; k=k+1 )`
190			`begin: combine_all`
191			`assign combined_din[k(2LLRWIDTH+5)+2LLRWIDTH+4 -: 2LLRWIDTH+5] = upmsg_din[k];`
192			`assign upmsg_dout[k] = combined_dout[k(2LLRWIDTH+5)+2LLRWIDTH+4 -: 2LLRWIDTH+5];`
193			`end`
194			`endgenerate`
195
196			`generate`
197			`if( ENABLE_DISABLE )`
198			`begin: split_rams`
199			`ldpc_ram_behav #(`
200			`.WIDTH ((NUMVNS-1)(2LLRWIDTH+5)),`
201			`.LOG2DEPTH(7+FOLDFACTOR)`
202			`) ldpc_vn_ram0i (`
203			`.clk(clk),`
204			`.we(upmsg_we),`
205			`.din(combined_din[(NUMVNS-1)(2LLRWIDTH+5)-1 : 0]),`
206			`.wraddr(vnram_wraddr),`
207			`.rdaddr(vnram_rdaddr),`
208			`.dout(combined_dout[(NUMVNS-1)(2LLRWIDTH+5)-1 : 0])`
209			`);`
210
211			`ldpc_ram_behav #(`
212			`.WIDTH (2*LLRWIDTH+5),`
213			`.LOG2DEPTH(7+FOLDFACTOR)`
214			`) ldpc_vn_ramlasti (`
215			`.clk(clk),`
216			`.we(upmsg_we_last),`
217			`.din(combined_din[NUMVNS(2LLRWIDTH+5)-1 -: 2*LLRWIDTH+5]),`
218			`.wraddr(vnram_wraddr),`
219			`.rdaddr(vnram_rdaddr),`
220			`.dout(combined_dout[NUMVNS(2LLRWIDTH+5)-1 -: 2*LLRWIDTH+5])`
221			`);`
222			`end`
223			`else`
224			`begin: united_ram`
225			`ldpc_ram_behav #(`
226			`.WIDTH (NUMVNS(2LLRWIDTH+5)),`
227			`.LOG2DEPTH(7+FOLDFACTOR)`
228			`) ldpc_vn_rami (`
229			`.clk (clk),`
230			`.we (upmsg_we),`
231			`.din (combined_din),`
232			`.wraddr(vnram_wraddr),`
233			`.rdaddr(vnram_rdaddr),`
234			`.dout (combined_dout)`
235			`);`
236			`end`
237			`endgenerate`
238
239			`endmodule`
240