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craighaywo |
## This file is a general .ucf for Nexys2 rev A board
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## To use it in a project:
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## - remove or comment the lines corresponding to unused pins
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## - rename the used signals according to the project
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## Signals Led<7>Led<4> are assigned to pins which change type from s3e500 to other dies using the same package
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## Both versions are provided in this file.
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## Keep only the appropriate one, and remove or comment the other one.
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## Clock pin for Nexys 2 Board
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NET "CLK_IN" LOC = "B8"; # Bank = 0, Pin name = IP_L13P_0/GCLK8, Type = GCLK, Sch name = GCLK0
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TIMESPEC ts_clk = PERIOD "CLK_IN" 20 ns HIGH 50 %;
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#NET "clk1" LOC = "U9"; # Bank = 2, Pin name = IO_L13P_2/D4/GCLK14, Type = DUAL/GCLK, Sch name = GCLK1
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## onBoard USB controller
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## NOTE: DEPP and DSTM net names use some of the same pins, if trying to use both DEPP and DSTM use a signle net name for each shared pin.
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## Data bus for both the DEPP and DSTM interfaces uncomment lines 20-27 if using either one
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#NET "DB<0>" LOC = "R14"; # Bank = 2, Pin name = IO_L24N_2/A20, Type = DUAL, Sch name = U-FD0
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#NET "DB<1>" LOC = "R13"; # Bank = 2, Pin name = IO_L22N_2/A22, Type = DUAL, Sch name = U-FD1
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#NET "DB<2>" LOC = "P13"; # Bank = 2, Pin name = IO_L22P_2/A23, Type = DUAL, Sch name = U-FD2
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#NET "DB<3>" LOC = "T12"; # Bank = 2, Pin name = IO_L20P_2, Type = I/O, Sch name = U-FD3
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#NET "DB<4>" LOC = "N11"; # Bank = 2, Pin name = IO_L18N_2, Type = I/O, Sch name = U-FD4
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#NET "DB<5>" LOC = "R11"; # Bank = 2, Pin name = IO, Type = I/O, Sch name = U-FD5
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#NET "DB<6>" LOC = "P10"; # Bank = 2, Pin name = IO_L15N_2/D1/GCLK3, Type = DUAL/GCLK, Sch name = U-FD6
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#NET "DB<7>" LOC = "R10"; # Bank = 2, Pin name = IO_L15P_2/D2/GCLK2, Type = DUAL/GCLK, Sch name = U-FD7
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## If using the DEPP interface uncomment lines 30-33
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#NET "EppWRITE" LOC = "V16"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = U-FLAGC
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#NET "EppASTB" LOC = "V14"; # Bank = 2, Pin name = IP_L23P_2, Type = INPUT, Sch name = U-FLAGA
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#NET "EppDSTB" LOC = "U14"; # Bank = 2, Pin name = IP_L23N_2, Type = INPUT, Sch name = U-FLAGB
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#NET "EppWAIT" LOC = "N9"; # Bank = 2, Pin name = IO_L12P_2/D7/GCLK12, Type = DUAL/GCLK, Sch name = U-SLRD
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## If using the DSTM interface uncomment lines 36-45
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#NET "DstmIFCLK" LOC = "T15"; # Bank = 2, Pin name = IO/VREF_2, Type = VREF, Sch name = U-IFCLK
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#NET "DstmSLCS" LOC = "T16"; # Bank = 2, Pin name = IO_L26P_2/VS0/A17, Type = DUAL, Sch name = U-SLCS
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#NET "DstmFLAGA" LOC = "V14"; # Bank = 2, Pin name = IP_L23P_2, Type = INPUT, Sch name = U-FLAGA
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#NET "DstmFLAGB" LOC = "U14"; # Bank = 2, Pin name = IP_L23N_2, Type = INPUT, Sch name = U-FLAGB
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#NET "DstmADR<0>" LOC = "T14"; # Bank = 2, Pin name = IO_L24P_2/A21, Type = DUAL, Sch name = U-FIFOAD0
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#NET "DstmADR<1>" LOC = "V13"; # Bank = 2, Pin name = IO_L19N_2/VREF_2, Type = VREF, Sch name = U-FIFOAD1
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#NET "DstmSLRD" LOC = "N9"; # Bank = 2, Pin name = IO_L12P_2/D7/GCLK12, Type = DUAL/GCLK, Sch name = U-SLRD
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#NET "DstmSLWR" LOC = "V9"; # Bank = 2, Pin name = IO_L13N_2/D3/GCLK15, Type = DUAL/GCLK, Sch name = U-SLWR
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#NET "DstmSLOE" LOC = "V15"; # Bank = 2, Pin name = IO_L25P_2/VS2/A19, Type = DUAL, Sch name = U-SLOE
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#NET "DstmPKTEND" LOC = "V12"; # Bank = 2, Pin name = IO_L19P_2, Type = I/O, Sch name = U-PKTEND
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#NET "UsbMode" LOC = "U15"; # Bank = 2, Pin name = IO_L25N_2/VS1/A18, Type = DUAL, Sch name = U-INT0#
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#NET "UsbRdy" LOC = "U13"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = U-RDY
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## onBoard Cellular RAM and StrataFlash
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#NET "MemOE" LOC = "T2"; # Bank = 3, Pin name = IO_L24P_3, Type = I/O, Sch name = OE
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#NET "MemWR" LOC = "N7"; # Bank = 2, Pin name = IO_L07P_2, Type = I/O, Sch name = WE
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#NET "RamAdv" LOC = "J4"; # Bank = 3, Pin name = IO_L11N_3/LHCLK1, Type = LHCLK, Sch name = MT-ADV
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#NET "RamCS" LOC = "R6"; # Bank = 2, Pin name = IO_L05P_2, Type = I/O, Sch name = MT-CE
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#NET "RamClk" LOC = "H5"; # Bank = 3, Pin name = IO_L08N_3, Type = I/O, Sch name = MT-CLK
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#NET "RamCRE" LOC = "P7"; # Bank = 2, Pin name = IO_L07N_2, Type = I/O, Sch name = MT-CRE
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#NET "RamLB" LOC = "K5"; # Bank = 3, Pin name = IO_L14N_3/LHCLK7, Type = LHCLK, Sch name = MT-LB
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#NET "RamUB" LOC = "K4"; # Bank = 3, Pin name = IO_L13N_3/LHCLK5, Type = LHCLK, Sch name = MT-UB
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#NET "RamWait" LOC = "F5"; # Bank = 3, Pin name = IP, Type = INPUT, Sch name = MT-WAIT
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#NET "FlashRp" LOC = "T5"; # Bank = 2, Pin name = IO_L04N_2, Type = I/O, Sch name = RP#
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#NET "FlashCS" LOC = "R5"; # Bank = 2, Pin name = IO_L04P_2, Type = I/O, Sch name = ST-CE
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#NET "FlashStSts" LOC = "D3"; # Bank = 3, Pin name = IP, Type = INPUT, Sch name = ST-STS
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#NET "MemAdr<1>" LOC = "J1"; # Bank = 3, Pin name = IO_L12P_3/LHCLK2, Type = LHCLK, Sch name = ADR1
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#NET "MemAdr<2>" LOC = "J2"; # Bank = 3, Pin name = IO_L12N_3/LHCLK3/IRDY2, Type = LHCLK, Sch name = ADR2
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#NET "MemAdr<3>" LOC = "H4"; # Bank = 3, Pin name = IO_L09P_3, Type = I/O, Sch name = ADR3
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#NET "MemAdr<4>" LOC = "H1"; # Bank = 3, Pin name = IO_L10N_3, Type = I/O, Sch name = ADR4
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#NET "MemAdr<5>" LOC = "H2"; # Bank = 3, Pin name = IO_L10P_3, Type = I/O, Sch name = ADR5
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#NET "MemAdr<6>" LOC = "J5"; # Bank = 3, Pin name = IO_L11P_3/LHCLK0, Type = LHCLK, Sch name = ADR6
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#NET "MemAdr<7>" LOC = "H3"; # Bank = 3, Pin name = IO_L09N_3, Type = I/O, Sch name = ADR7
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#NET "MemAdr<8>" LOC = "H6"; # Bank = 3, Pin name = IO_L08P_3, Type = I/O, Sch name = ADR8
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#NET "MemAdr<9>" LOC = "F1"; # Bank = 3, Pin name = IO_L05P_3, Type = I/O, Sch name = ADR9
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#NET "MemAdr<10>" LOC = "G3"; # Bank = 3, Pin name = IO_L06P_3, Type = I/O, Sch name = ADR10
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#NET "MemAdr<11>" LOC = "G6"; # Bank = 3, Pin name = IO_L07P_3, Type = I/O, Sch name = ADR11
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#NET "MemAdr<12>" LOC = "G5"; # Bank = 3, Pin name = IO_L07N_3, Type = I/O, Sch name = ADR12
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#NET "MemAdr<13>" LOC = "G4"; # Bank = 3, Pin name = IO_L06N_3/VREF_3, Type = VREF, Sch name = ADR13
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#NET "MemAdr<14>" LOC = "F2"; # Bank = 3, Pin name = IO_L05N_3, Type = I/O, Sch name = ADR14
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#NET "MemAdr<15>" LOC = "E1"; # Bank = 3, Pin name = IO_L03N_3, Type = I/O, Sch name = ADR15
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#NET "MemAdr<16>" LOC = "M5"; # Bank = 3, Pin name = IO_L19P_3, Type = I/O, Sch name = ADR16
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#NET "MemAdr<17>" LOC = "E2"; # Bank = 3, Pin name = IO_L03P_3, Type = I/O, Sch name = ADR17
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#NET "MemAdr<18>" LOC = "C2"; # Bank = 3, Pin name = IO_L01N_3, Type = I/O, Sch name = ADR18
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#NET "MemAdr<19>" LOC = "C1"; # Bank = 3, Pin name = IO_L01P_3, Type = I/O, Sch name = ADR19
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#NET "MemAdr<20>" LOC = "D2"; # Bank = 3, Pin name = IO_L02N_3/VREF_3, Type = VREF, Sch name = ADR20
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#NET "MemAdr<21>" LOC = "K3"; # Bank = 3, Pin name = IO_L13P_3/LHCLK4/TRDY2, Type = LHCLK, Sch name = ADR21
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#NET "MemAdr<22>" LOC = "D1"; # Bank = 3, Pin name = IO_L02P_3, Type = I/O, Sch name = ADR22
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#NET "MemAdr<23>" LOC = "K6"; # Bank = 3, Pin name = IO_L14P_3/LHCLK6, Type = LHCLK, Sch name = ADR23
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#NET "MemDB<0>" LOC = "L1"; # Bank = 3, Pin name = IO_L15P_3, Type = I/O, Sch name = DB0
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#NET "MemDB<1>" LOC = "L4"; # Bank = 3, Pin name = IO_L16N_3, Type = I/O, Sch name = DB1
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#NET "MemDB<2>" LOC = "L6"; # Bank = 3, Pin name = IO_L17P_3, Type = I/O, Sch name = DB2
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#NET "MemDB<3>" LOC = "M4"; # Bank = 3, Pin name = IO_L18P_3, Type = I/O, Sch name = DB3
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#NET "MemDB<4>" LOC = "N5"; # Bank = 3, Pin name = IO_L20N_3, Type = I/O, Sch name = DB4
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#NET "MemDB<5>" LOC = "P1"; # Bank = 3, Pin name = IO_L21N_3, Type = I/O, Sch name = DB5
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#NET "MemDB<6>" LOC = "P2"; # Bank = 3, Pin name = IO_L21P_3, Type = I/O, Sch name = DB6
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#NET "MemDB<7>" LOC = "R2"; # Bank = 3, Pin name = IO_L23N_3, Type = I/O, Sch name = DB7
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#NET "MemDB<8>" LOC = "L3"; # Bank = 3, Pin name = IO_L16P_3, Type = I/O, Sch name = DB8
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#NET "MemDB<9>" LOC = "L5"; # Bank = 3, Pin name = IO_L17N_3/VREF_3, Type = VREF, Sch name = DB9
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#NET "MemDB<10>" LOC = "M3"; # Bank = 3, Pin name = IO_L18N_3, Type = I/O, Sch name = DB10
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#NET "MemDB<11>" LOC = "M6"; # Bank = 3, Pin name = IO_L19N_3, Type = I/O, Sch name = DB11
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#NET "MemDB<12>" LOC = "L2"; # Bank = 3, Pin name = IO_L15N_3, Type = I/O, Sch name = DB12
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#NET "MemDB<13>" LOC = "N4"; # Bank = 3, Pin name = IO_L20P_3, Type = I/O, Sch name = DB13
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#NET "MemDB<14>" LOC = "R3"; # Bank = 3, Pin name = IO_L23P_3, Type = I/O, Sch name = DB14
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#NET "MemDB<15>" LOC = "T1"; # Bank = 3, Pin name = IO_L24N_3, Type = I/O, Sch name = DB15
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## 7 segment display
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NET "SSEG_OUT<7>" LOC = "L18"; # Bank = 1, Pin name = IO_L10P_1, Type = I/O, Sch name = CA
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NET "SSEG_OUT<6>" LOC = "F18"; # Bank = 1, Pin name = IO_L19P_1, Type = I/O, Sch name = CB
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NET "SSEG_OUT<5>" LOC = "D17"; # Bank = 1, Pin name = IO_L23P_1/HDC, Type = DUAL, Sch name = CC
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NET "SSEG_OUT<4>" LOC = "D16"; # Bank = 1, Pin name = IO_L23N_1/LDC0, Type = DUAL, Sch name = CD
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NET "SSEG_OUT<3>" LOC = "G14"; # Bank = 1, Pin name = IO_L20P_1, Type = I/O, Sch name = CE
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NET "SSEG_OUT<2>" LOC = "J17"; # Bank = 1, Pin name = IO_L13P_1/A6/RHCLK4/IRDY1, Type = RHCLK/DUAL, Sch name = CF
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NET "SSEG_OUT<1>" LOC = "H14"; # Bank = 1, Pin name = IO_L17P_1, Type = I/O, Sch name = CG
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NET "SSEG_OUT<0>" LOC = "C17"; # Bank = 1, Pin name = IO_L24N_1/LDC2, Type = DUAL, Sch name = DP
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NET "AN_OUT<0>" LOC = "F17"; # Bank = 1, Pin name = IO_L19N_1, Type = I/O, Sch name = AN0
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NET "AN_OUT<1>" LOC = "H17"; # Bank = 1, Pin name = IO_L16N_1/A0, Type = DUAL, Sch name = AN1
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NET "AN_OUT<2>" LOC = "C18"; # Bank = 1, Pin name = IO_L24P_1/LDC1, Type = DUAL, Sch name = AN2
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NET "AN_OUT<3>" LOC = "F15"; # Bank = 1, Pin name = IO_L21P_1, Type = I/O, Sch name = AN3
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## Leds
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NET "LED_OUT<0>" LOC = "J14"; # Bank = 1, Pin name = IO_L14N_1/A3/RHCLK7, Type = RHCLK/DUAL, Sch name = JD10/LD0
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NET "LED_OUT<1>" LOC = "J15"; # Bank = 1, Pin name = IO_L14P_1/A4/RHCLK6, Type = RHCLK/DUAL, Sch name = JD9/LD1
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NET "LED_OUT<2>" LOC = "K15"; # Bank = 1, Pin name = IO_L12P_1/A8/RHCLK2, Type = RHCLK/DUAL, Sch name = JD8/LD2
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NET "LED_OUT<3>" LOC = "K14"; # Bank = 1, Pin name = IO_L12N_1/A7/RHCLK3/TRDY1, Type = RHCLK/DUAL, Sch name = JD7/LD3
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NET "LED_OUT<4>" LOC = "E17"; # Bank = 1, Pin name = IO, Type = I/O, Sch name = LD4
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| 128 |
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NET "LED_OUT<5>" LOC = "P15"; # Bank = 1, Pin name = IO, Type = I/O, Sch name = LD5
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NET "LED_OUT<6>" LOC = "F4"; # Bank = 3, Pin name = IO, Type = I/O, Sch name = LD6
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| 130 |
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NET "LED_OUT<7>" LOC = "R4"; # Bank = 3, Pin name = IO/VREF_3, Type = VREF, Sch name = LD7
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## Switches
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NET "SW_IN<0>" LOC = "G18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW0
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| 134 |
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NET "SW_IN<1>" LOC = "H18"; # Bank = 1, Pin name = IP/VREF_1, Type = VREF, Sch name = SW1
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| 135 |
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NET "SW_IN<2>" LOC = "K18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW2
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| 136 |
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NET "SW_IN<3>" LOC = "K17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW3
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| 137 |
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NET "SW_IN<4>" LOC = "L14"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW4
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| 138 |
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NET "SW_IN<5>" LOC = "L13"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW5
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| 139 |
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NET "SW_IN<6>" LOC = "N17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW6
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| 140 |
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NET "SW_IN<7>" LOC = "R17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW7
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| 142 |
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## Buttons
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NET "BUTTON_IN<0>" LOC = "B18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN0
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| 144 |
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NET "BUTTON_IN<1>" LOC = "D18"; # Bank = 1, Pin name = IP/VREF_1, Type = VREF, Sch name = BTN1
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| 145 |
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NET "BUTTON_IN<2>" LOC = "E18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN2
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| 146 |
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NET "BUTTON_IN<3>" LOC = "H13"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN3
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| 147 |
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| 148 |
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## VGA Connector
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| 149 |
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NET "vgaRed<0>" LOC = "R9"; # Bank = 2, Pin name = IO/D5, Type = DUAL, Sch name = RED0
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| 150 |
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NET "vgaRed<1>" LOC = "T8"; # Bank = 2, Pin name = IO_L10N_2, Type = I/O, Sch name = RED1
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| 151 |
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NET "vgaRed<2>" LOC = "R8"; # Bank = 2, Pin name = IO_L10P_2, Type = I/O, Sch name = RED2
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| 152 |
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NET "vgaGreen<0>" LOC = "N8"; # Bank = 2, Pin name = IO_L09N_2, Type = I/O, Sch name = GRN0
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| 153 |
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NET "vgaGreen<1>" LOC = "P8"; # Bank = 2, Pin name = IO_L09P_2, Type = I/O, Sch name = GRN1
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| 154 |
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NET "vgaGreen<2>" LOC = "P6"; # Bank = 2, Pin name = IO_L05N_2, Type = I/O, Sch name = GRN2
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| 155 |
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NET "vgaBlue<0>" LOC = "U5"; # Bank = 2, Pin name = IO/VREF_2, Type = VREF, Sch name = BLU1
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| 156 |
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NET "vgaBlue<1>" LOC = "U4"; # Bank = 2, Pin name = IO_L03P_2/DOUT/BUSY, Type = DUAL, Sch name = BLU2
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| 157 |
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| 158 |
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NET "Hsync" LOC = "T4"; # Bank = 2, Pin name = IO_L03N_2/MOSI/CSI_B, Type = DUAL, Sch name = HSYNC
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| 159 |
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NET "Vsync" LOC = "U3"; # Bank = 2, Pin name = IO_L01P_2/CSO_B, Type = DUAL, Sch name = VSYNC
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| 160 |
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| 161 |
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## PS/2 connector
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| 162 |
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#NET "PS2C_INOUT" LOC = "R12"; # Bank = 2, Pin name = IO_L20N_2, Type = I/O, Sch name = PS2C
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| 163 |
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#NET "PS2D_INOUT" LOC = "P11"; # Bank = 2, Pin name = IO_L18P_2, Type = I/O, Sch name = PS2D
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| 164 |
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| 165 |
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## FX2 connector
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| 166 |
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#NET "PIO<0>" LOC = "B4"; # Bank = 0, Pin name = IO_L24N_0, Type = I/O, Sch name = R-IO1
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| 167 |
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#NET "PIO<1>" LOC = "A4"; # Bank = 0, Pin name = IO_L24P_0, Type = I/O, Sch name = R-IO2
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| 168 |
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#NET "PIO<2>" LOC = "C3"; # Bank = 0, Pin name = IO_L25P_0, Type = I/O, Sch name = R-IO3
|
| 169 |
|
|
#NET "PIO<3>" LOC = "C4"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO4
|
| 170 |
|
|
#NET "PIO<4>" LOC = "B6"; # Bank = 0, Pin name = IO_L20P_0, Type = I/O, Sch name = R-IO5
|
| 171 |
|
|
#NET "PIO<5>" LOC = "D5"; # Bank = 0, Pin name = IO_L23N_0/VREF_0, Type = VREF, Sch name = R-IO6
|
| 172 |
|
|
#NET "PIO<6>" LOC = "C5"; # Bank = 0, Pin name = IO_L23P_0, Type = I/O, Sch name = R-IO7
|
| 173 |
|
|
#NET "PIO<7>" LOC = "F7"; # Bank = 0, Pin name = IO_L19P_0, Type = I/O, Sch name = R-IO8
|
| 174 |
|
|
#NET "PIO<8>" LOC = "E7"; # Bank = 0, Pin name = IO_L19N_0/VREF_0, Type = VREF, Sch name = R-IO9
|
| 175 |
|
|
#NET "PIO<9>" LOC = "A6"; # Bank = 0, Pin name = IO_L20N_0, Type = I/O, Sch name = R-IO10
|
| 176 |
|
|
#NET "PIO<10>" LOC = "C7"; # Bank = 0, Pin name = IO_L18P_0, Type = I/O, Sch name = R-IO11
|
| 177 |
|
|
#NET "PIO<11>" LOC = "F8"; # Bank = 0, Pin name = IO_L17N_0, Type = I/O, Sch name = R-IO12
|
| 178 |
|
|
#NET "PIO<12>" LOC = "D7"; # Bank = 0, Pin name = IO_L18N_0/VREF_0, Type = VREF, Sch name = R-IO13
|
| 179 |
|
|
#NET "PIO<13>" LOC = "E8"; # Bank = 0, Pin name = IO_L17P_0, Type = I/O, Sch name = R-IO14
|
| 180 |
|
|
#NET "PIO<14>" LOC = "E9"; # Bank = 0, Pin name = IO_L15P_0, Type = I/O, Sch name = R-IO15
|
| 181 |
|
|
#NET "PIO<15>" LOC = "C9"; # Bank = 0, Pin name = IO_L14P_0/GCLK10, Type = GCLK, Sch name = R-IO16
|
| 182 |
|
|
#NET "PIO<16>" LOC = "A8"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO17
|
| 183 |
|
|
#NET "PIO<17>" LOC = "G9"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO18
|
| 184 |
|
|
#NET "PIO<18>" LOC = "F9"; # Bank = 0, Pin name = IO_L15N_0, Type = I/O, Sch name = R-IO19
|
| 185 |
|
|
#NET "PIO<19>" LOC = "D10"; # Bank = 0, Pin name = IO_L11P_0/GCLK4, Type = GCLK, Sch name = R-IO20
|
| 186 |
|
|
#NET "PIO<20>" LOC = "A10"; # Bank = 0, Pin name = IO_L12N_0/GCLK7, Type = GCLK, Sch name = R-IO21
|
| 187 |
|
|
#NET "PIO<21>" LOC = "B10"; # Bank = 0, Pin name = IO_L12P_0/GCLK6, Type = GCLK, Sch name = R-IO22
|
| 188 |
|
|
#NET "PIO<22>" LOC = "A11"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO23
|
| 189 |
|
|
#NET "PIO<23>" LOC = "D11"; # Bank = 0, Pin name = IO_L09N_0, Type = I/O, Sch name = R-IO24
|
| 190 |
|
|
#NET "PIO<24>" LOC = "E10"; # Bank = 0, Pin name = IO_L11N_0/GCLK5, Type = GCLK, Sch name = R-IO25
|
| 191 |
|
|
#NET "PIO<25>" LOC = "B11"; # Bank = 0, Pin name = IO/VREF_0, Type = VREF, Sch name = R-IO26
|
| 192 |
|
|
#NET "PIO<26>" LOC = "C11"; # Bank = 0, Pin name = IO_L09P_0, Type = I/O, Sch name = R-IO27
|
| 193 |
|
|
#NET "PIO<27>" LOC = "E11"; # Bank = 0, Pin name = IO_L08P_0, Type = I/O, Sch name = R-IO28
|
| 194 |
|
|
#NET "PIO<28>" LOC = "F11"; # Bank = 0, Pin name = IO_L08N_0, Type = I/O, Sch name = R-IO29
|
| 195 |
|
|
#NET "PIO<29>" LOC = "E12"; # Bank = 0, Pin name = IO_L06N_0, Type = I/O, Sch name = R-IO30
|
| 196 |
|
|
#NET "PIO<30>" LOC = "F12"; # Bank = 0, Pin name = IO_L06P_0, Type = I/O, Sch name = R-IO31
|
| 197 |
|
|
#NET "PIO<31>" LOC = "A13"; # Bank = 0, Pin name = IO_L05P_0, Type = I/O, Sch name = R-IO32
|
| 198 |
|
|
#NET "PIO<32>" LOC = "B13"; # Bank = 0, Pin name = IO_L05N_0/VREF_0, Type = VREF, Sch name = R-IO33
|
| 199 |
|
|
#NET "PIO<33>" LOC = "E13"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO34
|
| 200 |
|
|
#NET "PIO<34>" LOC = "A14"; # Bank = 0, Pin name = IO_L04N_0, Type = I/O, Sch name = R-IO35
|
| 201 |
|
|
#NET "PIO<35>" LOC = "C14"; # Bank = 0, Pin name = IO_L03N_0/VREF_0, Type = VREF, Sch name = R-IO36
|
| 202 |
|
|
#NET "PIO<36>" LOC = "D14"; # Bank = 0, Pin name = IO_L03P_0, Type = I/O, Sch name = R-IO37
|
| 203 |
|
|
#NET "PIO<37>" LOC = "B14"; # Bank = 0, Pin name = IO_L04P_0, Type = I/O, Sch name = R-IO38
|
| 204 |
|
|
#NET "PIO<38>" LOC = "A16"; # Bank = 0, Pin name = IO_L01N_0, Type = I/O, Sch name = R-IO39
|
| 205 |
|
|
#NET "PIO<39>" LOC = "B16"; # Bank = 0, Pin name = IO_L01P_0, Type = I/O, Sch name = R-IO40
|
| 206 |
|
|
|
| 207 |
|
|
## 12 pin connectors
|
| 208 |
|
|
##JA
|
| 209 |
|
|
#NET "DEBUG_OUT<0>" LOC = "L15"; # Bank = 1, Pin name = IO_L09N_1/A11, Type = DUAL, Sch name = JA1
|
| 210 |
|
|
#NET "DEBUG_OUT<1>" LOC = "K12"; # Bank = 1, Pin name = IO_L11N_1/A9/RHCLK1, Type = RHCLK/DUAL, Sch name = JA2
|
| 211 |
|
|
#NET "DEBUG_OUT<2>" LOC = "L17"; # Bank = 1, Pin name = IO_L10N_1/VREF_1, Type = VREF, Sch name = JA3
|
| 212 |
|
|
#NET "DEBUG_OUT<3>" LOC = "M15"; # Bank = 1, Pin name = IO_L07P_1, Type = I/O, Sch name = JA4
|
| 213 |
|
|
#NET "DEBUG_OUT<4>" LOC = "K13"; # Bank = 1, Pin name = IO_L11P_1/A10/RHCLK0, Type = RHCLK/DUAL, Sch name = JA7
|
| 214 |
|
|
#NET "DEBUG_OUT<5>" LOC = "L16"; # Bank = 1, Pin name = IO_L09P_1/A12, Type = DUAL, Sch name = JA8
|
| 215 |
|
|
#NET "DEBUG_OUT<6>" LOC = "M14"; # Bank = 1, Pin name = IO_L05P_1, Type = I/O, Sch name = JA9
|
| 216 |
|
|
#NET "DEBUG_OUT<7>" LOC = "M16"; # Bank = 1, Pin name = IO_L07N_1, Type = I/O, Sch name = JA10
|
| 217 |
|
|
|
| 218 |
|
|
##JB
|
| 219 |
|
|
#NET "JB<0>" LOC = "M13"; # Bank = 1, Pin name = IO_L05N_1/VREF_1, Type = VREF, Sch name = JB1
|
| 220 |
|
|
#NET "JB<1>" LOC = "R18"; # Bank = 1, Pin name = IO_L02P_1/A14, Type = DUAL, Sch name = JB2
|
| 221 |
|
|
#NET "JB<2>" LOC = "R15"; # Bank = 1, Pin name = IO_L03P_1, Type = I/O, Sch name = JB3
|
| 222 |
|
|
#NET "JB<3>" LOC = "T17"; # Bank = 1, Pin name = IO_L01N_1/A15, Type = DUAL, Sch name = JB4
|
| 223 |
|
|
#NET "JB<4>" LOC = "P17"; # Bank = 1, Pin name = IO_L06P_1, Type = I/O, Sch name = JB7
|
| 224 |
|
|
#NET "JB<5>" LOC = "R16"; # Bank = 1, Pin name = IO_L03N_1/VREF_1, Type = VREF, Sch name = JB8
|
| 225 |
|
|
#NET "RX_IN" LOC = "T18"; # Bank = 1, Pin name = IO_L02N_1/A13, Type = DUAL, Sch name = JB9
|
| 226 |
|
|
#NET "TX_OUT" LOC = "U18"; # Bank = 1, Pin name = IO_L01P_1/A16, Type = DUAL, Sch name = JB10
|
| 227 |
|
|
|
| 228 |
|
|
##JC
|
| 229 |
|
|
#NET "JC<0>" LOC = "G15"; # Bank = 1, Pin name = IO_L18P_1, Type = I/O, Sch name = JC1
|
| 230 |
|
|
#NET "JC<1>" LOC = "J16"; # Bank = 1, Pin name = IO_L13N_1/A5/RHCLK5, Type = RHCLK/DUAL, Sch name = JC2
|
| 231 |
|
|
NET "SD_CS_OUT" LOC = "G13"; # Bank = 1, Pin name = IO_L20N_1, Type = I/O, Sch name = JC3
|
| 232 |
|
|
NET "SD_MOSI_OUT" LOC = "H16"; # Bank = 1, Pin name = IO_L16P_1, Type = I/O, Sch name = JC4
|
| 233 |
|
|
#NET "JC<4>" LOC = "H15"; # Bank = 1, Pin name = IO_L17N_1, Type = I/O, Sch name = JC7
|
| 234 |
|
|
NET "SD_CLK_OUT" LOC = "F14"; # Bank = 1, Pin name = IO_L21N_1, Type = I/O, Sch name = JC8
|
| 235 |
|
|
NET "SD_PRESENT_BAR_IN" LOC = "G16"; # Bank = 1, Pin name = IO_L18N_1, Type = I/O, Sch name = JC9
|
| 236 |
|
|
NET "SD_MISO_IN" LOC = "J12"; # Bank = 1, Pin name = IO_L15P_1/A2, Type = DUAL, Sch name = JC10
|
| 237 |
|
|
|
| 238 |
|
|
##JD - NOTE: For other JD pins see LD(3:0) above under "Leds"
|
| 239 |
|
|
#NET "JD<0>" LOC = "J13"; # Bank = 1, Pin name = IO_L15N_1/A1, Type = DUAL, Sch name = JD1
|
| 240 |
|
|
#NET "JD<1>" LOC = "M18"; # Bank = 1, Pin name = IO_L08N_1, Type = I/O, Sch name = JD2
|
| 241 |
|
|
#NET "JD<2>" LOC = "N18"; # Bank = 1, Pin name = IO_L08P_1, Type = I/O, Sch name = JD3
|
| 242 |
|
|
#NET "JD<3>" LOC = "P18"; # Bank = 1, Pin name = IO_L06N_1, Type = I/O, Sch name = JD4
|
| 243 |
|
|
|
| 244 |
|
|
## RS232 connector
|
| 245 |
|
|
#NET "RsRx" LOC = "U6"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = RS-RX
|
| 246 |
|
|
#NET "RsTx" LOC = "P9"; # Bank = 2, Pin name = IO, Type = I/O, Sch name = RS-TX
|
