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[/] [fat_32_file_parser/] [trunk/] [TB_lifo.vhd] - Blame information for rev 2

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Line No. Rev Author Line
1 2 craighaywo 
--------------------------------------------------------------------------------
2 
-- Company:
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-- Engineer:
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--
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-- Create Date:   22:03:37 11/18/2014
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-- Design Name:
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-- Module Name:   /home/craig/Documents/CW/Git_Repos/sd_card/TB_lifo.vhd
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-- Project Name:  hw_client
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- VHDL Test Bench Created by ISE for module: lifo
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--USE ieee.numeric_std.ALL;
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ENTITY TB_lifo IS
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END TB_lifo;
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ARCHITECTURE behavior OF TB_lifo IS
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    -- Component Declaration for the Unit Under Test (UUT)
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    COMPONENT lifo
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    PORT(
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         CLK_IN : IN  std_logic;
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         RESET_IN : IN  std_logic;
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         CACHE_ADDR_IN : IN  std_logic;
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         GOTO_CACHE_IN : IN  std_logic;
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         WR_DATA_IN : IN  std_logic_vector(7 downto 0);
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         WR_EN_IN : IN  std_logic;
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         RD_DATA_OUT : OUT  std_logic_vector(7 downto 0);
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         RD_EN_IN : IN  std_logic;
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         EMPTY_OUT : OUT  std_logic;
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         FULL_OUT : OUT  std_logic
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        );
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    END COMPONENT;
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   --Inputs
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   signal CLK_IN : std_logic := '0';
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   signal RESET_IN : std_logic := '0';
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   signal CACHE_ADDR_IN : std_logic := '0';
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   signal GOTO_CACHE_IN : std_logic := '0';
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   signal WR_DATA_IN : std_logic_vector(7 downto 0) := (others => '0');
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   signal WR_EN_IN : std_logic := '0';
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   signal RD_EN_IN : std_logic := '0';
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        --Outputs
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   signal RD_DATA_OUT : std_logic_vector(7 downto 0);
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   signal EMPTY_OUT : std_logic;
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   signal FULL_OUT : std_logic;
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   -- Clock period definitions
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   constant CLK_IN_period : time := 10 ns;
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BEGIN
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        -- Instantiate the Unit Under Test (UUT)
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   uut: lifo PORT MAP (
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          CLK_IN => CLK_IN,
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          RESET_IN => RESET_IN,
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          CACHE_ADDR_IN => CACHE_ADDR_IN,
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          GOTO_CACHE_IN => GOTO_CACHE_IN,
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          WR_DATA_IN => WR_DATA_IN,
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          WR_EN_IN => WR_EN_IN,
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          RD_DATA_OUT => RD_DATA_OUT,
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          RD_EN_IN => RD_EN_IN,
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          EMPTY_OUT => EMPTY_OUT,
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          FULL_OUT => FULL_OUT
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        );
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   -- Clock process definitions
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   CLK_IN_process :process
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   begin
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                CLK_IN <= '0';
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                wait for CLK_IN_period/2;
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                CLK_IN <= '1';
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                wait for CLK_IN_period/2;
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   end process;
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--   stim_proc: process
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--   begin
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--
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--              wait for CLK_IN_period*10;
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--
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--              WR_DATA_IN <= X"81";
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--              WR_EN_IN <= '1';
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--              wait for CLK_IN_period;
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--              WR_EN_IN <= '0';
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--              wait for CLK_IN_period * 5;
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--
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--              WR_DATA_IN <= X"82";
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--              WR_EN_IN <= '1';
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--              wait for CLK_IN_period;
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--              WR_EN_IN <= '0';
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--              wait for CLK_IN_period * 5;
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--
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--              WR_DATA_IN <= X"83";
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--              WR_EN_IN <= '1';
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--              wait for CLK_IN_period;
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--              WR_EN_IN <= '0';
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--              wait for CLK_IN_period * 25;
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--
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--              RD_EN_IN <= '1';
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--              wait for CLK_IN_period;
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--              RD_EN_IN <= '0';
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--              wait for CLK_IN_period * 5;
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--
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--              RD_EN_IN <= '1';
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--              wait for CLK_IN_period;
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--              RD_EN_IN <= '0';
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--              wait for CLK_IN_period * 5;
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--
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--              RD_EN_IN <= '1';
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--              wait for CLK_IN_period;
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--              RD_EN_IN <= '0';
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--              wait for CLK_IN_period * 5;
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--
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--      wait;
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--   end process;
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   -- Stimulus process
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   stim_proc: process
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   begin
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                wait for CLK_IN_period*10;
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                WR_DATA_IN <= X"01";
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                WR_EN_IN <= '1';
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                wait for CLK_IN_period;
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                WR_EN_IN <= '0';
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                WR_DATA_IN <= X"02";
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                WR_EN_IN <= '1';
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                wait for CLK_IN_period;
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                WR_EN_IN <= '0';
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                WR_DATA_IN <= X"03";
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                WR_EN_IN <= '1';
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                wait for CLK_IN_period;
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                WR_EN_IN <= '0';
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                WR_DATA_IN <= X"11";
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                WR_EN_IN <= '1';
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                wait for CLK_IN_period;
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                WR_EN_IN <= '0';
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                WR_DATA_IN <= X"12";
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                WR_EN_IN <= '1';
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                wait for CLK_IN_period;
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                WR_DATA_IN <= X"13";
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                WR_EN_IN <= '1';
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                wait for CLK_IN_period;
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                WR_DATA_IN <= X"14";
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                WR_EN_IN <= '1';
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                wait for CLK_IN_period;
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                WR_EN_IN <= '0';
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                wait for CLK_IN_period;
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                RD_EN_IN <= '1';
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                wait for CLK_IN_period;
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                RD_EN_IN <= '0';
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                wait for CLK_IN_period;
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                RD_EN_IN <= '1';
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                wait for CLK_IN_period;
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                RD_EN_IN <= '0';
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                wait for CLK_IN_period;
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                RD_EN_IN <= '1';
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                wait for CLK_IN_period;
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                RD_EN_IN <= '0';
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                wait for CLK_IN_period;
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                RD_EN_IN <= '1';
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                wait for CLK_IN_period;
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                RD_EN_IN <= '0';
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                wait for CLK_IN_period * 2;
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                RD_EN_IN <= '0';
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                wait for CLK_IN_period * 4;
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                CACHE_ADDR_IN <= '1';
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                wait for CLK_IN_period;
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                CACHE_ADDR_IN <= '0';
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                RD_EN_IN <= '1';
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                wait for CLK_IN_period * 20;
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                RD_EN_IN <= '0';
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                wait for CLK_IN_period;
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                GOTO_CACHE_IN <= '1';
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                wait for CLK_IN_period;
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                GOTO_CACHE_IN <= '0';
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                wait for CLK_IN_period * 20;
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                RD_EN_IN <= '1';
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                wait for CLK_IN_period * 20;
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                RD_EN_IN <= '0';
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                wait for CLK_IN_period;
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                GOTO_CACHE_IN <= '1';
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                wait for CLK_IN_period;
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                GOTO_CACHE_IN <= '0';
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                wait for CLK_IN_period;
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                RESET_IN <= '1';
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                wait for CLK_IN_period;
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                RESET_IN <= '0';
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      wait;
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   end process;
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END;

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