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CHANGE LOG for LogiCORE Block Memory Generator V7.2
 
                Core name: Xilinx LogiCORE Block Memory Generator
                Version: 7.2
                Release: ISE 14.2 / Vivado 2012.2
                Release Date: July 25, 2012
 
--------------------------------------------------------------------------------
 
Table of Contents
 
1. INTRODUCTION
2. DEVICE SUPPORT
3. NEW FEATURES HISTORY
4. RESOLVED ISSUES
5. KNOWN ISSUES & LIMITATIONS
6. TECHNICAL SUPPORT & FEEDBACK
7. CORE RELEASE HISTORY
8. LEGAL DISCLAIMER
 
--------------------------------------------------------------------------------
 
 
1. INTRODUCTION
 
For installation instructions for this release, please go to:
 
  <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A>
 
For system requirements:
 
   <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A>
 
This file contains release notes for the Xilinx LogiCORE IP Block Memory Generator v7.2
solution. For the latest core updates, see the product page at:
 
 <A HREF="http://www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm">www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm</A>
 
 
................................................................................
 
 
2. DEVICE SUPPORT
 
 
  2.1 ISE
 
  The following device families are supported by the core for this release.
 
  All 7 Series devices
  Zynq-7000 devices
  All Virtex-6 devices
  All Spartan-6 devices
  All Virtex-5 devices
  All Spartan-3 devices
  All Virtex-4 devices
 
 
  2.2 Vivado
  All 7 Series devices
  Zynq-7000 devices
 
................................................................................
 
3. NEW FEATURES HISTORY
 
 
  3.1 ISE
 
    - ISE 14.2 software support
 
 
  3.2 Vivado
 
    - 2012.2 software support
 
 
................................................................................
 
 
4. RESOLVED ISSUES
 
 
The following issues are resolved in Block Memory Generator v7.2:
 
  4.1 ISE
 
 
  4.2 Vivado
 
 
................................................................................
 
 
5. KNOWN ISSUES & LIMITATIONS
 
 
  5.1 ISE
 
    The following are known issues for v7.2 of this core at time of release:
 
    1. Virtex-6 and Spartan-6: BRAM Memory collision error, when the user selects TDP (write_mode= Read First)
      Work around: The user must review the possible scenarios that causes the collission and revise
       their design to avoid those situations.
      - CR588505
 
      Note: Refer to UG383, 'Conflict Avoidance' section when using TDP Memory - with
            Write Mode = Read First in conjunction with asynchronous clocking
 
    2. Power estimation figures in the datasheet are preliminary for Virtex-5 and Spartan-3.
 
    3. Core does not generate for large memories. Depending on the
       machine the ISE CORE Generator software runs on, the maximum size of the memory that
       can be generated will vary.  For example, a Dual Pentium-4 server
       with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes
      - CR 415768
      - AR 24034
 
 
  5.2 Vivado
 
    The following are known issues for v7.2 of this core at time of release:
 
    1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen
       ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work.
 
       CR 665836
 
  The most recent information, including known issues, workarounds, and resolutions for
  this version is provided in the IP Release Notes User Guide located at
 
         <A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A>
 
................................................................................
 
 
6. TECHNICAL SUPPORT & FEEDBACK
 
To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A>
Questions are routed to a team with expertise using this product.
 
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
 
 
 
7. CORE RELEASE HISTORY
 
Date        By            Version      Description
================================================================================
07/25/2012  Xilinx, Inc.  7.2          ISE 14.2 and Vivado 2012.2 support;
04/24/2012  Xilinx, Inc.  7.1          ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
01/18/2011  Xilinx, Inc.  6.3          ISE 13.4 support;Artix7L*, AArtix-7* device support
06/22/2011  Xilinx, Inc.  6.2          ISE 13.2 support;Virtex-7L,Kintex-7L,Artix7 and Zynq-7000* device support;
03/01/2011  Xilinx, Inc.  6.1          ISE 13.1 support and Virtex-7 and Kintex-7 device support; AXI4/AXI4-Lite Support
09/21/2010  Xilinx, Inc.  4.3          ISE 12.3 support
07/23/2010  Xilinx, Inc.  4.2          ISE 12.2 support
04/19/2010  Xilinx, Inc.  4.1          ISE 12.1 support
03/09/2010  Xilinx, Inc.  3.3 rev 2    Fix for V6 Memory collision issue
12/02/2009  Xilinx, Inc.  3.3 rev 1    ISE 11.4 support; Spartan-6 Low Power
                                       Device support; Automotive Spartan 3A
                                       DSP device support
09/16/2009  Xilinx, Inc.  3.3          Revised to v3.3
06/24/2009  Xilinx, Inc.  3.2          Revised to v3.2
04/24/2009  Xilinx, Inc.  3.1          Revised to v3.1
09/19/2008  Xilinx, Inc.  2.8          Revised to v2.8
03/24/2008  Xilinx, Inc.  2.7          10.1 support; Revised to v2.7
10/03/2007  Xilinx, Inc.  2.6          Revised to v2.6
07/2007     Xilinx, Inc.  2.5          Revised to v2.5
04/2007     Xilinx, Inc.  2.4          Revised to v2.4 rev 1
02/2007     Xilinx, Inc.  2.4          Revised to v2.4
11/2006     Xilinx, Inc.  2.3          Revised to v2.3
09/2006     Xilinx, Inc.  2.2          Revised to v2.2
06/2006     Xilinx, Inc.  2.1          Revised to v2.1
01/2006     Xilinx, Inc.  1.1          Initial release
================================================================================
 
8. Legal Disclaimer
 
(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
 
  This file contains confidential and proprietary information
  of Xilinx, Inc. and is protected under U.S. and
  international copyright and other intellectual property
  laws.
 
  DISCLAIMER
  This disclaimer is not a license and does not grant any
  rights to the materials distributed herewith. Except as
  otherwise provided in a valid license issued to you by
  Xilinx, and to the maximum extent permitted by applicable
  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
  (2) Xilinx shall not be liable (whether in contract or tort,
  including negligence, or under any other theory of
  liability) for any loss or damage of any kind or nature
  related to, arising under or in connection with these
  materials, including for any direct, or any indirect,
  special, incidental, or consequential loss or damage
  (including loss of data, profits, goodwill, or any type of
  loss or damage suffered as a result of any action brought
  by a third party) even if such damage or loss was
  reasonably foreseeable or Xilinx had been advised of the
  possibility of the same.
 
  CRITICAL APPLICATIONS
  Xilinx products are not designed or intended to be fail-
  safe, or for use in any application requiring fail-safe
  performance, such as life-support or safety devices or
  systems, Class III medical devices, nuclear facilities,
  applications related to the deployment of airbags, or any
  other applications that could lead to death, personal
  injury, or severe property or environmental damage
  (individually and collectively, "Critical
  Applications"). Customer assumes the sole risk and
  liability of any use of Xilinx products in Critical
  Applications, subject only to applicable laws and
  regulations governing limitations on product liability.
 
  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
  PART OF THIS FILE AT ALL TIMES.
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Line No.	Rev	Author	Line
1	2	craighaywo	`<HTML>`
2			`<HEAD>`
3			`<TITLE>blk_mem_gen_v7_2_vinfo</TITLE>`
4			`<META HTTP-EQUIV="Content-Type" CONTENT="text/plain;CHARSET=iso-8859-1">`
5			`</HEAD>`
6			`<BODY>`
7			`<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1">`
8			`CHANGE LOG for LogiCORE Block Memory Generator V7.2`
9
10			`Core name: Xilinx LogiCORE Block Memory Generator`
11			`Version: 7.2`
12			`Release: ISE 14.2 / Vivado 2012.2`
13			`Release Date: July 25, 2012`
14
15			`--------------------------------------------------------------------------------`
16
17			`Table of Contents`
18
19			`1. INTRODUCTION`
20			`2. DEVICE SUPPORT`
21			`3. NEW FEATURES HISTORY`
22			`4. RESOLVED ISSUES`
23			`5. KNOWN ISSUES & LIMITATIONS`
24			`6. TECHNICAL SUPPORT & FEEDBACK`
25			`7. CORE RELEASE HISTORY`
26			`8. LEGAL DISCLAIMER`
27
28			`--------------------------------------------------------------------------------`
29
30
31			`1. INTRODUCTION`
32
33			`For installation instructions for this release, please go to:`
34
35			`<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A>`
36
37			`For system requirements:`
38
39			`<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A>`
40
41			`This file contains release notes for the Xilinx LogiCORE IP Block Memory Generator v7.2`
42			`solution. For the latest core updates, see the product page at:`
43
44			`<A HREF="http://www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm">www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm</A>`
45
46
47			`................................................................................`
48
49
50			`2. DEVICE SUPPORT`
51
52
53			`2.1 ISE`
54
55			`The following device families are supported by the core for this release.`
56
57			`All 7 Series devices`
58			`Zynq-7000 devices`
59			`All Virtex-6 devices`
60			`All Spartan-6 devices`
61			`All Virtex-5 devices`
62			`All Spartan-3 devices`
63			`All Virtex-4 devices`
64
65
66			`2.2 Vivado`
67			`All 7 Series devices`
68			`Zynq-7000 devices`
69
70			`................................................................................`
71
72			`3. NEW FEATURES HISTORY`
73
74
75			`3.1 ISE`
76
77			`- ISE 14.2 software support`
78
79
80			`3.2 Vivado`
81
82			`- 2012.2 software support`
83
84
85			`................................................................................`
86
87
88			`4. RESOLVED ISSUES`
89
90
91			`The following issues are resolved in Block Memory Generator v7.2:`
92
93			`4.1 ISE`
94
95
96			`4.2 Vivado`
97
98
99			`................................................................................`
100
101
102			`5. KNOWN ISSUES & LIMITATIONS`
103
104
105			`5.1 ISE`
106
107			`The following are known issues for v7.2 of this core at time of release:`
108
109			`1. Virtex-6 and Spartan-6: BRAM Memory collision error, when the user selects TDP (write_mode= Read First)`
110			`Work around: The user must review the possible scenarios that causes the collission and revise`
111			`their design to avoid those situations.`
112			`- CR588505`
113
114			`Note: Refer to UG383, 'Conflict Avoidance' section when using TDP Memory - with`
115			`Write Mode = Read First in conjunction with asynchronous clocking`
116
117			`2. Power estimation figures in the datasheet are preliminary for Virtex-5 and Spartan-3.`
118
119			`3. Core does not generate for large memories. Depending on the`
120			`machine the ISE CORE Generator software runs on, the maximum size of the memory that`
121			`can be generated will vary. For example, a Dual Pentium-4 server`
122			`with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes`
123			`- CR 415768`
124			`- AR 24034`
125
126
127			`5.2 Vivado`
128
129			`The following are known issues for v7.2 of this core at time of release:`
130
131			`1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen`
132			`ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work.`
133
134			`CR 665836`
135
136			`The most recent information, including known issues, workarounds, and resolutions for`
137			`this version is provided in the IP Release Notes User Guide located at`
138
139			`<A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A>`
140
141			`................................................................................`
142
143
144			`6. TECHNICAL SUPPORT & FEEDBACK`
145
146			`To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A>`
147			`Questions are routed to a team with expertise using this product.`
148
149			`Xilinx provides technical support for use of this product when used`
150			`according to the guidelines described in the core documentation, and`
151			`cannot guarantee timing, functionality, or support of this product for`
152			`designs that do not follow specified guidelines.`
153
154
155
156			`7. CORE RELEASE HISTORY`
157
158			`Date By Version Description`
159			`================================================================================`
160			`07/25/2012 Xilinx, Inc. 7.2 ISE 14.2 and Vivado 2012.2 support;`
161			`04/24/2012 Xilinx, Inc. 7.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support`
162			`01/18/2011 Xilinx, Inc. 6.3 ISE 13.4 support;Artix7L, AArtix-7 device support`
163			`06/22/2011 Xilinx, Inc. 6.2 ISE 13.2 support;Virtex-7L,Kintex-7L,Artix7 and Zynq-7000* device support;`
164			`03/01/2011 Xilinx, Inc. 6.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; AXI4/AXI4-Lite Support`
165			`09/21/2010 Xilinx, Inc. 4.3 ISE 12.3 support`
166			`07/23/2010 Xilinx, Inc. 4.2 ISE 12.2 support`
167			`04/19/2010 Xilinx, Inc. 4.1 ISE 12.1 support`
168			`03/09/2010 Xilinx, Inc. 3.3 rev 2 Fix for V6 Memory collision issue`
169			`12/02/2009 Xilinx, Inc. 3.3 rev 1 ISE 11.4 support; Spartan-6 Low Power`
170			`Device support; Automotive Spartan 3A`
171			`DSP device support`
172			`09/16/2009 Xilinx, Inc. 3.3 Revised to v3.3`
173			`06/24/2009 Xilinx, Inc. 3.2 Revised to v3.2`
174			`04/24/2009 Xilinx, Inc. 3.1 Revised to v3.1`
175			`09/19/2008 Xilinx, Inc. 2.8 Revised to v2.8`
176			`03/24/2008 Xilinx, Inc. 2.7 10.1 support; Revised to v2.7`
177			`10/03/2007 Xilinx, Inc. 2.6 Revised to v2.6`
178			`07/2007 Xilinx, Inc. 2.5 Revised to v2.5`
179			`04/2007 Xilinx, Inc. 2.4 Revised to v2.4 rev 1`
180			`02/2007 Xilinx, Inc. 2.4 Revised to v2.4`
181			`11/2006 Xilinx, Inc. 2.3 Revised to v2.3`
182			`09/2006 Xilinx, Inc. 2.2 Revised to v2.2`
183			`06/2006 Xilinx, Inc. 2.1 Revised to v2.1`
184			`01/2006 Xilinx, Inc. 1.1 Initial release`
185			`================================================================================`
186
187			`8. Legal Disclaimer`
188
189			`(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.`
190
191			`This file contains confidential and proprietary information`
192			`of Xilinx, Inc. and is protected under U.S. and`
193			`international copyright and other intellectual property`
194			`laws.`
195
196			`DISCLAIMER`
197			`This disclaimer is not a license and does not grant any`
198			`rights to the materials distributed herewith. Except as`
199			`otherwise provided in a valid license issued to you by`
200			`Xilinx, and to the maximum extent permitted by applicable`
201			`law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND`
202			`WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES`
203			`AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING`
204			`BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-`
205			`INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and`
206			`(2) Xilinx shall not be liable (whether in contract or tort,`
207			`including negligence, or under any other theory of`
208			`liability) for any loss or damage of any kind or nature`
209			`related to, arising under or in connection with these`
210			`materials, including for any direct, or any indirect,`
211			`special, incidental, or consequential loss or damage`
212			`(including loss of data, profits, goodwill, or any type of`
213			`loss or damage suffered as a result of any action brought`
214			`by a third party) even if such damage or loss was`
215			`reasonably foreseeable or Xilinx had been advised of the`
216			`possibility of the same.`
217
218			`CRITICAL APPLICATIONS`
219			`Xilinx products are not designed or intended to be fail-`
220			`safe, or for use in any application requiring fail-safe`
221			`performance, such as life-support or safety devices or`
222			`systems, Class III medical devices, nuclear facilities,`
223			`applications related to the deployment of airbags, or any`
224			`other applications that could lead to death, personal`
225			`injury, or severe property or environmental damage`
226			`(individually and collectively, "Critical`
227			`Applications"). Customer assumes the sole risk and`
228			`liability of any use of Xilinx products in Critical`
229			`Applications, subject only to applicable laws and`
230			`regulations governing limitations on product liability.`
231
232			`THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS`
233			`PART OF THIS FILE AT ALL TIMES.`
234			`</FONT>`
235			`</PRE>`
236			`</BODY>`
237			`</HTML>`