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craighaywo |
Welcome to Xilinx CORE Generator.
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Help system initialized.
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The IP Catalog has been reloaded.
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Opening project file
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/home/craig/Documents/CW/Git_Repos/hw_client/ipcore_dir/coregen.cgp.
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Recustomize and Generate (Under Current Project Settings)INFO:sim:172 - Generating IP...
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Applying current project options...
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Finished applying current project options.
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ERROR:sim - Unable to find /home/craig/Documents/craigs/projectV/nexys2/ps2
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ERROR:sim - keyboard/ps2keyboard/lat0-12.coe
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ERROR:sim - Coregen is looking for
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/home/craig/Documents/craigs/projectV/nexys2/ps2
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ERROR:sim - keyboard/ps2keyboard/lat0-12.coe
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ERROR:sim - Unable to find /home/craig/Documents/craigs/projectV/nexys2/ps2
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ERROR:sim - keyboard/ps2keyboard/lat0-12.coe
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ERROR:sim - Coregen is looking for
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/home/craig/Documents/craigs/projectV/nexys2/ps2
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ERROR:sim - keyboard/ps2keyboard/lat0-12.coe
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ERROR:sim - An invalid core configuration has been detected during
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ERROR:sim - Customization. Core parameters will be reset to their default
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values.
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Resolving generics for 'FONT_MEM'...
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Applying external generics to 'FONT_MEM'...
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Delivering associated files for 'FONT_MEM'...
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WARNING:sim - Component blk_mem_gen_v7_2 does not have a valid model name for
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VHDL synthesis
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Delivering EJava files for 'FONT_MEM'...
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Generating implementation netlist for 'FONT_MEM'...
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INFO:sim - Pre-processing HDL files for 'FONT_MEM'...
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Running synthesis for 'FONT_MEM'
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Running ngcbuild...
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Writing VHO instantiation template for 'FONT_MEM'...
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Writing VHDL instantiation wrapper for 'FONT_MEM'...
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Writing VHDL behavioral simulation model for 'FONT_MEM'...
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WARNING:sim - No files were found for the view xilinx_documentation
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Generating ASY schematic symbol...
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INFO:sim:949 - Finished generation of ASY schematic symbol.
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Generating metadata file...
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Generating ISE project file for 'FONT_MEM'...
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Generating ISE project...
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XCO file found: FONT_MEM.xco
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XMDF file found: FONT_MEM_xmdf.tcl
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Adding
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/home/craig/Documents/CW/Git_Repos/hw_client/ipcore_dir/tmp/_cg/FONT_MEM.asy
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-view all -origin_type imported
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Adding
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/home/craig/Documents/CW/Git_Repos/hw_client/ipcore_dir/tmp/_cg/FONT_MEM.ngc
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-view all -origin_type created
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Checking file
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"/home/craig/Documents/CW/Git_Repos/hw_client/ipcore_dir/tmp/_cg/FONT_MEM.ngc"
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for project device match ...
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File
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"/home/craig/Documents/CW/Git_Repos/hw_client/ipcore_dir/tmp/_cg/FONT_MEM.ngc"
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device information matches project device.
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Adding
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/home/craig/Documents/CW/Git_Repos/hw_client/ipcore_dir/tmp/_cg/FONT_MEM.vhd
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-view all -origin_type created
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INFO:HDLCompiler:1061 - Parsing VHDL file
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"/home/craig/Documents/CW/Git_Repos/hw_client/ipcore_dir/tmp/_cg/FONT_MEM.vhd
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" into library work
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INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
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Adding
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/home/craig/Documents/CW/Git_Repos/hw_client/ipcore_dir/tmp/_cg/FONT_MEM.vho
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-view all -origin_type imported
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Adding
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/home/craig/Documents/CW/Git_Repos/hw_client/ipcore_dir/tmp/_cg/FONT_MEM_synth.v
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hd -view all -origin_type created
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INFO:HDLCompiler:1061 - Parsing VHDL file
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"/home/craig/Documents/CW/Git_Repos/hw_client/ipcore_dir/tmp/_cg/FONT_MEM_syn
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th.vhd" into library work
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INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
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WARNING:ProjectMgmt - Duplicate Design Unit 'FONT_MEM' found in library 'work'
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WARNING:ProjectMgmt -
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"/home/craig/Documents/CW/Git_Repos/hw_client/ipcore_dir/tmp/_cg/FONT_MEM.vhd
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" line 43 (active)
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WARNING:ProjectMgmt -
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"/home/craig/Documents/CW/Git_Repos/hw_client/ipcore_dir/tmp/_cg/FONT_MEM_syn
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th.vhd" line 64
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INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
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Please set the new top explicitly by running the "project set top" command.
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To re-calculate the new top automatically, set the "Auto Implementation Top"
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property to true.
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Top level has been set to "/FONT_MEM"
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Generating README file...
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Generating FLIST file...
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INFO:sim:948 - Finished FLIST file generation.
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Launching README viewer...
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Moving files to output directory...
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Finished moving files to output directory
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Saved CGP file for project 'coregen'.
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Closed project file.
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