| 1 |
2 |
craighaywo |
----------------------------------------------------------------------------------
|
| 2 |
|
|
-- Company:
|
| 3 |
|
|
-- Engineer:
|
| 4 |
|
|
--
|
| 5 |
|
|
-- Create Date: 21:09:44 11/18/2014
|
| 6 |
|
|
-- Design Name:
|
| 7 |
|
|
-- Module Name: lifo - Behavioral
|
| 8 |
|
|
-- Project Name:
|
| 9 |
|
|
-- Target Devices:
|
| 10 |
|
|
-- Tool versions:
|
| 11 |
|
|
-- Description:
|
| 12 |
|
|
--
|
| 13 |
|
|
-- Dependencies:
|
| 14 |
|
|
--
|
| 15 |
|
|
-- Revision:
|
| 16 |
|
|
-- Revision 0.01 - File Created
|
| 17 |
|
|
-- Additional Comments:
|
| 18 |
|
|
--
|
| 19 |
|
|
----------------------------------------------------------------------------------
|
| 20 |
|
|
library IEEE;
|
| 21 |
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
| 22 |
|
|
use IEEE.NUMERIC_STD.ALL;
|
| 23 |
|
|
|
| 24 |
|
|
-- Uncomment the following library declaration if instantiating
|
| 25 |
|
|
-- any Xilinx primitives in this code.
|
| 26 |
|
|
--library UNISIM;
|
| 27 |
|
|
--use UNISIM.VComponents.all;
|
| 28 |
|
|
|
| 29 |
|
|
entity lifo is
|
| 30 |
|
|
Generic ( G_LOG2_DEPTH : natural := 6;
|
| 31 |
|
|
G_DATA_SIZE : natural := 8 ); -- LOG2(lifo depth)
|
| 32 |
|
|
Port ( CLK_IN : in STD_LOGIC;
|
| 33 |
|
|
RESET_IN : in STD_LOGIC;
|
| 34 |
|
|
CACHE_ADDR_IN : in STD_LOGIC;
|
| 35 |
|
|
GOTO_CACHE_IN : in STD_LOGIC;
|
| 36 |
|
|
WR_DATA_IN : in STD_LOGIC_VECTOR ((G_DATA_SIZE - 1) downto 0);
|
| 37 |
|
|
WR_EN_IN : in STD_LOGIC;
|
| 38 |
|
|
RD_DATA_OUT : out STD_LOGIC_VECTOR ((G_DATA_SIZE - 1) downto 0);
|
| 39 |
|
|
RD_EN_IN : in STD_LOGIC;
|
| 40 |
|
|
EMPTY_OUT : out STD_LOGIC;
|
| 41 |
|
|
FULL_OUT : out STD_LOGIC);
|
| 42 |
|
|
|
| 43 |
|
|
attribute ram_style : string;
|
| 44 |
|
|
attribute ram_style of lifo : entity is "block";
|
| 45 |
|
|
|
| 46 |
|
|
end lifo;
|
| 47 |
|
|
|
| 48 |
|
|
architecture Behavioral of lifo is
|
| 49 |
|
|
|
| 50 |
|
|
COMPONENT TDP_RAM
|
| 51 |
|
|
Generic (G_DATA_A_SIZE :natural :=32;
|
| 52 |
|
|
G_ADDR_A_SIZE :natural :=9;
|
| 53 |
|
|
G_RELATION :natural :=3;
|
| 54 |
|
|
G_INIT_FILE :string :="");--log2(SIZE_A/SIZE_B)
|
| 55 |
|
|
Port ( CLK_A_IN : in STD_LOGIC;
|
| 56 |
|
|
WE_A_IN : in STD_LOGIC;
|
| 57 |
|
|
ADDR_A_IN : in STD_LOGIC_VECTOR (G_ADDR_A_SIZE-1 downto 0);
|
| 58 |
|
|
DATA_A_IN : in STD_LOGIC_VECTOR (G_DATA_A_SIZE-1 downto 0);
|
| 59 |
|
|
DATA_A_OUT : out STD_LOGIC_VECTOR (G_DATA_A_SIZE-1 downto 0);
|
| 60 |
|
|
CLK_B_IN : in STD_LOGIC;
|
| 61 |
|
|
WE_B_IN : in STD_LOGIC;
|
| 62 |
|
|
ADDR_B_IN : in STD_LOGIC_VECTOR (G_ADDR_A_SIZE+G_RELATION-1 downto 0);
|
| 63 |
|
|
DATA_B_IN : in STD_LOGIC_VECTOR (G_DATA_A_SIZE/(2**G_RELATION)-1 downto 0);
|
| 64 |
|
|
DATA_B_OUT : out STD_LOGIC_VECTOR (G_DATA_A_SIZE/(2**G_RELATION)-1 downto 0));
|
| 65 |
|
|
END COMPONENT;
|
| 66 |
|
|
|
| 67 |
|
|
subtype slv is std_logic_vector;
|
| 68 |
|
|
|
| 69 |
|
|
constant C_max : unsigned((G_LOG2_DEPTH - 1) downto 0) := (others => '1');
|
| 70 |
|
|
constant C_min : unsigned((G_LOG2_DEPTH - 1) downto 0) := (others => '0');
|
| 71 |
|
|
|
| 72 |
|
|
signal wr_addr : unsigned((G_LOG2_DEPTH - 1) downto 0) := C_min;
|
| 73 |
|
|
signal rd_addr : unsigned((G_LOG2_DEPTH - 1) downto 0) := C_min;
|
| 74 |
|
|
signal cached_addr : unsigned((G_LOG2_DEPTH - 1) downto 0) := (others => '0');
|
| 75 |
|
|
signal zeros : std_logic_vector((G_DATA_SIZE - 1) downto 0) := (others => '0');
|
| 76 |
|
|
|
| 77 |
|
|
begin
|
| 78 |
|
|
|
| 79 |
|
|
process(CLK_IN)
|
| 80 |
|
|
begin
|
| 81 |
|
|
if rising_edge(CLK_IN) then
|
| 82 |
|
|
if RESET_IN = '1' then
|
| 83 |
|
|
wr_addr <= (others => '0');
|
| 84 |
|
|
rd_addr <= (others => '0');
|
| 85 |
|
|
elsif GOTO_CACHE_IN = '0' then
|
| 86 |
|
|
if WR_EN_IN = '1' then
|
| 87 |
|
|
if wr_addr /= C_max then
|
| 88 |
|
|
wr_addr <= wr_addr + 1;
|
| 89 |
|
|
end if;
|
| 90 |
|
|
if rd_addr /= C_max and wr_addr /= C_min then
|
| 91 |
|
|
rd_addr <= rd_addr + 1;
|
| 92 |
|
|
end if;
|
| 93 |
|
|
elsif RD_EN_IN = '1' then
|
| 94 |
|
|
if rd_addr /= C_min then
|
| 95 |
|
|
rd_addr <= rd_addr - 1;
|
| 96 |
|
|
end if;
|
| 97 |
|
|
if wr_addr /= C_min and rd_addr /= C_max then
|
| 98 |
|
|
wr_addr <= wr_addr - 1;
|
| 99 |
|
|
end if;
|
| 100 |
|
|
end if;
|
| 101 |
|
|
else
|
| 102 |
|
|
wr_addr <= cached_addr + 1;
|
| 103 |
|
|
rd_addr <= cached_addr;
|
| 104 |
|
|
end if;
|
| 105 |
|
|
end if;
|
| 106 |
|
|
end process;
|
| 107 |
|
|
|
| 108 |
|
|
process(CLK_IN)
|
| 109 |
|
|
begin
|
| 110 |
|
|
if rising_edge(CLK_IN) then
|
| 111 |
|
|
if CACHE_ADDR_IN = '1' then
|
| 112 |
|
|
cached_addr <= rd_addr;
|
| 113 |
|
|
elsif RESET_IN = '1' then
|
| 114 |
|
|
cached_addr <= (others => '0');
|
| 115 |
|
|
end if;
|
| 116 |
|
|
end if;
|
| 117 |
|
|
end process;
|
| 118 |
|
|
|
| 119 |
|
|
process(CLK_IN)
|
| 120 |
|
|
begin
|
| 121 |
|
|
if rising_edge(CLK_IN) then
|
| 122 |
|
|
if RESET_IN = '1' then
|
| 123 |
|
|
EMPTY_OUT <= '1';
|
| 124 |
|
|
elsif WR_EN_IN = '1' or GOTO_CACHE_IN = '1' then
|
| 125 |
|
|
EMPTY_OUT <= '0';
|
| 126 |
|
|
elsif wr_addr = C_min then
|
| 127 |
|
|
EMPTY_OUT <= '1';
|
| 128 |
|
|
end if;
|
| 129 |
|
|
end if;
|
| 130 |
|
|
end process;
|
| 131 |
|
|
|
| 132 |
|
|
process(CLK_IN)
|
| 133 |
|
|
begin
|
| 134 |
|
|
if rising_edge(CLK_IN) then
|
| 135 |
|
|
if RD_EN_IN = '1' then
|
| 136 |
|
|
FULL_OUT <= '0';
|
| 137 |
|
|
elsif rd_addr = C_max then
|
| 138 |
|
|
FULL_OUT <= '1';
|
| 139 |
|
|
end if;
|
| 140 |
|
|
end if;
|
| 141 |
|
|
end process;
|
| 142 |
|
|
|
| 143 |
|
|
TDP_RAM_Inst : TDP_RAM
|
| 144 |
|
|
Generic Map ( G_DATA_A_SIZE => G_DATA_SIZE,
|
| 145 |
|
|
G_ADDR_A_SIZE => G_LOG2_DEPTH,
|
| 146 |
|
|
G_RELATION => 0, --log2(SIZE_A/SIZE_B)
|
| 147 |
|
|
G_INIT_FILE => "")
|
| 148 |
|
|
Port Map ( CLK_A_IN => CLK_IN,
|
| 149 |
|
|
WE_A_IN => WR_EN_IN,
|
| 150 |
|
|
ADDR_A_IN => slv(wr_addr),
|
| 151 |
|
|
DATA_A_IN => WR_DATA_IN,
|
| 152 |
|
|
DATA_A_OUT => open,
|
| 153 |
|
|
CLK_B_IN => CLK_IN,
|
| 154 |
|
|
WE_B_IN => '0',
|
| 155 |
|
|
ADDR_B_IN => slv(rd_addr),
|
| 156 |
|
|
DATA_B_IN => zeros,
|
| 157 |
|
|
DATA_B_OUT => RD_DATA_OUT);
|
| 158 |
|
|
|
| 159 |
|
|
end Behavioral;
|
| 160 |
|
|
|
