URL https://opencores.org/ocsvn/fat_32_file_parser/fat_32_file_parser/trunk

Subversion Repositories fat_32_file_parser

[/] [fat_32_file_parser/] [trunk/] [top_ps2keyboard.vhd] - Blame information for rev 2

Details | Compare with Previous | View Log


----------------------------------------------------------------------------------
-- Company: 
-- Engineer: CW
-- 
-- Create Date:    21:25:31 10/06/2014 
-- Design Name: 
-- Module Name:    hw_client - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.CommonPckg.all;
use work.SdCardPckg.all;
 
library UNISIM;
use UNISIM.VComponents.all;
 
entity hw_client is
    Port ( CLK_IN               : in STD_LOGIC;
 
                          -- DEBUG Signals
           LED_OUT              : out STD_LOGIC_VECTOR (7 downto 0);
           SSEG_OUT             : out STD_LOGIC_VECTOR (7 downto 0);
           AN_OUT               : out STD_LOGIC_VECTOR (3 downto 0);
           SW_IN                        : in STD_LOGIC_VECTOR (7 downto 0);
           BUTTON_IN    : in STD_LOGIC_VECTOR (3 downto 0);
                          vgaRed                        : out STD_LOGIC_VECTOR (2 downto 0);
                          vgaGreen              : out STD_LOGIC_VECTOR (2 downto 0);
                          vgaBlue               : out STD_LOGIC_VECTOR (1 downto 0);
                          Hsync                 : out STD_LOGIC;
                          Vsync                 : out STD_LOGIC;
 
                          -- SD Signals
                          SD_PRESENT_BAR_IN     : in STD_LOGIC;
                          SD_MOSI_OUT                   : out STD_LOGIC;
                          SD_MISO_IN                    : in STD_LOGIC;
                          SD_CLK_OUT                    : out STD_LOGIC;
                          SD_CS_OUT                             : out STD_LOGIC);
end hw_client;
 
architecture Behavioral of hw_client is
 
        COMPONENT clk_mod
                 Port ( CLK_50MHz_IN    : in  STD_LOGIC;
                                  CLK_25Mhz_OUT         : out  STD_LOGIC);
        END COMPONENT;
 
        COMPONENT sseg
        PORT (
                CLK    : in STD_LOGIC;
                VAL_IN          : in STD_LOGIC_VECTOR (15 downto 0);
                SSEG_OUT        : out STD_LOGIC_VECTOR(7 downto 0);
                AN_OUT   : out STD_LOGIC_VECTOR(3 downto 0));
        END COMPONENT;
 
        COMPONENT SdCardInit
    Port ( CLK_IN                               : in  STD_LOGIC;
           RESET_IN                             : in  STD_LOGIC;
 
                          SD_PRESENT_BAR_IN     : in  STD_LOGIC;
           SD_INIT_OUT                  : out STD_LOGIC;
           SD_BLOCK_RD_OUT      : out STD_LOGIC;
           SD_BLOCK_ADDR_OUT    : out STD_LOGIC_VECTOR (31 downto 0);
           SD_DATA_IN                   : in  STD_LOGIC_VECTOR (7 downto 0);
           SD_BUSY_IN                   : in  STD_LOGIC;
           SD_BYTE_RD_OUT               : out STD_LOGIC;
           SD_BYTE_RD_ACK_IN    : in  STD_LOGIC;
           SD_ERROR_IN                  : in  STD_LOGIC_VECTOR (15 downto 0);
           SD_INIT_CMPLT_OUT    : out STD_LOGIC;
 
           FAT_BEGIN_ADDR_OUT                   : out  STD_LOGIC_VECTOR (31 downto 0);
                          SECTORS_PER_FAT_OUT                   : out  STD_LOGIC_VECTOR (31 downto 0);
           CLUSTER_BEGIN_ADDR_OUT               : out  STD_LOGIC_VECTOR (31 downto 0);
           SECTORS_PER_CLUSTER_OUT              : out  STD_LOGIC_VECTOR (7 downto 0);
           ROOT_DIR_FIRST_CLUSTER_OUT   : out  STD_LOGIC_VECTOR (31 downto 0));
        END COMPONENT;
 
        COMPONENT SdCardReadWrite
    Port ( CLK_IN : in  STD_LOGIC;
           RESET_IN : in  STD_LOGIC;
 
                          FAT_BEGIN_ADDR_IN                             : in  STD_LOGIC_VECTOR (31 downto 0);
                          SECTORS_PER_FAT_IN                            : in  STD_LOGIC_VECTOR (31 downto 0);
           CLUSTER_BEGIN_ADDR_IN                : in  STD_LOGIC_VECTOR (31 downto 0);
           SECTORS_PER_CLUSTER_IN               : in  STD_LOGIC_VECTOR (7 downto 0);
           ROOT_DIR_FIRST_CLUSTER_IN    : in  STD_LOGIC_VECTOR (31 downto 0);
 
                          SD_INIT_CMPLT_IN      : in STD_LOGIC;
 
                          SD_BLOCK_RD_OUT       : out STD_LOGIC;
           SD_BLOCK_ADDR_OUT    : out STD_LOGIC_VECTOR (31 downto 0);
           SD_DATA_IN                   : in  STD_LOGIC_VECTOR (7 downto 0);
           SD_BUSY_IN                   : in  STD_LOGIC;
           SD_BYTE_RD_OUT               : out STD_LOGIC;
           SD_BYTE_RD_ACK_IN    : in  STD_LOGIC;
 
                          GET_NEXT_DIRENT_IN                    : in STD_LOGIC;
                          NEXT_DIRENT_DONE_OUT          : out STD_LOGIC;
                          DIRENT_IS_FOLDER_OUT          : out STD_LOGIC;
                          RD_DIRENT_NAME_CHAR_IN        : in STD_LOGIC;
                          DIRENT_CHAR_OUT                               : out STD_LOGIC_VECTOR(7 downto 0);
                          END_OF_DIRENT_NAME_OUT        : out STD_LOGIC;
                          NO_MORE_DIRENTS_OUT           : out STD_LOGIC;
 
                          DEBUG_IN              : in STD_LOGIC_VECTOR(7 downto 0);
                          DEBUG_OUT     : out STD_LOGIC_VECTOR(15 downto 0);
                          DEBUG_OUT2    : out STD_LOGIC_VECTOR(7 downto 0));
        END COMPONENT;
 
        COMPONENT SdCardCtrl
    generic (
      FREQ_G          : real       := 100.0;  -- Master clock frequency (MHz).
      INIT_SPI_FREQ_G : real       := 0.4;  -- Slow SPI clock freq. during initialization (MHz).
      SPI_FREQ_G      : real       := 25.0;  -- Operational SPI freq. to the SD card (MHz).
      BLOCK_SIZE_G    : natural    := 512;  -- Number of bytes in an SD card block or sector.
      CARD_TYPE_G     : CardType_t := SD_CARD_E  -- Type of SD card connected to this controller.
      );
    port (
      -- Host-side interface signals.
      clk_i      : in  std_logic;       -- Master clock.
      reset_i    : in  std_logic                     := NO;  -- active-high, synchronous  reset.
      rd_i       : in  std_logic                     := NO;  -- active-high read block request.
      wr_i       : in  std_logic                     := NO;  -- active-high write block request.
      continue_i : in  std_logic                     := NO;  -- If true, inc address and continue R/W.
      addr_i     : in  std_logic_vector(31 downto 0) := x"00000000";  -- Block address.
      data_i     : in  std_logic_vector(7 downto 0)  := x"00";  -- Data to write to block.
      data_o     : out std_logic_vector(7 downto 0)  := x"00";  -- Data read from block.
      busy_o     : out std_logic;  -- High when controller is busy performing some operation.
      hndShk_i   : in  std_logic;  -- High when host has data to give or has taken data.
      hndShk_o   : out std_logic;  -- High when controller has taken data or has data to give.
      error_o    : out std_logic_vector(15 downto 0) := (others => NO);
      -- I/O signals to the external SD card.
      cs_bo      : out std_logic                     := HI;  -- Active-low chip-select.
      sclk_o     : out std_logic                     := LO;  -- Serial clock to SD card.
      mosi_o     : out std_logic                     := HI;  -- Serial data output to SD card.
      miso_i     : in  std_logic                     := ZERO;  -- Serial data input from SD card.
                state_debug_o   : out std_logic_vector(4 downto 0)
      );
        END COMPONENT;
 
        COMPONENT vga80x40
          PORT (
                 reset       : in  std_logic;
                 clk25MHz    : in  std_logic;
                 TEXT_A      : out std_logic_vector(11 downto 0);
                 TEXT_D      : in  std_logic_vector(7 downto 0);
                 FONT_A      : out std_logic_vector(11 downto 0);
                 FONT_D      : in  std_logic_vector(7 downto 0);
                 --
                 ocrx        : in  std_logic_vector(7 downto 0);
                 ocry        : in  std_logic_vector(7 downto 0);
                 octl        : in  std_logic_vector(7 downto 0);
                 --
                 R           : out std_logic;
                 G           : out std_logic;
                 B           : out std_logic;
                 hsync       : out std_logic;
                 vsync       : out std_logic);
        END COMPONENT;
 
        COMPONENT FONT_MEM
          PORT (
                 clka   : IN STD_LOGIC;
                 wea            : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
                 addra  : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
                 dina   : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
                 douta  : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
        END COMPONENT;
 
        COMPONENT TDP_RAM
                Generic (G_DATA_A_SIZE  :natural :=32;
                                        G_ADDR_A_SIZE   :natural :=9;
                                        G_RELATION              :natural :=3;
                                        G_INIT_FILE             :string :="");--log2(SIZE_A/SIZE_B)
                Port ( CLK_A_IN         : in  STD_LOGIC;
                                 WE_A_IN        : in  STD_LOGIC;
                                 ADDR_A_IN      : in  STD_LOGIC_VECTOR (G_ADDR_A_SIZE-1 downto 0);
                                 DATA_A_IN      : in  STD_LOGIC_VECTOR (G_DATA_A_SIZE-1 downto 0);
                                 DATA_A_OUT     : out STD_LOGIC_VECTOR (G_DATA_A_SIZE-1 downto 0);
                                 CLK_B_IN       : in  STD_LOGIC;
                                 WE_B_IN        : in  STD_LOGIC;
                                 ADDR_B_IN      : in  STD_LOGIC_VECTOR (G_ADDR_A_SIZE+G_RELATION-1 downto 0);
                                 DATA_B_IN      : in  STD_LOGIC_VECTOR (G_DATA_A_SIZE/(2**G_RELATION)-1 downto 0);
                                 DATA_B_OUT : out STD_LOGIC_VECTOR (G_DATA_A_SIZE/(2**G_RELATION)-1 downto 0));
        END COMPONENT;
 
subtype slv is std_logic_vector;
 
signal clk_25MHz : std_logic;
 
-------------------------- DEBUG ------------------------------------
 
signal sseg_data                                                                                : std_logic_vector(15 downto 0) := (others => '0');
signal leds, switches                                                           : std_logic_vector(7 downto 0) := (others => '0');
signal debug_in, debug_out2                                             : std_logic_vector(7 downto 0) := (others => '0');
signal debug_out                                                                                : std_logic_vector(15 downto 0) := (others => '0');
signal buttons, buttons_prev, buttons_edge      : std_logic_vector(3 downto 0) := (others => '0');
signal debounce_count                                                           : unsigned(15 downto 0) := (others => '0');
signal repeat_count                                                                     : unsigned(21 downto 0) := (others => '0');
signal debug_we                                                                                 : std_logic := '0';
signal debug_wr_data                                                            : std_logic_vector(7 downto 0) := (others => '0');
signal r, g, b                                                                          : std_logic := '0';
signal font_addr, debug_addr                                            : std_logic_vector(11 downto 0);
signal font_data, debug_data                                            : std_logic_vector(7 downto 0);
signal debug_wr_addr    : unsigned(11 downto 0) := (others => '0');
 
------------------------ SD CARD SIGNALS -------------------------------
 
signal sd_mosi, sd_miso, sd_cs, sd_clk, sd_init_cmplt : std_logic;
signal sd_busy, sd_present, sd_init, sd_rd_block, sd_rd_block_init_proc : std_logic := '0';
signal sd_rd_block_rd_proc, rd_byte, rd_byte_init_proc, rd_byte_rd_proc, rd_byte_ack : std_logic := '0';
signal sd_init_attempts_counter                         : unsigned(3 downto 0) := X"0";
signal sd_error                                                                 : std_logic_vector(15 downto 0) := (others => '0');
signal sd_data, block_rd_data                           : std_logic_vector(7 downto 0) := (others => '0');
signal sd_block_addr, sd_block_addr_init_proc, sd_block_addr_rd_proc    : std_logic_vector(31 downto 0) := (others => '0');
 
signal sectors_per_cluster                                              : std_logic_vector(7 downto 0);
signal fat_begin_lba, cluster_begin_lba         : std_logic_vector(31 downto 0);
signal sectors_per_fat, root_dir_cluster                : std_logic_vector(31 downto 0);
signal read_dirent_name, dirent_found, rd_dirent_char, end_of_dirent_name : std_logic := '0';
signal dirent_is_folder, no_more_dirents : std_logic := '0';
 
begin
 
        clk_mod_Inst : clk_mod
        PORT MAP (      CLK_50MHz_IN    => CLK_IN,
                                        CLK_25Mhz_OUT => clk_25MHz);
 
----------------------- DEBUG I/O ----------------------------------
 
        LED_OUT <= leds;
        switches <= SW_IN;
 
        sseg_inst : sseg
        PORT MAP (
                CLK     => clk_25MHz,
                VAL_IN  => sseg_data,
                SSEG_OUT        => SSEG_OUT,
                AN_OUT   => AN_OUT);
 
        process(clk_25MHz)
        begin
                if rising_edge(clk_25MHz) then
                        leds(7 downto 0) <= debug_out2(7 downto 0);
                        --leds(6) <= sd_init_cmplt;
                        --leds(7) <= not(SD_PRESENT_BAR_IN);
                end if;
        end process;
 
        debug_in <= "0000000"&buttons(1);
        sseg_data <= debug_out;
        --sseg_data <= sd_error;
 
        process(clk_25MHz)
        begin
                if rising_edge(clk_25MHz) then
                        repeat_count <= repeat_count + 1;
                        debounce_count <= debounce_count + 1;
                        buttons_prev <= buttons;
                        if debounce_count = X"0000" then
                                buttons <= BUTTON_IN;
                        end if;
                        if buttons_prev(0) = '0' and buttons(0) = '1' then
                                buttons_edge(0) <= '1';
                        elsif repeat_count = X"00000"&"00" and buttons(0) = '1' then
                                buttons_edge(0) <= '1';
                        else
                                buttons_edge(0) <= '0';
                        end if;
                        if buttons_prev(1) = '0' and buttons(1) = '1' then
                                buttons_edge(1) <= '1';
                        else
                                buttons_edge(1) <= '0';
                        end if;
                        if buttons_prev(3) = '0' and buttons(3) = '1' then
                                buttons_edge(3) <= '1';
                        else
                                buttons_edge(3) <= '0';
                        end if;
                end if;
        end process;
 
        vgaRed <= r&r&r;
        vgaGreen <= g&g&g;
        vgaBlue <= b&b;
 
        vga80x40_inst : vga80x40
        PORT MAP (
                 reset       =>  '0',
                 clk25MHz    => clk_25MHz,
                 TEXT_A      => debug_addr,
                 TEXT_D      => debug_data,
                 FONT_A      => font_addr,
                 FONT_D      => font_data,
 
                 ocrx        => X"00",
                 ocry        => X"00",
                 octl        => "11100111",
 
                 R           => r,
                 G           => g,
                 B           => b,
                 hsync       => Hsync,
                 vsync       => Vsync);
 
        Font_Mem_inst : FONT_MEM
          PORT MAP (
                 clka   => clk_25MHz,
                 wea            => "0",
                 addra  => font_addr,
                 dina   => (others => '0'),
                 douta  => font_data);
 
        rd_dirent_char <= read_dirent_name;
 
        process(clk_25MHz)
        begin
                if rising_edge(clk_25MHz) then
--                      if dirent_found = '1' then
--                              leds(6) <= dirent_is_folder;
--                      end if;
                        if dirent_found = '1' then
                                read_dirent_name <= '1';
                        elsif end_of_dirent_name = '1' then
                                read_dirent_name <= '0';
                        end if;
                        if read_dirent_name = '1' then
                                debug_we <= '1';
                        elsif end_of_dirent_name = '1' then
                                debug_we <= '0';
                        end if;
                        if read_dirent_name = '1' then
                                if debug_wr_addr = X"C80" then
                                        debug_wr_addr <= (others => '0');
                                else
                                        debug_wr_addr <= debug_wr_addr + 1;
                                end if;
                        end if;
                end if;
        end process;
 
        debug_buf : TDP_RAM
        Generic Map ( G_DATA_A_SIZE     => debug_data'length,
                                          G_ADDR_A_SIZE => debug_addr'length,
                                          G_RELATION            => 0, --log2(SIZE_A/SIZE_B)
                                          G_INIT_FILE           => "./coe_dir/ascii_space.coe")
   Port Map ( CLK_A_IN          => clk_25MHz,
                                  WE_A_IN               => '0',
                                  ADDR_A_IN     => debug_addr,
                                  DATA_A_IN             => X"00",
                                  DATA_A_OUT    => debug_data,
                                  CLK_B_IN              => clk_25MHz,
                                  WE_B_IN               => debug_we,
                                  ADDR_B_IN     => slv(debug_wr_addr),
                                  DATA_B_IN     => debug_wr_data,
                                  DATA_B_OUT    => open);
 
---------------------------------------------------------
 
        SD_CS_OUT <= sd_cs;
        SD_CLK_OUT <= sd_clk;
        SD_MOSI_OUT <= sd_mosi;
        sd_miso <= SD_MISO_IN;
 
  SdCardCtrl_Inst : SdCardCtrl
    generic map (
      FREQ_G          => 25.0,          -- Master clock frequency (MHz).
      INIT_SPI_FREQ_G => 0.4,           -- Slow SPI clock freq. during initialization (MHz).
      SPI_FREQ_G      => 5.0,           -- Operational SPI freq. to the SD card (MHz).
      BLOCK_SIZE_G    => 512,           -- Number of bytes in an SD card block or sector.
      CARD_TYPE_G     => SD_CARD_E  -- Type of SD card connected to this controller.
      )
    port map (
      -- Host-side interface signals.
      clk_i      => clk_25MHz,
      reset_i    => sd_init,
      rd_i       => sd_rd_block,
      wr_i       => '0',
      continue_i => '0',
      addr_i     => sd_block_addr,
      data_i     => X"00",
      data_o     => sd_data,
      busy_o     => sd_busy,
      hndShk_i   => rd_byte,
      hndShk_o   => rd_byte_ack,
      error_o    => sd_error,
      -- I/O signals to the external SD card.
      cs_bo               => sd_cs,
      sclk_o     => sd_clk,
      mosi_o     => sd_mosi,
      miso_i     => sd_miso,
                state_debug_o   => open); --leds(4 downto 0));
 
        with sd_init_cmplt select
                rd_byte <= rd_byte_init_proc    when '0',
                                          rd_byte_rd_proc               when others;
 
        with sd_init_cmplt select
                sd_rd_block <= sd_rd_block_init_proc    when '0',
                                                        sd_rd_block_rd_proc             when others;
 
        with sd_init_cmplt select
                sd_block_addr <= sd_block_addr_init_proc        when '0',
                                                          sd_block_addr_rd_proc         when others;
 
        SdCardInit_Inst : SdCardInit
    Port Map(   CLK_IN                          => clk_25MHz,
                                        RESET_IN                        => buttons_edge(3),
 
                                        SD_PRESENT_BAR_IN => SD_PRESENT_BAR_IN,
                                        SD_INIT_OUT             => sd_init,
                                        SD_BLOCK_RD_OUT         => sd_rd_block_init_proc,
                                        SD_BLOCK_ADDR_OUT => sd_block_addr_init_proc,
                                        SD_DATA_IN                      => sd_data,
                                        SD_BUSY_IN                      => sd_busy,
                                        SD_BYTE_RD_OUT  => rd_byte_init_proc,
                                        SD_BYTE_RD_ACK_IN => rd_byte_ack,
                                        SD_ERROR_IN             => sd_error,
                                        SD_INIT_CMPLT_OUT => sd_init_cmplt,
 
                                        FAT_BEGIN_ADDR_OUT                      => fat_begin_lba,
                                        SECTORS_PER_FAT_OUT                     => sectors_per_fat,
                                        CLUSTER_BEGIN_ADDR_OUT          => cluster_begin_lba,
                                        SECTORS_PER_CLUSTER_OUT         => sectors_per_cluster,
                                        ROOT_DIR_FIRST_CLUSTER_OUT => root_dir_cluster);
 
        SdCardReadWrite_Inst : SdCardReadWrite
    Port Map(   CLK_IN  => clk_25MHz,
                                        RESET_IN => buttons_edge(3),
 
                                        FAT_BEGIN_ADDR_IN                       => fat_begin_lba,
                                        SECTORS_PER_FAT_IN                      => sectors_per_fat,
                                        CLUSTER_BEGIN_ADDR_IN           => cluster_begin_lba,
                                        SECTORS_PER_CLUSTER_IN          => sectors_per_cluster,
                                        ROOT_DIR_FIRST_CLUSTER_IN       => root_dir_cluster,
 
                                        SD_INIT_CMPLT_IN => sd_init_cmplt,
 
                                        SD_BLOCK_RD_OUT         => sd_rd_block_rd_proc,
                                        SD_BLOCK_ADDR_OUT => sd_block_addr_rd_proc,
                                        SD_DATA_IN                      => sd_data,
                                        SD_BUSY_IN                      => sd_busy,
                                        SD_BYTE_RD_OUT  => rd_byte_rd_proc,
                                        SD_BYTE_RD_ACK_IN => rd_byte_ack,
 
                                        GET_NEXT_DIRENT_IN              => buttons_edge(0),
                                        NEXT_DIRENT_DONE_OUT            => dirent_found,
                                        DIRENT_IS_FOLDER_OUT            => dirent_is_folder,
                                        RD_DIRENT_NAME_CHAR_IN  => rd_dirent_char,
                                        DIRENT_CHAR_OUT                 => debug_wr_data,
                                        END_OF_DIRENT_NAME_OUT  => end_of_dirent_name,
                                        NO_MORE_DIRENTS_OUT             => no_more_dirents,
 
                                        DEBUG_IN        => debug_in,
                                        DEBUG_OUT       => debug_out,
                                        DEBUG_OUT2      => debug_out2);
 
end Behavioral;
 

Browse

Tools

Subversion Repositories fat_32_file_parser

[/] [fat_32_file_parser/] [trunk/] [top_ps2keyboard.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	craighaywo	`----------------------------------------------------------------------------------`
2			`-- Company:`
3			`-- Engineer: CW`
4			`--`
5			`-- Create Date: 21:25:31 10/06/2014`
6			`-- Design Name:`
7			`-- Module Name: hw_client - Behavioral`
8			`-- Project Name:`
9			`-- Target Devices:`
10			`-- Tool versions:`
11			`-- Description:`
12			`--`
13			`-- Dependencies:`
14			`--`
15			`-- Revision:`
16			`-- Revision 0.01 - File Created`
17			`-- Additional Comments:`
18			`--`
19			`----------------------------------------------------------------------------------`
20
21			`library IEEE;`
22			`use IEEE.STD_LOGIC_1164.ALL;`
23			`use IEEE.NUMERIC_STD.ALL;`
24			`use work.CommonPckg.all;`
25			`use work.SdCardPckg.all;`
26
27			`library UNISIM;`
28			`use UNISIM.VComponents.all;`
29
30			`entity hw_client is`
31			`Port ( CLK_IN : in STD_LOGIC;`
32
33			`-- DEBUG Signals`
34			`LED_OUT : out STD_LOGIC_VECTOR (7 downto 0);`
35			`SSEG_OUT : out STD_LOGIC_VECTOR (7 downto 0);`
36			`AN_OUT : out STD_LOGIC_VECTOR (3 downto 0);`
37			`SW_IN : in STD_LOGIC_VECTOR (7 downto 0);`
38			`BUTTON_IN : in STD_LOGIC_VECTOR (3 downto 0);`
39			`vgaRed : out STD_LOGIC_VECTOR (2 downto 0);`
40			`vgaGreen : out STD_LOGIC_VECTOR (2 downto 0);`
41			`vgaBlue : out STD_LOGIC_VECTOR (1 downto 0);`
42			`Hsync : out STD_LOGIC;`
43			`Vsync : out STD_LOGIC;`
44
45			`-- SD Signals`
46			`SD_PRESENT_BAR_IN : in STD_LOGIC;`
47			`SD_MOSI_OUT : out STD_LOGIC;`
48			`SD_MISO_IN : in STD_LOGIC;`
49			`SD_CLK_OUT : out STD_LOGIC;`
50			`SD_CS_OUT : out STD_LOGIC);`
51			`end hw_client;`
52
53			`architecture Behavioral of hw_client is`
54
55			`COMPONENT clk_mod`
56			`Port ( CLK_50MHz_IN : in STD_LOGIC;`
57			`CLK_25Mhz_OUT : out STD_LOGIC);`
58			`END COMPONENT;`
59
60			`COMPONENT sseg`
61			`PORT (`
62			`CLK : in STD_LOGIC;`
63			`VAL_IN : in STD_LOGIC_VECTOR (15 downto 0);`
64			`SSEG_OUT : out STD_LOGIC_VECTOR(7 downto 0);`
65			`AN_OUT : out STD_LOGIC_VECTOR(3 downto 0));`
66			`END COMPONENT;`
67
68			`COMPONENT SdCardInit`
69			`Port ( CLK_IN : in STD_LOGIC;`
70			`RESET_IN : in STD_LOGIC;`
71
72			`SD_PRESENT_BAR_IN : in STD_LOGIC;`
73			`SD_INIT_OUT : out STD_LOGIC;`
74			`SD_BLOCK_RD_OUT : out STD_LOGIC;`
75			`SD_BLOCK_ADDR_OUT : out STD_LOGIC_VECTOR (31 downto 0);`
76			`SD_DATA_IN : in STD_LOGIC_VECTOR (7 downto 0);`
77			`SD_BUSY_IN : in STD_LOGIC;`
78			`SD_BYTE_RD_OUT : out STD_LOGIC;`
79			`SD_BYTE_RD_ACK_IN : in STD_LOGIC;`
80			`SD_ERROR_IN : in STD_LOGIC_VECTOR (15 downto 0);`
81			`SD_INIT_CMPLT_OUT : out STD_LOGIC;`
82
83			`FAT_BEGIN_ADDR_OUT : out STD_LOGIC_VECTOR (31 downto 0);`
84			`SECTORS_PER_FAT_OUT : out STD_LOGIC_VECTOR (31 downto 0);`
85			`CLUSTER_BEGIN_ADDR_OUT : out STD_LOGIC_VECTOR (31 downto 0);`
86			`SECTORS_PER_CLUSTER_OUT : out STD_LOGIC_VECTOR (7 downto 0);`
87			`ROOT_DIR_FIRST_CLUSTER_OUT : out STD_LOGIC_VECTOR (31 downto 0));`
88			`END COMPONENT;`
89
90			`COMPONENT SdCardReadWrite`
91			`Port ( CLK_IN : in STD_LOGIC;`
92			`RESET_IN : in STD_LOGIC;`
93
94			`FAT_BEGIN_ADDR_IN : in STD_LOGIC_VECTOR (31 downto 0);`
95			`SECTORS_PER_FAT_IN : in STD_LOGIC_VECTOR (31 downto 0);`
96			`CLUSTER_BEGIN_ADDR_IN : in STD_LOGIC_VECTOR (31 downto 0);`
97			`SECTORS_PER_CLUSTER_IN : in STD_LOGIC_VECTOR (7 downto 0);`
98			`ROOT_DIR_FIRST_CLUSTER_IN : in STD_LOGIC_VECTOR (31 downto 0);`
99
100			`SD_INIT_CMPLT_IN : in STD_LOGIC;`
101
102			`SD_BLOCK_RD_OUT : out STD_LOGIC;`
103			`SD_BLOCK_ADDR_OUT : out STD_LOGIC_VECTOR (31 downto 0);`
104			`SD_DATA_IN : in STD_LOGIC_VECTOR (7 downto 0);`
105			`SD_BUSY_IN : in STD_LOGIC;`
106			`SD_BYTE_RD_OUT : out STD_LOGIC;`
107			`SD_BYTE_RD_ACK_IN : in STD_LOGIC;`
108
109			`GET_NEXT_DIRENT_IN : in STD_LOGIC;`
110			`NEXT_DIRENT_DONE_OUT : out STD_LOGIC;`
111			`DIRENT_IS_FOLDER_OUT : out STD_LOGIC;`
112			`RD_DIRENT_NAME_CHAR_IN : in STD_LOGIC;`
113			`DIRENT_CHAR_OUT : out STD_LOGIC_VECTOR(7 downto 0);`
114			`END_OF_DIRENT_NAME_OUT : out STD_LOGIC;`
115			`NO_MORE_DIRENTS_OUT : out STD_LOGIC;`
116
117			`DEBUG_IN : in STD_LOGIC_VECTOR(7 downto 0);`
118			`DEBUG_OUT : out STD_LOGIC_VECTOR(15 downto 0);`
119			`DEBUG_OUT2 : out STD_LOGIC_VECTOR(7 downto 0));`
120			`END COMPONENT;`
121
122			`COMPONENT SdCardCtrl`
123			`generic (`
124			`FREQ_G : real := 100.0; -- Master clock frequency (MHz).`
125			`INIT_SPI_FREQ_G : real := 0.4; -- Slow SPI clock freq. during initialization (MHz).`
126			`SPI_FREQ_G : real := 25.0; -- Operational SPI freq. to the SD card (MHz).`
127			`BLOCK_SIZE_G : natural := 512; -- Number of bytes in an SD card block or sector.`
128			`CARD_TYPE_G : CardType_t := SD_CARD_E -- Type of SD card connected to this controller.`
129			`);`
130			`port (`
131			`-- Host-side interface signals.`
132			`clk_i : in std_logic; -- Master clock.`
133			`reset_i : in std_logic := NO; -- active-high, synchronous reset.`
134			`rd_i : in std_logic := NO; -- active-high read block request.`
135			`wr_i : in std_logic := NO; -- active-high write block request.`
136			`continue_i : in std_logic := NO; -- If true, inc address and continue R/W.`
137			`addr_i : in std_logic_vector(31 downto 0) := x"00000000"; -- Block address.`
138			`data_i : in std_logic_vector(7 downto 0) := x"00"; -- Data to write to block.`
139			`data_o : out std_logic_vector(7 downto 0) := x"00"; -- Data read from block.`
140			`busy_o : out std_logic; -- High when controller is busy performing some operation.`
141			`hndShk_i : in std_logic; -- High when host has data to give or has taken data.`
142			`hndShk_o : out std_logic; -- High when controller has taken data or has data to give.`
143			`error_o : out std_logic_vector(15 downto 0) := (others => NO);`
144			`-- I/O signals to the external SD card.`
145			`cs_bo : out std_logic := HI; -- Active-low chip-select.`
146			`sclk_o : out std_logic := LO; -- Serial clock to SD card.`
147			`mosi_o : out std_logic := HI; -- Serial data output to SD card.`
148			`miso_i : in std_logic := ZERO; -- Serial data input from SD card.`
149			`state_debug_o : out std_logic_vector(4 downto 0)`
150			`);`
151			`END COMPONENT;`
152
153			`COMPONENT vga80x40`
154			`PORT (`
155			`reset : in std_logic;`
156			`clk25MHz : in std_logic;`
157			`TEXT_A : out std_logic_vector(11 downto 0);`
158			`TEXT_D : in std_logic_vector(7 downto 0);`
159			`FONT_A : out std_logic_vector(11 downto 0);`
160			`FONT_D : in std_logic_vector(7 downto 0);`
161			`--`
162			`ocrx : in std_logic_vector(7 downto 0);`
163			`ocry : in std_logic_vector(7 downto 0);`
164			`octl : in std_logic_vector(7 downto 0);`
165			`--`
166			`R : out std_logic;`
167			`G : out std_logic;`
168			`B : out std_logic;`
169			`hsync : out std_logic;`
170			`vsync : out std_logic);`
171			`END COMPONENT;`
172
173			`COMPONENT FONT_MEM`
174			`PORT (`
175			`clka : IN STD_LOGIC;`
176			`wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);`
177			`addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);`
178			`dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
179			`douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));`
180			`END COMPONENT;`
181
182			`COMPONENT TDP_RAM`
183			`Generic (G_DATA_A_SIZE :natural :=32;`
184			`G_ADDR_A_SIZE :natural :=9;`
185			`G_RELATION :natural :=3;`
186			`G_INIT_FILE :string :="");--log2(SIZE_A/SIZE_B)`
187			`Port ( CLK_A_IN : in STD_LOGIC;`
188			`WE_A_IN : in STD_LOGIC;`
189			`ADDR_A_IN : in STD_LOGIC_VECTOR (G_ADDR_A_SIZE-1 downto 0);`
190			`DATA_A_IN : in STD_LOGIC_VECTOR (G_DATA_A_SIZE-1 downto 0);`
191			`DATA_A_OUT : out STD_LOGIC_VECTOR (G_DATA_A_SIZE-1 downto 0);`
192			`CLK_B_IN : in STD_LOGIC;`
193			`WE_B_IN : in STD_LOGIC;`
194			`ADDR_B_IN : in STD_LOGIC_VECTOR (G_ADDR_A_SIZE+G_RELATION-1 downto 0);`
195			`DATA_B_IN : in STD_LOGIC_VECTOR (G_DATA_A_SIZE/(2**G_RELATION)-1 downto 0);`
196			`DATA_B_OUT : out STD_LOGIC_VECTOR (G_DATA_A_SIZE/(2**G_RELATION)-1 downto 0));`
197			`END COMPONENT;`
198
199			`subtype slv is std_logic_vector;`
200
201			`signal clk_25MHz : std_logic;`
202
203			`-------------------------- DEBUG ------------------------------------`
204
205			`signal sseg_data : std_logic_vector(15 downto 0) := (others => '0');`
206			`signal leds, switches : std_logic_vector(7 downto 0) := (others => '0');`
207			`signal debug_in, debug_out2 : std_logic_vector(7 downto 0) := (others => '0');`
208			`signal debug_out : std_logic_vector(15 downto 0) := (others => '0');`
209			`signal buttons, buttons_prev, buttons_edge : std_logic_vector(3 downto 0) := (others => '0');`
210			`signal debounce_count : unsigned(15 downto 0) := (others => '0');`
211			`signal repeat_count : unsigned(21 downto 0) := (others => '0');`
212			`signal debug_we : std_logic := '0';`
213			`signal debug_wr_data : std_logic_vector(7 downto 0) := (others => '0');`
214			`signal r, g, b : std_logic := '0';`
215			`signal font_addr, debug_addr : std_logic_vector(11 downto 0);`
216			`signal font_data, debug_data : std_logic_vector(7 downto 0);`
217			`signal debug_wr_addr : unsigned(11 downto 0) := (others => '0');`
218
219			`------------------------ SD CARD SIGNALS -------------------------------`
220
221			`signal sd_mosi, sd_miso, sd_cs, sd_clk, sd_init_cmplt : std_logic;`
222			`signal sd_busy, sd_present, sd_init, sd_rd_block, sd_rd_block_init_proc : std_logic := '0';`
223			`signal sd_rd_block_rd_proc, rd_byte, rd_byte_init_proc, rd_byte_rd_proc, rd_byte_ack : std_logic := '0';`
224			`signal sd_init_attempts_counter : unsigned(3 downto 0) := X"0";`
225			`signal sd_error : std_logic_vector(15 downto 0) := (others => '0');`
226			`signal sd_data, block_rd_data : std_logic_vector(7 downto 0) := (others => '0');`
227			`signal sd_block_addr, sd_block_addr_init_proc, sd_block_addr_rd_proc : std_logic_vector(31 downto 0) := (others => '0');`
228
229			`signal sectors_per_cluster : std_logic_vector(7 downto 0);`
230			`signal fat_begin_lba, cluster_begin_lba : std_logic_vector(31 downto 0);`
231			`signal sectors_per_fat, root_dir_cluster : std_logic_vector(31 downto 0);`
232			`signal read_dirent_name, dirent_found, rd_dirent_char, end_of_dirent_name : std_logic := '0';`
233			`signal dirent_is_folder, no_more_dirents : std_logic := '0';`
234
235			`begin`
236
237			`clk_mod_Inst : clk_mod`
238			`PORT MAP ( CLK_50MHz_IN => CLK_IN,`
239			`CLK_25Mhz_OUT => clk_25MHz);`
240
241			`----------------------- DEBUG I/O ----------------------------------`
242
243			`LED_OUT <= leds;`
244			`switches <= SW_IN;`
245
246			`sseg_inst : sseg`
247			`PORT MAP (`
248			`CLK => clk_25MHz,`
249			`VAL_IN => sseg_data,`
250			`SSEG_OUT => SSEG_OUT,`
251			`AN_OUT => AN_OUT);`
252
253			`process(clk_25MHz)`
254			`begin`
255			`if rising_edge(clk_25MHz) then`
256			`leds(7 downto 0) <= debug_out2(7 downto 0);`
257			`--leds(6) <= sd_init_cmplt;`
258			`--leds(7) <= not(SD_PRESENT_BAR_IN);`
259			`end if;`
260			`end process;`
261
262			`debug_in <= "0000000"&buttons(1);`
263			`sseg_data <= debug_out;`
264			`--sseg_data <= sd_error;`
265
266			`process(clk_25MHz)`
267			`begin`
268			`if rising_edge(clk_25MHz) then`
269			`repeat_count <= repeat_count + 1;`
270			`debounce_count <= debounce_count + 1;`
271			`buttons_prev <= buttons;`
272			`if debounce_count = X"0000" then`
273			`buttons <= BUTTON_IN;`
274			`end if;`
275			`if buttons_prev(0) = '0' and buttons(0) = '1' then`
276			`buttons_edge(0) <= '1';`
277			`elsif repeat_count = X"00000"&"00" and buttons(0) = '1' then`
278			`buttons_edge(0) <= '1';`
279			`else`
280			`buttons_edge(0) <= '0';`
281			`end if;`
282			`if buttons_prev(1) = '0' and buttons(1) = '1' then`
283			`buttons_edge(1) <= '1';`
284			`else`
285			`buttons_edge(1) <= '0';`
286			`end if;`
287			`if buttons_prev(3) = '0' and buttons(3) = '1' then`
288			`buttons_edge(3) <= '1';`
289			`else`
290			`buttons_edge(3) <= '0';`
291			`end if;`
292			`end if;`
293			`end process;`
294
295			`vgaRed <= r&r&r;`
296			`vgaGreen <= g&g&g;`
297			`vgaBlue <= b&b;`
298
299			`vga80x40_inst : vga80x40`
300			`PORT MAP (`
301			`reset => '0',`
302			`clk25MHz => clk_25MHz,`
303			`TEXT_A => debug_addr,`
304			`TEXT_D => debug_data,`
305			`FONT_A => font_addr,`
306			`FONT_D => font_data,`
307
308			`ocrx => X"00",`
309			`ocry => X"00",`
310			`octl => "11100111",`
311
312			`R => r,`
313			`G => g,`
314			`B => b,`
315			`hsync => Hsync,`
316			`vsync => Vsync);`
317
318			`Font_Mem_inst : FONT_MEM`
319			`PORT MAP (`
320			`clka => clk_25MHz,`
321			`wea => "0",`
322			`addra => font_addr,`
323			`dina => (others => '0'),`
324			`douta => font_data);`
325
326			`rd_dirent_char <= read_dirent_name;`
327
328			`process(clk_25MHz)`
329			`begin`
330			`if rising_edge(clk_25MHz) then`
331			`-- if dirent_found = '1' then`
332			`-- leds(6) <= dirent_is_folder;`
333			`-- end if;`
334			`if dirent_found = '1' then`
335			`read_dirent_name <= '1';`
336			`elsif end_of_dirent_name = '1' then`
337			`read_dirent_name <= '0';`
338			`end if;`
339			`if read_dirent_name = '1' then`
340			`debug_we <= '1';`
341			`elsif end_of_dirent_name = '1' then`
342			`debug_we <= '0';`
343			`end if;`
344			`if read_dirent_name = '1' then`
345			`if debug_wr_addr = X"C80" then`
346			`debug_wr_addr <= (others => '0');`
347			`else`
348			`debug_wr_addr <= debug_wr_addr + 1;`
349			`end if;`
350			`end if;`
351			`end if;`
352			`end process;`
353
354			`debug_buf : TDP_RAM`
355			`Generic Map ( G_DATA_A_SIZE => debug_data'length,`
356			`G_ADDR_A_SIZE => debug_addr'length,`
357			`G_RELATION => 0, --log2(SIZE_A/SIZE_B)`
358			`G_INIT_FILE => "./coe_dir/ascii_space.coe")`
359			`Port Map ( CLK_A_IN => clk_25MHz,`
360			`WE_A_IN => '0',`
361			`ADDR_A_IN => debug_addr,`
362			`DATA_A_IN => X"00",`
363			`DATA_A_OUT => debug_data,`
364			`CLK_B_IN => clk_25MHz,`
365			`WE_B_IN => debug_we,`
366			`ADDR_B_IN => slv(debug_wr_addr),`
367			`DATA_B_IN => debug_wr_data,`
368			`DATA_B_OUT => open);`
369
370			`---------------------------------------------------------`
371
372			`SD_CS_OUT <= sd_cs;`
373			`SD_CLK_OUT <= sd_clk;`
374			`SD_MOSI_OUT <= sd_mosi;`
375			`sd_miso <= SD_MISO_IN;`
376
377			`SdCardCtrl_Inst : SdCardCtrl`
378			`generic map (`
379			`FREQ_G => 25.0, -- Master clock frequency (MHz).`
380			`INIT_SPI_FREQ_G => 0.4, -- Slow SPI clock freq. during initialization (MHz).`
381			`SPI_FREQ_G => 5.0, -- Operational SPI freq. to the SD card (MHz).`
382			`BLOCK_SIZE_G => 512, -- Number of bytes in an SD card block or sector.`
383			`CARD_TYPE_G => SD_CARD_E -- Type of SD card connected to this controller.`
384			`)`
385			`port map (`
386			`-- Host-side interface signals.`
387			`clk_i => clk_25MHz,`
388			`reset_i => sd_init,`
389			`rd_i => sd_rd_block,`
390			`wr_i => '0',`
391			`continue_i => '0',`
392			`addr_i => sd_block_addr,`
393			`data_i => X"00",`
394			`data_o => sd_data,`
395			`busy_o => sd_busy,`
396			`hndShk_i => rd_byte,`
397			`hndShk_o => rd_byte_ack,`
398			`error_o => sd_error,`
399			`-- I/O signals to the external SD card.`
400			`cs_bo => sd_cs,`
401			`sclk_o => sd_clk,`
402			`mosi_o => sd_mosi,`
403			`miso_i => sd_miso,`
404			`state_debug_o => open); --leds(4 downto 0));`
405
406			`with sd_init_cmplt select`
407			`rd_byte <= rd_byte_init_proc when '0',`
408			`rd_byte_rd_proc when others;`
409
410			`with sd_init_cmplt select`
411			`sd_rd_block <= sd_rd_block_init_proc when '0',`
412			`sd_rd_block_rd_proc when others;`
413
414			`with sd_init_cmplt select`
415			`sd_block_addr <= sd_block_addr_init_proc when '0',`
416			`sd_block_addr_rd_proc when others;`
417
418			`SdCardInit_Inst : SdCardInit`
419			`Port Map( CLK_IN => clk_25MHz,`
420			`RESET_IN => buttons_edge(3),`
421
422			`SD_PRESENT_BAR_IN => SD_PRESENT_BAR_IN,`
423			`SD_INIT_OUT => sd_init,`
424			`SD_BLOCK_RD_OUT => sd_rd_block_init_proc,`
425			`SD_BLOCK_ADDR_OUT => sd_block_addr_init_proc,`
426			`SD_DATA_IN => sd_data,`
427			`SD_BUSY_IN => sd_busy,`
428			`SD_BYTE_RD_OUT => rd_byte_init_proc,`
429			`SD_BYTE_RD_ACK_IN => rd_byte_ack,`
430			`SD_ERROR_IN => sd_error,`
431			`SD_INIT_CMPLT_OUT => sd_init_cmplt,`
432
433			`FAT_BEGIN_ADDR_OUT => fat_begin_lba,`
434			`SECTORS_PER_FAT_OUT => sectors_per_fat,`
435			`CLUSTER_BEGIN_ADDR_OUT => cluster_begin_lba,`
436			`SECTORS_PER_CLUSTER_OUT => sectors_per_cluster,`
437			`ROOT_DIR_FIRST_CLUSTER_OUT => root_dir_cluster);`
438
439			`SdCardReadWrite_Inst : SdCardReadWrite`
440			`Port Map( CLK_IN => clk_25MHz,`
441			`RESET_IN => buttons_edge(3),`
442
443			`FAT_BEGIN_ADDR_IN => fat_begin_lba,`
444			`SECTORS_PER_FAT_IN => sectors_per_fat,`
445			`CLUSTER_BEGIN_ADDR_IN => cluster_begin_lba,`
446			`SECTORS_PER_CLUSTER_IN => sectors_per_cluster,`
447			`ROOT_DIR_FIRST_CLUSTER_IN => root_dir_cluster,`
448
449			`SD_INIT_CMPLT_IN => sd_init_cmplt,`
450
451			`SD_BLOCK_RD_OUT => sd_rd_block_rd_proc,`
452			`SD_BLOCK_ADDR_OUT => sd_block_addr_rd_proc,`
453			`SD_DATA_IN => sd_data,`
454			`SD_BUSY_IN => sd_busy,`
455			`SD_BYTE_RD_OUT => rd_byte_rd_proc,`
456			`SD_BYTE_RD_ACK_IN => rd_byte_ack,`
457
458			`GET_NEXT_DIRENT_IN => buttons_edge(0),`
459			`NEXT_DIRENT_DONE_OUT => dirent_found,`
460			`DIRENT_IS_FOLDER_OUT => dirent_is_folder,`
461			`RD_DIRENT_NAME_CHAR_IN => rd_dirent_char,`
462			`DIRENT_CHAR_OUT => debug_wr_data,`
463			`END_OF_DIRENT_NAME_OUT => end_of_dirent_name,`
464			`NO_MORE_DIRENTS_OUT => no_more_dirents,`
465
466			`DEBUG_IN => debug_in,`
467			`DEBUG_OUT => debug_out,`
468			`DEBUG_OUT2 => debug_out2);`
469
470			`end Behavioral;`
471