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Subversion Repositories fat_32_file_parser

[/] [fat_32_file_parser/] [trunk/] [user_input_handler.vhd] - Blame information for rev 2

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----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:39:01 10/19/2014 
-- Design Name: 
-- Module Name:    user_input_handler - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity user_input_handler is
    Port ( CLK_IN                       : in  STD_LOGIC;
           RX_IN                                : in  STD_LOGIC;
           TX_OUT                       : out  STD_LOGIC;
           TEXT_ADDR_IN         : in  STD_LOGIC_VECTOR (11 downto 0);
           TEXT_DATA_OUT        : out STD_LOGIC_VECTOR (7 downto 0);
           FONT_ADDR_IN         : in  STD_LOGIC_VECTOR (11 downto 0);
           FONT_DATA_OUT        : out STD_LOGIC_VECTOR (7 downto 0);
           CURSORPOS_X_OUT : out STD_LOGIC_VECTOR (7 downto 0);
           CURSORPOS_Y_OUT : out STD_LOGIC_VECTOR (7 downto 0);
                          DEBUG_OUT                     : out STD_LOGIC_VECTOR(7 downto 0);
                          DEBUG_OUT2            : out STD_LOGIC_VECTOR(7 downto 0));
end user_input_handler;
 
architecture Behavioral of user_input_handler is
 
        COMPONENT uart
        Generic (
                CLK_FREQ        : integer := 50;                -- Main frequency (MHz)
                SER_FREQ        : integer := 9600               -- Baud rate (bps)
        );
        Port (
                -- Control
                clk                     : in    std_logic;                                                      -- Main clock
                rst                     : in    std_logic;                                                      -- Main reset
                -- External Interface
                rx                      : in    std_logic;                                                              -- RS232 received serial data
                tx                      : out   std_logic;                                                              -- RS232 transmitted serial data
                -- RS232/UART Configuration
                par_en          : in    std_logic;                                                      -- Parity bit enable
                -- uPC Interface
                tx_req          : in    std_logic;                                                      -- Request SEND of data
                tx_end          : out   std_logic;                                                      -- Data SENDED
                tx_data         : in    std_logic_vector(7 downto 0);    -- Data to transmit
                rx_ready                : out   std_logic;                                                      -- Received data ready to uPC read
                rx_data         : out   std_logic_vector(7 downto 0)     -- Received data 
        );
        END COMPONENT;
 
        COMPONENT TDP_RAM
                Generic (G_DATA_A_SIZE  :natural :=32;
                                        G_ADDR_A_SIZE   :natural :=9;
                                        G_RELATION              :natural :=3;
                                        G_INIT_FILE             :string :="");--log2(SIZE_A/SIZE_B)
                Port ( CLK_A_IN         : in  STD_LOGIC;
                                 WE_A_IN        : in  STD_LOGIC;
                                 ADDR_A_IN      : in  STD_LOGIC_VECTOR (G_ADDR_A_SIZE-1 downto 0);
                                 DATA_A_IN      : in  STD_LOGIC_VECTOR (G_DATA_A_SIZE-1 downto 0);
                                 DATA_A_OUT     : out  STD_LOGIC_VECTOR (G_DATA_A_SIZE-1 downto 0);
                                 CLK_B_IN       : in  STD_LOGIC;
                                 WE_B_IN        : in  STD_LOGIC;
                                 ADDR_B_IN      : in  STD_LOGIC_VECTOR (G_ADDR_A_SIZE+G_RELATION-1 downto 0);
                                 DATA_B_IN      : in  STD_LOGIC_VECTOR (G_DATA_A_SIZE/(2**G_RELATION)-1 downto 0);
                                 DATA_B_OUT : out STD_LOGIC_VECTOR (G_DATA_A_SIZE/(2**G_RELATION)-1 downto 0));
        END COMPONENT;
 
        COMPONENT FONT_MEM
          PORT (
                 clka : IN STD_LOGIC;
                 wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
                 addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
                 dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
                 douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
        END COMPONENT;
 
subtype slv is std_logic_vector;
 
constant C_backspace_cmnd : std_logic_vector(7 downto 0) := X"80";
constant C_esc_cmnd : std_logic_vector(7 downto 0)               := X"81";
constant C_enter_cmnd : std_logic_vector(7 downto 0)             := X"82";
 
constant C_space_char : std_logic_vector(7 downto 0) := X"20";
 
constant C_max_char                     : std_logic_vector(11 downto 0) := X"C2F"; -- 3119 (zero indexed)
constant C_page_height          : std_logic_vector(7 downto 0) := X"26"; -- 39 (zero indexed)
constant C_page_width           : std_logic_vector(7 downto 0) := X"4F"; -- 80 (zero indexed)
constant C_page_width_p1        : std_logic_vector(7 downto 0) := X"50"; -- 80
 
signal char_buf_wr, char_cmd_wr : std_logic := '0';
signal char_buf_wr_addr : unsigned(11 downto 0) := (others => '0');
signal char_buf_wr_data : std_logic_vector(7 downto 0) := (others => '0');
signal ocrx, ocry : unsigned(7 downto 0) := (others => '0');
 
signal keyboard_data, keyboard_data_buf : std_logic_vector(7 downto 0) := (others => '0');
signal keyboard_rd : std_logic := '0';
 
signal char_buf_x_coord : unsigned(7 downto 0);
 
signal debug2 : unsigned(7 downto 0) := (others => '0');
 
type HANDLE_KEYBOARD_ST is (    IDLE,
                                                                                HANDLE_CHARACTER_S0,
                                                                                HANDLE_CHARACTER_S1,
                                                                                HANDLE_COMMAND,
                                                                                HANDLE_BACKSPACE_S0,
                                                                                HANDLE_BACKSPACE_S1,
                                                                                HANDLE_ENTER_S0,
                                                                                HANDLE_ENTER_S1);
 
signal hk_state, hk_next_state : HANDLE_KEYBOARD_ST := IDLE;
 
begin
 
        debug2 <= unsigned(keyboard_data);
 
        ---- CONVERT UART DATA TO KEYBOARD DATA ----
 
        uart_inst : uart
        GENERIC MAP (
                CLK_FREQ        => 100,
                SER_FREQ        => 9600)
        Port Map (
                clk             => CLK_IN,
                rst             => '0',
                rx                      => RX_IN,
                tx                      => TX_OUT,
                par_en  => '1',
                tx_req  => '0',
                tx_end  => open,
                tx_data => (others => '0'),
                rx_ready        => keyboard_rd,
                rx_data => keyboard_data);
 
        ---- HANDLE KEYBOARD DATA ----
 
   SYNC_PROC: process(CLK_IN)
   begin
      if rising_edge(CLK_IN) then
                        hk_state <= hk_next_state;
      end if;
   end process;
 
        process(CLK_IN)
        begin
                if rising_edge(CLK_IN) then
                        if hk_state = IDLE and keyboard_rd = '1' then
                                keyboard_data_buf <= keyboard_data;
                        end if;
                end if;
        end process;
 
        process(CLK_IN)
        begin
                if rising_edge(CLK_IN) then
                        if hk_state = HANDLE_CHARACTER_S0 then
                                char_buf_wr <= '1';
                        elsif hk_state = HANDLE_BACKSPACE_S1 then
                                char_buf_wr <= '1';
                        else
                                char_buf_wr <= '0';
                        end if;
                end if;
        end process;
 
        process(CLK_IN)
        begin
                if rising_edge(CLK_IN) then
                        if hk_state = HANDLE_CHARACTER_S0 then
                                char_buf_wr_data <= keyboard_data_buf;
                        elsif hk_state = HANDLE_BACKSPACE_S1 then
                                char_buf_wr_data <= C_space_char;
                        end if;
                end if;
        end process;
 
        process(CLK_IN)
        begin
                if rising_edge(CLK_IN) then
                        if hk_state = HANDLE_CHARACTER_S1 then
                                char_buf_wr_addr <= char_buf_wr_addr + 1;
                        elsif hk_state = HANDLE_BACKSPACE_S0 then
                                char_buf_wr_addr <= char_buf_wr_addr - 1;
                        elsif hk_state = HANDLE_ENTER_S1 then
                                char_buf_wr_addr <= char_buf_wr_addr + RESIZE(char_buf_x_coord, 12);
                        end if;
                end if;
        end process;
 
        process(CLK_IN)
        begin
                if rising_edge(CLK_IN) then
                        if hk_state = HANDLE_ENTER_S0 then
                                char_buf_x_coord <= unsigned(C_page_width_p1) - unsigned(ocrx);
                        end if;
                end if;
        end process;
 
   NEXT_STATE_DECODE: process (hk_state, keyboard_rd, keyboard_data(7), keyboard_data_buf)
   begin
      hk_next_state <= hk_state;  --default is to stay in current state
      case (hk_state) is
         when IDLE =>
            if keyboard_rd = '1' then
                                        if keyboard_data(7) = '0' then
                                                if slv(char_buf_wr_addr) /= C_max_char then
                                                        hk_next_state <= HANDLE_CHARACTER_S0;
                                                else
                                                        hk_next_state <= IDLE;
                                                end if;
                                        else
                                                hk_next_state <= HANDLE_COMMAND;
                                        end if;
            end if;
         when HANDLE_CHARACTER_S0 =>
            hk_next_state <= HANDLE_CHARACTER_S1;
                        when HANDLE_CHARACTER_S1 =>
            hk_next_state <= IDLE;
         when HANDLE_COMMAND =>
                                if keyboard_data_buf = C_backspace_cmnd then
                                        if slv(char_buf_wr_addr) /= X"00" then
                                                hk_next_state <= HANDLE_BACKSPACE_S0;
                                        else
                                                hk_next_state <= IDLE;
                                        end if;
                                elsif keyboard_data_buf = C_enter_cmnd then
                                        hk_next_state <= HANDLE_ENTER_S0;
                                else
                                        hk_next_state <= IDLE;
                                end if;
                        when HANDLE_BACKSPACE_S0 =>
                                hk_next_state <= HANDLE_BACKSPACE_S1;
                        when HANDLE_BACKSPACE_S1 =>
                                hk_next_state <= IDLE;
                        when HANDLE_ENTER_S0 =>
                                hk_next_state <= HANDLE_ENTER_S1;
                        when HANDLE_ENTER_S1 =>
                                hk_next_state <= IDLE;
         when others =>
            hk_next_state <= IDLE;
      end case;
   end process;
 
 
        DEBUG_OUT <= slv(char_buf_x_coord);
        DEBUG_OUT2 <= slv(debug2);
 
        ---- HANDLE CURSOR POSITION ----        
 
        CURSORPOS_X_OUT <= slv(ocrx);
        CURSORPOS_Y_OUT <= slv(ocry);
 
        process(CLK_IN)
        begin
                if rising_edge(CLK_IN) then
                        if hk_state = HANDLE_CHARACTER_S1 then
                                if slv(ocrx) = C_page_width and slv(ocry) /= C_page_height then
                                        ocrx <= X"00";
                                else
                                        ocrx <= ocrx + 1;
                                end if;
                                if slv(ocrx) = C_page_width then
                                        if slv(ocry) /= C_page_height then
                                                ocry <= ocry + 1;
                                        end if;
                                end if;
                        elsif hk_state = HANDLE_BACKSPACE_S1 then
                                if slv(ocrx) = X"00" and slv(ocry) /= X"00" then
                                        ocrx <= unsigned(C_page_width);
                                else
                                        ocrx <= ocrx - 1;
                                end if;
                                if slv(ocrx) = X"00" then
                                        if ocry /= X"00" then
                                                ocry <= ocry - 1;
                                        end if;
                                end if;
                        elsif hk_state = HANDLE_ENTER_S0 and slv(ocry) /= C_page_height then
                                ocrx <= X"00";
                                ocry <= ocry + 1;
                        end if;
                end if;
        end process;
 
        ---- SCREEN MEMORY ----
 
        char_buf : TDP_RAM
        Generic Map ( G_DATA_A_SIZE     => TEXT_DATA_OUT'length,
                                          G_ADDR_A_SIZE => TEXT_ADDR_IN'length,
                                          G_RELATION            => 0, --log2(SIZE_A/SIZE_B)
                                          G_INIT_FILE           => "./coe_dir/ascii_space.coe")
   Port Map ( CLK_A_IN          => CLK_IN,
                                  WE_A_IN               => '0',
                                  ADDR_A_IN     => TEXT_ADDR_IN,
                                  DATA_A_IN             => X"00",
                                  DATA_A_OUT    => TEXT_DATA_OUT,
                                  CLK_B_IN              => CLK_IN,
                                  WE_B_IN               => char_buf_wr,
                                  ADDR_B_IN     => slv(char_buf_wr_addr),
                                  DATA_B_IN     => char_buf_wr_data,
                                  DATA_B_OUT    => open);
 
        Font_Mem_inst : FONT_MEM
          PORT MAP (
                 clka   => CLK_IN,
                 wea            => "0",
                 addra  => FONT_ADDR_IN,
                 dina   => (others => '0'),
                 douta  => FONT_DATA_OUT);
 
end Behavioral;
 

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Subversion Repositories fat_32_file_parser

[/] [fat_32_file_parser/] [trunk/] [user_input_handler.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	craighaywo	`----------------------------------------------------------------------------------`
2			`-- Company:`
3			`-- Engineer:`
4			`--`
5			`-- Create Date: 10:39:01 10/19/2014`
6			`-- Design Name:`
7			`-- Module Name: user_input_handler - Behavioral`
8			`-- Project Name:`
9			`-- Target Devices:`
10			`-- Tool versions:`
11			`-- Description:`
12			`--`
13			`-- Dependencies:`
14			`--`
15			`-- Revision:`
16			`-- Revision 0.01 - File Created`
17			`-- Additional Comments:`
18			`--`
19			`----------------------------------------------------------------------------------`
20			`library IEEE;`
21			`use IEEE.STD_LOGIC_1164.ALL;`
22			`use IEEE.NUMERIC_STD.ALL;`
23
24			`-- Uncomment the following library declaration if instantiating`
25			`-- any Xilinx primitives in this code.`
26			`--library UNISIM;`
27			`--use UNISIM.VComponents.all;`
28
29			`entity user_input_handler is`
30			`Port ( CLK_IN : in STD_LOGIC;`
31			`RX_IN : in STD_LOGIC;`
32			`TX_OUT : out STD_LOGIC;`
33			`TEXT_ADDR_IN : in STD_LOGIC_VECTOR (11 downto 0);`
34			`TEXT_DATA_OUT : out STD_LOGIC_VECTOR (7 downto 0);`
35			`FONT_ADDR_IN : in STD_LOGIC_VECTOR (11 downto 0);`
36			`FONT_DATA_OUT : out STD_LOGIC_VECTOR (7 downto 0);`
37			`CURSORPOS_X_OUT : out STD_LOGIC_VECTOR (7 downto 0);`
38			`CURSORPOS_Y_OUT : out STD_LOGIC_VECTOR (7 downto 0);`
39			`DEBUG_OUT : out STD_LOGIC_VECTOR(7 downto 0);`
40			`DEBUG_OUT2 : out STD_LOGIC_VECTOR(7 downto 0));`
41			`end user_input_handler;`
42
43			`architecture Behavioral of user_input_handler is`
44
45			`COMPONENT uart`
46			`Generic (`
47			`CLK_FREQ : integer := 50; -- Main frequency (MHz)`
48			`SER_FREQ : integer := 9600 -- Baud rate (bps)`
49			`);`
50			`Port (`
51			`-- Control`
52			`clk : in std_logic; -- Main clock`
53			`rst : in std_logic; -- Main reset`
54			`-- External Interface`
55			`rx : in std_logic; -- RS232 received serial data`
56			`tx : out std_logic; -- RS232 transmitted serial data`
57			`-- RS232/UART Configuration`
58			`par_en : in std_logic; -- Parity bit enable`
59			`-- uPC Interface`
60			`tx_req : in std_logic; -- Request SEND of data`
61			`tx_end : out std_logic; -- Data SENDED`
62			`tx_data : in std_logic_vector(7 downto 0); -- Data to transmit`
63			`rx_ready : out std_logic; -- Received data ready to uPC read`
64			`rx_data : out std_logic_vector(7 downto 0) -- Received data`
65			`);`
66			`END COMPONENT;`
67
68			`COMPONENT TDP_RAM`
69			`Generic (G_DATA_A_SIZE :natural :=32;`
70			`G_ADDR_A_SIZE :natural :=9;`
71			`G_RELATION :natural :=3;`
72			`G_INIT_FILE :string :="");--log2(SIZE_A/SIZE_B)`
73			`Port ( CLK_A_IN : in STD_LOGIC;`
74			`WE_A_IN : in STD_LOGIC;`
75			`ADDR_A_IN : in STD_LOGIC_VECTOR (G_ADDR_A_SIZE-1 downto 0);`
76			`DATA_A_IN : in STD_LOGIC_VECTOR (G_DATA_A_SIZE-1 downto 0);`
77			`DATA_A_OUT : out STD_LOGIC_VECTOR (G_DATA_A_SIZE-1 downto 0);`
78			`CLK_B_IN : in STD_LOGIC;`
79			`WE_B_IN : in STD_LOGIC;`
80			`ADDR_B_IN : in STD_LOGIC_VECTOR (G_ADDR_A_SIZE+G_RELATION-1 downto 0);`
81			`DATA_B_IN : in STD_LOGIC_VECTOR (G_DATA_A_SIZE/(2**G_RELATION)-1 downto 0);`
82			`DATA_B_OUT : out STD_LOGIC_VECTOR (G_DATA_A_SIZE/(2**G_RELATION)-1 downto 0));`
83			`END COMPONENT;`
84
85			`COMPONENT FONT_MEM`
86			`PORT (`
87			`clka : IN STD_LOGIC;`
88			`wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);`
89			`addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);`
90			`dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
91			`douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));`
92			`END COMPONENT;`
93
94			`subtype slv is std_logic_vector;`
95
96			`constant C_backspace_cmnd : std_logic_vector(7 downto 0) := X"80";`
97			`constant C_esc_cmnd : std_logic_vector(7 downto 0) := X"81";`
98			`constant C_enter_cmnd : std_logic_vector(7 downto 0) := X"82";`
99
100			`constant C_space_char : std_logic_vector(7 downto 0) := X"20";`
101
102			`constant C_max_char : std_logic_vector(11 downto 0) := X"C2F"; -- 3119 (zero indexed)`
103			`constant C_page_height : std_logic_vector(7 downto 0) := X"26"; -- 39 (zero indexed)`
104			`constant C_page_width : std_logic_vector(7 downto 0) := X"4F"; -- 80 (zero indexed)`
105			`constant C_page_width_p1 : std_logic_vector(7 downto 0) := X"50"; -- 80`
106
107			`signal char_buf_wr, char_cmd_wr : std_logic := '0';`
108			`signal char_buf_wr_addr : unsigned(11 downto 0) := (others => '0');`
109			`signal char_buf_wr_data : std_logic_vector(7 downto 0) := (others => '0');`
110			`signal ocrx, ocry : unsigned(7 downto 0) := (others => '0');`
111
112			`signal keyboard_data, keyboard_data_buf : std_logic_vector(7 downto 0) := (others => '0');`
113			`signal keyboard_rd : std_logic := '0';`
114
115			`signal char_buf_x_coord : unsigned(7 downto 0);`
116
117			`signal debug2 : unsigned(7 downto 0) := (others => '0');`
118
119			`type HANDLE_KEYBOARD_ST is ( IDLE,`
120			`HANDLE_CHARACTER_S0,`
121			`HANDLE_CHARACTER_S1,`
122			`HANDLE_COMMAND,`
123			`HANDLE_BACKSPACE_S0,`
124			`HANDLE_BACKSPACE_S1,`
125			`HANDLE_ENTER_S0,`
126			`HANDLE_ENTER_S1);`
127
128			`signal hk_state, hk_next_state : HANDLE_KEYBOARD_ST := IDLE;`
129
130			`begin`
131
132			`debug2 <= unsigned(keyboard_data);`
133
134			`---- CONVERT UART DATA TO KEYBOARD DATA ----`
135
136			`uart_inst : uart`
137			`GENERIC MAP (`
138			`CLK_FREQ => 100,`
139			`SER_FREQ => 9600)`
140			`Port Map (`
141			`clk => CLK_IN,`
142			`rst => '0',`
143			`rx => RX_IN,`
144			`tx => TX_OUT,`
145			`par_en => '1',`
146			`tx_req => '0',`
147			`tx_end => open,`
148			`tx_data => (others => '0'),`
149			`rx_ready => keyboard_rd,`
150			`rx_data => keyboard_data);`
151
152			`---- HANDLE KEYBOARD DATA ----`
153
154			`SYNC_PROC: process(CLK_IN)`
155			`begin`
156			`if rising_edge(CLK_IN) then`
157			`hk_state <= hk_next_state;`
158			`end if;`
159			`end process;`
160
161			`process(CLK_IN)`
162			`begin`
163			`if rising_edge(CLK_IN) then`
164			`if hk_state = IDLE and keyboard_rd = '1' then`
165			`keyboard_data_buf <= keyboard_data;`
166			`end if;`
167			`end if;`
168			`end process;`
169
170			`process(CLK_IN)`
171			`begin`
172			`if rising_edge(CLK_IN) then`
173			`if hk_state = HANDLE_CHARACTER_S0 then`
174			`char_buf_wr <= '1';`
175			`elsif hk_state = HANDLE_BACKSPACE_S1 then`
176			`char_buf_wr <= '1';`
177			`else`
178			`char_buf_wr <= '0';`
179			`end if;`
180			`end if;`
181			`end process;`
182
183			`process(CLK_IN)`
184			`begin`
185			`if rising_edge(CLK_IN) then`
186			`if hk_state = HANDLE_CHARACTER_S0 then`
187			`char_buf_wr_data <= keyboard_data_buf;`
188			`elsif hk_state = HANDLE_BACKSPACE_S1 then`
189			`char_buf_wr_data <= C_space_char;`
190			`end if;`
191			`end if;`
192			`end process;`
193
194			`process(CLK_IN)`
195			`begin`
196			`if rising_edge(CLK_IN) then`
197			`if hk_state = HANDLE_CHARACTER_S1 then`
198			`char_buf_wr_addr <= char_buf_wr_addr + 1;`
199			`elsif hk_state = HANDLE_BACKSPACE_S0 then`
200			`char_buf_wr_addr <= char_buf_wr_addr - 1;`
201			`elsif hk_state = HANDLE_ENTER_S1 then`
202			`char_buf_wr_addr <= char_buf_wr_addr + RESIZE(char_buf_x_coord, 12);`
203			`end if;`
204			`end if;`
205			`end process;`
206
207			`process(CLK_IN)`
208			`begin`
209			`if rising_edge(CLK_IN) then`
210			`if hk_state = HANDLE_ENTER_S0 then`
211			`char_buf_x_coord <= unsigned(C_page_width_p1) - unsigned(ocrx);`
212			`end if;`
213			`end if;`
214			`end process;`
215
216			`NEXT_STATE_DECODE: process (hk_state, keyboard_rd, keyboard_data(7), keyboard_data_buf)`
217			`begin`
218			`hk_next_state <= hk_state; --default is to stay in current state`
219			`case (hk_state) is`
220			`when IDLE =>`
221			`if keyboard_rd = '1' then`
222			`if keyboard_data(7) = '0' then`
223			`if slv(char_buf_wr_addr) /= C_max_char then`
224			`hk_next_state <= HANDLE_CHARACTER_S0;`
225			`else`
226			`hk_next_state <= IDLE;`
227			`end if;`
228			`else`
229			`hk_next_state <= HANDLE_COMMAND;`
230			`end if;`
231			`end if;`
232			`when HANDLE_CHARACTER_S0 =>`
233			`hk_next_state <= HANDLE_CHARACTER_S1;`
234			`when HANDLE_CHARACTER_S1 =>`
235			`hk_next_state <= IDLE;`
236			`when HANDLE_COMMAND =>`
237			`if keyboard_data_buf = C_backspace_cmnd then`
238			`if slv(char_buf_wr_addr) /= X"00" then`
239			`hk_next_state <= HANDLE_BACKSPACE_S0;`
240			`else`
241			`hk_next_state <= IDLE;`
242			`end if;`
243			`elsif keyboard_data_buf = C_enter_cmnd then`
244			`hk_next_state <= HANDLE_ENTER_S0;`
245			`else`
246			`hk_next_state <= IDLE;`
247			`end if;`
248			`when HANDLE_BACKSPACE_S0 =>`
249			`hk_next_state <= HANDLE_BACKSPACE_S1;`
250			`when HANDLE_BACKSPACE_S1 =>`
251			`hk_next_state <= IDLE;`
252			`when HANDLE_ENTER_S0 =>`
253			`hk_next_state <= HANDLE_ENTER_S1;`
254			`when HANDLE_ENTER_S1 =>`
255			`hk_next_state <= IDLE;`
256			`when others =>`
257			`hk_next_state <= IDLE;`
258			`end case;`
259			`end process;`
260
261
262			`DEBUG_OUT <= slv(char_buf_x_coord);`
263			`DEBUG_OUT2 <= slv(debug2);`
264
265			`---- HANDLE CURSOR POSITION ----`
266
267			`CURSORPOS_X_OUT <= slv(ocrx);`
268			`CURSORPOS_Y_OUT <= slv(ocry);`
269
270			`process(CLK_IN)`
271			`begin`
272			`if rising_edge(CLK_IN) then`
273			`if hk_state = HANDLE_CHARACTER_S1 then`
274			`if slv(ocrx) = C_page_width and slv(ocry) /= C_page_height then`
275			`ocrx <= X"00";`
276			`else`
277			`ocrx <= ocrx + 1;`
278			`end if;`
279			`if slv(ocrx) = C_page_width then`
280			`if slv(ocry) /= C_page_height then`
281			`ocry <= ocry + 1;`
282			`end if;`
283			`end if;`
284			`elsif hk_state = HANDLE_BACKSPACE_S1 then`
285			`if slv(ocrx) = X"00" and slv(ocry) /= X"00" then`
286			`ocrx <= unsigned(C_page_width);`
287			`else`
288			`ocrx <= ocrx - 1;`
289			`end if;`
290			`if slv(ocrx) = X"00" then`
291			`if ocry /= X"00" then`
292			`ocry <= ocry - 1;`
293			`end if;`
294			`end if;`
295			`elsif hk_state = HANDLE_ENTER_S0 and slv(ocry) /= C_page_height then`
296			`ocrx <= X"00";`
297			`ocry <= ocry + 1;`
298			`end if;`
299			`end if;`
300			`end process;`
301
302			`---- SCREEN MEMORY ----`
303
304			`char_buf : TDP_RAM`
305			`Generic Map ( G_DATA_A_SIZE => TEXT_DATA_OUT'length,`
306			`G_ADDR_A_SIZE => TEXT_ADDR_IN'length,`
307			`G_RELATION => 0, --log2(SIZE_A/SIZE_B)`
308			`G_INIT_FILE => "./coe_dir/ascii_space.coe")`
309			`Port Map ( CLK_A_IN => CLK_IN,`
310			`WE_A_IN => '0',`
311			`ADDR_A_IN => TEXT_ADDR_IN,`
312			`DATA_A_IN => X"00",`
313			`DATA_A_OUT => TEXT_DATA_OUT,`
314			`CLK_B_IN => CLK_IN,`
315			`WE_B_IN => char_buf_wr,`
316			`ADDR_B_IN => slv(char_buf_wr_addr),`
317			`DATA_B_IN => char_buf_wr_data,`
318			`DATA_B_OUT => open);`
319
320			`Font_Mem_inst : FONT_MEM`
321			`PORT MAP (`
322			`clka => CLK_IN,`
323			`wea => "0",`
324			`addra => FONT_ADDR_IN,`
325			`dina => (others => '0'),`
326			`douta => FONT_DATA_OUT);`
327
328			`end Behavioral;`
329