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[/] [firewire/] [trunk/] [bench/] [verilog/] [fw_host_tasks.v] - Blame information for rev 22

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1 12 johnsonw10
// $Id: fw_host_tasks.v,v 1.1 2002-03-10 17:18:07 johnsonw10 Exp $
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// FIREWIRE IP Core                                             ////
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////                                                              ////
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//// This file is part of the firewire project                    ////
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//// http://www.opencores.org/cores/firewire/                     ////
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////                                                              ////
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//// Description                                                  ////
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//// Implementation of firewire IP core according to              ////
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//// firewire IP core specification document.                     ////
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////                                                              ////
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//// To Do:                                                       ////
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//// -                                                            ////
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////                                                              ////
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//// Author(s):                                                   ////
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//// - johnsonw10@opencores.org                                   ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE. See the GNU Lesser General Public License for more  ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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//
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//
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task host_write_reg;
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input [7:0] addr;
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input [31:0] data;
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begin
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    @ (posedge sclk);
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    host_cs_n <= 0;
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    host_wr_n <= 0;
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    host_addr <= addr;
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    host_data_out <= data;
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    @ (posedge sclk);
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    host_cs_n <= 1;
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    host_wr_n <= 1;
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    host_data_out <= 32'hzzzz_zzzz;
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end
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endtask // host_write_reg
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task host_write_atxf;
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input data_num;
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integer data_num;
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reg [0:31] temp;
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integer i;
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begin
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    i = 0;
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    while (i < data_num) begin
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        temp <= send_buf[i];
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        @ (posedge sclk);
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        if (!atxf_ff) begin
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            atxf_wr <= 1;
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            atxf_din <= temp;
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            i = i + 1;  // have to use blocking assignment
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        end
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    end
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    @ (posedge sclk);
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    atxf_wr <= 0;
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end
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endtask // host_write_atxf

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