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[/] [fpuvhdl/] [trunk/] [fpuvhdl/] [multiplier/] [fpmul_single_cycle.vhd] - Blame information for rev 4

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1 3 gmarcus
-- VHDL Entity HAVOC.FPmul.symbol
2
--
3
-- Created by
4
-- Guillermo Marcus, gmarcus@ieee.org
5
-- using Mentor Graphics FPGA Advantage tools.
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--
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-- Visit "http://fpga.mty.itesm.mx" for more info.
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--
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-- 2003-2004. V1.0
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--
11
 
12
LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
15
 
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ENTITY FPmul IS
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   PORT(
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      FP_A : IN     std_logic_vector (31 DOWNTO 0);
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      FP_B : IN     std_logic_vector (31 DOWNTO 0);
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      clk  : IN     std_logic;
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      FP_Z : OUT    std_logic_vector (31 DOWNTO 0)
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   );
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24
-- Declarations
25
 
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END FPmul ;
27
 
28
--
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-- VHDL Architecture HAVOC.FPmul.single_cycle
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--
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-- Created by
32
-- Guillermo Marcus, gmarcus@ieee.org
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-- using Mentor Graphics FPGA Advantage tools.
34
--
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-- Visit "http://fpga.mty.itesm.mx" for more info.
36
--
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-- Copyright 2003-2004. V1.0
38
--
39
 
40
 
41
LIBRARY ieee;
42
USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
44
 
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ARCHITECTURE single_cycle OF FPmul IS
46
 
47
   -- Architecture declarations
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      -- Non hierarchical truthtable declarations
49
 
50
 
51
 
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   -- Internal signal declarations
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   SIGNAL A_EXP         : std_logic_vector(7 DOWNTO 0);
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   SIGNAL A_SIG         : std_logic_vector(31 DOWNTO 0);
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   SIGNAL A_SIGN        : std_logic;
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   SIGNAL A_isINF       : std_logic;
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   SIGNAL A_isNaN       : std_logic;
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   SIGNAL A_isZ         : std_logic;
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   SIGNAL B_EXP         : std_logic_vector(7 DOWNTO 0);
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   SIGNAL B_SIG         : std_logic_vector(31 DOWNTO 0);
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   SIGNAL B_SIGN        : std_logic;
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   SIGNAL B_isINF       : std_logic;
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   SIGNAL B_isNaN       : std_logic;
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   SIGNAL B_isZ         : std_logic;
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   SIGNAL EXP_addout    : std_logic_vector(7 DOWNTO 0);
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   SIGNAL EXP_in        : std_logic_vector(7 DOWNTO 0);
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   SIGNAL EXP_out       : std_logic_vector(7 DOWNTO 0);
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   SIGNAL EXP_out_norm  : std_logic_vector(7 DOWNTO 0);
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   SIGNAL EXP_out_round : std_logic_vector(7 DOWNTO 0);
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   SIGNAL SIGN_out      : std_logic;
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   SIGNAL SIG_in        : std_logic_vector(27 DOWNTO 0);
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   SIGNAL SIG_isZ       : std_logic;
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   SIGNAL SIG_out       : std_logic_vector(22 DOWNTO 0);
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   SIGNAL SIG_out_norm  : std_logic_vector(27 DOWNTO 0);
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   SIGNAL SIG_out_norm2 : std_logic_vector(27 DOWNTO 0);
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   SIGNAL SIG_out_round : std_logic_vector(27 DOWNTO 0);
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   SIGNAL dout          : std_logic;
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   SIGNAL isINF         : std_logic;
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   SIGNAL isINF_tab     : std_logic;
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   SIGNAL isNaN         : std_logic;
81
   SIGNAL isZ           : std_logic;
82
   SIGNAL isZ_tab       : std_logic;
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   SIGNAL prod          : std_logic_vector(63 DOWNTO 0);
84
 
85
 
86
   -- Component Declarations
87
   COMPONENT FPnormalize
88
   GENERIC (
89
      SIG_width : integer := 28
90
   );
91
   PORT (
92
      SIG_in  : IN     std_logic_vector (SIG_width-1 DOWNTO 0);
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      EXP_in  : IN     std_logic_vector (7 DOWNTO 0);
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      SIG_out : OUT    std_logic_vector (SIG_width-1 DOWNTO 0);
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      EXP_out : OUT    std_logic_vector (7 DOWNTO 0)
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   );
97
   END COMPONENT;
98
   COMPONENT FPround
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   GENERIC (
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      SIG_width : integer := 28
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   );
102
   PORT (
103
      SIG_in  : IN     std_logic_vector (SIG_width-1 DOWNTO 0);
104
      EXP_in  : IN     std_logic_vector (7 DOWNTO 0);
105
      SIG_out : OUT    std_logic_vector (SIG_width-1 DOWNTO 0);
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      EXP_out : OUT    std_logic_vector (7 DOWNTO 0)
107
   );
108
   END COMPONENT;
109
   COMPONENT PackFP
110
   PORT (
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      SIGN  : IN     std_logic ;
112
      EXP   : IN     std_logic_vector (7 DOWNTO 0);
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      SIG   : IN     std_logic_vector (22 DOWNTO 0);
114
      isNaN : IN     std_logic ;
115
      isINF : IN     std_logic ;
116
      isZ   : IN     std_logic ;
117
      FP    : OUT    std_logic_vector (31 DOWNTO 0)
118
   );
119
   END COMPONENT;
120
   COMPONENT UnpackFP
121
   PORT (
122
      FP    : IN     std_logic_vector (31 DOWNTO 0);
123
      SIG   : OUT    std_logic_vector (31 DOWNTO 0);
124
      EXP   : OUT    std_logic_vector (7 DOWNTO 0);
125
      SIGN  : OUT    std_logic ;
126
      isNaN : OUT    std_logic ;
127
      isINF : OUT    std_logic ;
128
      isZ   : OUT    std_logic ;
129
      isDN  : OUT    std_logic
130
   );
131
   END COMPONENT;
132
 
133
   -- Optional embedded configurations
134
   -- pragma synthesis_off
135 4 gmarcus
   FOR ALL : FPnormalize USE ENTITY work.FPnormalize;
136
   FOR ALL : FPround USE ENTITY work.FPround;
137
   FOR ALL : PackFP USE ENTITY work.PackFP;
138
   FOR ALL : UnpackFP USE ENTITY work.UnpackFP;
139 3 gmarcus
   -- pragma synthesis_on
140
 
141
 
142
BEGIN
143
   -- Architecture concurrent statements
144
   -- HDL Embedded Text Block 1 eb1
145
   -- eb1 1
146
   SIG_in <= prod(47 DOWNTO 20);
147
 
148
   -- HDL Embedded Text Block 2 eb2
149
   -- eb2 
150
 
151
   SIG_out <= SIG_out_norm2(25 DOWNTO 3);
152
 
153
   -- HDL Embedded Text Block 3 eb3
154
   -- eb3 3
155
   PROCESS(isZ,isINF_tab, A_EXP, B_EXP, EXP_out)
156
   BEGIN
157
      IF isZ='0' THEN
158
         IF isINF_tab='1' THEN
159
            isINF <= '1';
160
         ELSIF EXP_out=X"FF" THEN
161
            isINF <='1';
162
         ELSIF (A_EXP(7)='1' AND B_EXP(7)='1' AND (EXP_out(7)='0'))  THEN
163
            isINF <='1';
164
         ELSE
165
            isINF <= '0';
166
         END IF;
167
      ELSE
168
         isINF <= '0';
169
      END IF;
170
   END PROCESS;
171
 
172
   -- HDL Embedded Block 4 eb4
173
   -- Non hierarchical truthtable
174
   ---------------------------------------------------------------------------
175
   eb4_truth_process: PROCESS(A_isINF, A_isNaN, A_isZ, B_isINF, B_isNaN, B_isZ)
176
   ---------------------------------------------------------------------------
177
   BEGIN
178
      -- Block 1
179
      IF (A_isINF = '0') AND (A_isNaN = '0') AND (A_isZ = '0') AND (B_isINF = '0') AND (B_isNaN = '0') AND (B_isZ = '0') THEN
180
         isZ_tab <= '0';
181
         isINF_tab <= '0';
182
         isNaN <= '0';
183
      ELSIF (A_isINF = '1') AND (B_isZ = '1') THEN
184
         isZ_tab <= '0';
185
         isINF_tab <= '0';
186
         isNaN <= '1';
187
      ELSIF (A_isZ = '1') AND (B_isINF = '1') THEN
188
         isZ_tab <= '0';
189
         isINF_tab <= '0';
190
         isNaN <= '1';
191
      ELSIF (A_isINF = '1') THEN
192
         isZ_tab <= '0';
193
         isINF_tab <= '1';
194
         isNaN <= '0';
195
      ELSIF (B_isINF = '1') THEN
196
         isZ_tab <= '0';
197
         isINF_tab <= '1';
198
         isNaN <= '0';
199
      ELSIF (A_isNaN = '1') THEN
200
         isZ_tab <= '0';
201
         isINF_tab <= '0';
202
         isNaN <= '1';
203
      ELSIF (B_isNaN = '1') THEN
204
         isZ_tab <= '0';
205
         isINF_tab <= '0';
206
         isNaN <= '1';
207
      ELSIF (A_isZ = '1') THEN
208
         isZ_tab <= '1';
209
         isINF_tab <= '0';
210
         isNaN <= '0';
211
      ELSIF (B_isZ = '1') THEN
212
         isZ_tab <= '1';
213
         isINF_tab <= '0';
214
         isNaN <= '0';
215
      ELSE
216
         isZ_tab <= '0';
217
         isINF_tab <= '0';
218
         isNaN <= '0';
219
      END IF;
220
 
221
   END PROCESS eb4_truth_process;
222
 
223
   -- Architecture concurrent statements
224
 
225
 
226
 
227
   -- HDL Embedded Text Block 5 eb5
228
   -- eb5 5
229
   EXP_in <= (NOT EXP_addout(7)) & EXP_addout(6 DOWNTO 0);
230
 
231
   -- HDL Embedded Text Block 6 eb6
232
   -- eb6 6
233
   PROCESS(SIG_out_norm2,A_EXP,B_EXP, EXP_out)
234
   BEGIN
235 4 gmarcus
      IF ( EXP_out(7)='1' AND
236
                    ( (A_EXP(7)='0' AND NOT (A_EXP=X"7F")) AND
237
                           (B_EXP(7)='0' AND NOT (B_EXP=X"7F")) ) ) OR
238
         (SIG_out_norm2(26 DOWNTO 3)=X"000000") THEN
239 3 gmarcus
         -- Underflow or zero significand
240
         SIG_isZ <= '1';
241
      ELSE
242
         SIG_isZ <= '0';
243
      END IF;
244
   END PROCESS;
245
 
246
 
247
   -- ModuleWare code(v1.1) for instance 'I4' of 'add'
248
   I4combo: PROCESS (A_EXP, B_EXP, dout)
249
   VARIABLE mw_I4t0 : std_logic_vector(8 DOWNTO 0);
250
   VARIABLE mw_I4t1 : std_logic_vector(8 DOWNTO 0);
251
   VARIABLE mw_I4sum : unsigned(8 DOWNTO 0);
252
   VARIABLE mw_I4carry : std_logic;
253
   BEGIN
254
      mw_I4t0 := '0' & A_EXP;
255
      mw_I4t1 := '0' & B_EXP;
256
      mw_I4carry := dout;
257
      mw_I4sum := unsigned(mw_I4t0) + unsigned(mw_I4t1) + mw_I4carry;
258
      EXP_addout <= conv_std_logic_vector(mw_I4sum(7 DOWNTO 0),8);
259
   END PROCESS I4combo;
260
 
261
   -- ModuleWare code(v1.1) for instance 'I2' of 'mult'
262
   I2combo : PROCESS (A_SIG, B_SIG)
263
   VARIABLE dtemp : unsigned(63 DOWNTO 0);
264
   BEGIN
265
      dtemp := (unsigned(A_SIG) * unsigned(B_SIG));
266
      prod <= std_logic_vector(dtemp);
267
   END PROCESS I2combo;
268
 
269
   -- ModuleWare code(v1.1) for instance 'I7' of 'or'
270
   isZ <= SIG_isZ OR isZ_tab;
271
 
272
   -- ModuleWare code(v1.1) for instance 'I6' of 'vdd'
273
   dout <= '1';
274
 
275
   -- ModuleWare code(v1.1) for instance 'I3' of 'xor'
276
   SIGN_out <= A_SIGN XOR B_SIGN;
277
 
278
   -- Instance port mappings.
279
   I9 : FPnormalize
280
      GENERIC MAP (
281
         SIG_width => 28
282
      )
283
      PORT MAP (
284
         SIG_in  => SIG_in,
285
         EXP_in  => EXP_in,
286
         SIG_out => SIG_out_norm,
287
         EXP_out => EXP_out_norm
288
      );
289
   I10 : FPnormalize
290
      GENERIC MAP (
291
         SIG_width => 28
292
      )
293
      PORT MAP (
294
         SIG_in  => SIG_out_round,
295
         EXP_in  => EXP_out_round,
296
         SIG_out => SIG_out_norm2,
297
         EXP_out => EXP_out
298
      );
299
   I11 : FPround
300
      GENERIC MAP (
301
         SIG_width => 28
302
      )
303
      PORT MAP (
304
         SIG_in  => SIG_out_norm,
305
         EXP_in  => EXP_out_norm,
306
         SIG_out => SIG_out_round,
307
         EXP_out => EXP_out_round
308
      );
309
   I5 : PackFP
310
      PORT MAP (
311
         SIGN  => SIGN_out,
312
         EXP   => EXP_out,
313
         SIG   => SIG_out,
314
         isNaN => isNaN,
315
         isINF => isINF,
316
         isZ   => isZ,
317
         FP    => FP_Z
318
      );
319
   I0 : UnpackFP
320
      PORT MAP (
321
         FP    => FP_A,
322
         SIG   => A_SIG,
323
         EXP   => A_EXP,
324
         SIGN  => A_SIGN,
325
         isNaN => A_isNaN,
326
         isINF => A_isINF,
327
         isZ   => A_isZ,
328
         isDN  => OPEN
329
      );
330
   I1 : UnpackFP
331
      PORT MAP (
332
         FP    => FP_B,
333
         SIG   => B_SIG,
334
         EXP   => B_EXP,
335
         SIGN  => B_SIGN,
336
         isNaN => B_isNaN,
337
         isINF => B_isINF,
338
         isZ   => B_isZ,
339
         isDN  => OPEN
340
      );
341
 
342
END single_cycle;

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