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[/] [funbase_ip_library/] [trunk/] [Altera/] [ip.hwp.cpu/] [nios_ii_sdram/] [2.0/] [hdl/] [nios2_sdram/] [synthesis/] [nios2_sdram.v] - Blame information for rev 177

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1 177 lanttu 
// nios2_sdram.v
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// Generated using ACDS version 12.1 177 at 2013.06.11.13:52:14
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`timescale 1 ps / 1 ps
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module nios2_sdram (
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                input  wire [31:0] hibi_pe_dma_data_in,  // hibi_pe_dma.data_in
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                input  wire        hibi_pe_dma_av_in,    //            .av_in
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                input  wire        hibi_pe_dma_empty_in, //            .empty_in
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                input  wire [4:0]  hibi_pe_dma_comm_in,  //            .comm_in
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                output wire        hibi_pe_dma_re_out,   //            .re_out
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                output wire [31:0] hibi_pe_dma_data_out, //            .data_out
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                output wire        hibi_pe_dma_av_out,   //            .av_out
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                input  wire        hibi_pe_dma_full_in,  //            .full_in
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                output wire [4:0]  hibi_pe_dma_comm_out, //            .comm_out
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                output wire        hibi_pe_dma_we_out,   //            .we_out
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                output wire [11:0] sdram_0_addr,         //     sdram_0.addr
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                output wire [1:0]  sdram_0_ba,           //            .ba
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                output wire        sdram_0_cas_n,        //            .cas_n
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                output wire        sdram_0_cke,          //            .cke
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                output wire        sdram_0_cs_n,         //            .cs_n
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                inout  wire [15:0] sdram_0_dq,           //            .dq
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                output wire [1:0]  sdram_0_dqm,          //            .dqm
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                output wire        sdram_0_ras_n,        //            .ras_n
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                output wire        sdram_0_we_n,         //            .we_n
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                input  wire        reset_reset_n,        //       reset.reset_n
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                input  wire        clk_clk               //         clk.clk
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        );
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        wire          nios2_qsys_1_instruction_master_waitrequest;                                                         // nios2_qsys_1_instruction_master_translator:av_waitrequest -> nios2_qsys_1:i_waitrequest
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        wire   [25:0] nios2_qsys_1_instruction_master_address;                                                             // nios2_qsys_1:i_address -> nios2_qsys_1_instruction_master_translator:av_address
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        wire          nios2_qsys_1_instruction_master_read;                                                                // nios2_qsys_1:i_read -> nios2_qsys_1_instruction_master_translator:av_read
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        wire   [31:0] nios2_qsys_1_instruction_master_readdata;                                                            // nios2_qsys_1_instruction_master_translator:av_readdata -> nios2_qsys_1:i_readdata
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        wire          nios2_qsys_1_instruction_master_readdatavalid;                                                       // nios2_qsys_1_instruction_master_translator:av_readdatavalid -> nios2_qsys_1:i_readdatavalid
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        wire          nios2_qsys_1_data_master_waitrequest;                                                                // nios2_qsys_1_data_master_translator:av_waitrequest -> nios2_qsys_1:d_waitrequest
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        wire   [31:0] nios2_qsys_1_data_master_writedata;                                                                  // nios2_qsys_1:d_writedata -> nios2_qsys_1_data_master_translator:av_writedata
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        wire   [25:0] nios2_qsys_1_data_master_address;                                                                    // nios2_qsys_1:d_address -> nios2_qsys_1_data_master_translator:av_address
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        wire          nios2_qsys_1_data_master_write;                                                                      // nios2_qsys_1:d_write -> nios2_qsys_1_data_master_translator:av_write
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        wire          nios2_qsys_1_data_master_read;                                                                       // nios2_qsys_1:d_read -> nios2_qsys_1_data_master_translator:av_read
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        wire   [31:0] nios2_qsys_1_data_master_readdata;                                                                   // nios2_qsys_1_data_master_translator:av_readdata -> nios2_qsys_1:d_readdata
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        wire          nios2_qsys_1_data_master_debugaccess;                                                                // nios2_qsys_1:jtag_debug_module_debugaccess_to_roms -> nios2_qsys_1_data_master_translator:av_debugaccess
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        wire          nios2_qsys_1_data_master_readdatavalid;                                                              // nios2_qsys_1_data_master_translator:av_readdatavalid -> nios2_qsys_1:d_readdatavalid
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        wire    [3:0] nios2_qsys_1_data_master_byteenable;                                                                 // nios2_qsys_1:d_byteenable -> nios2_qsys_1_data_master_translator:av_byteenable
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        wire   [31:0] nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_writedata;                             // nios2_qsys_1_jtag_debug_module_translator:av_writedata -> nios2_qsys_1:jtag_debug_module_writedata
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        wire    [8:0] nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_address;                               // nios2_qsys_1_jtag_debug_module_translator:av_address -> nios2_qsys_1:jtag_debug_module_address
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        wire          nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_chipselect;                            // nios2_qsys_1_jtag_debug_module_translator:av_chipselect -> nios2_qsys_1:jtag_debug_module_select
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        wire          nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_write;                                 // nios2_qsys_1_jtag_debug_module_translator:av_write -> nios2_qsys_1:jtag_debug_module_write
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        wire   [31:0] nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_readdata;                              // nios2_qsys_1:jtag_debug_module_readdata -> nios2_qsys_1_jtag_debug_module_translator:av_readdata
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        wire          nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer;                         // nios2_qsys_1_jtag_debug_module_translator:av_begintransfer -> nios2_qsys_1:jtag_debug_module_begintransfer
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        wire          nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess;                           // nios2_qsys_1_jtag_debug_module_translator:av_debugaccess -> nios2_qsys_1:jtag_debug_module_debugaccess
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        wire    [3:0] nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_byteenable;                            // nios2_qsys_1_jtag_debug_module_translator:av_byteenable -> nios2_qsys_1:jtag_debug_module_byteenable
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        wire          sdram_0_s1_translator_avalon_anti_slave_0_waitrequest;                                               // sdram_0:za_waitrequest -> sdram_0_s1_translator:av_waitrequest
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        wire   [15:0] sdram_0_s1_translator_avalon_anti_slave_0_writedata;                                                 // sdram_0_s1_translator:av_writedata -> sdram_0:az_data
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        wire   [21:0] sdram_0_s1_translator_avalon_anti_slave_0_address;                                                   // sdram_0_s1_translator:av_address -> sdram_0:az_addr
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        wire          sdram_0_s1_translator_avalon_anti_slave_0_chipselect;                                                // sdram_0_s1_translator:av_chipselect -> sdram_0:az_cs
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        wire          sdram_0_s1_translator_avalon_anti_slave_0_write;                                                     // sdram_0_s1_translator:av_write -> sdram_0:az_wr_n
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        wire          sdram_0_s1_translator_avalon_anti_slave_0_read;                                                      // sdram_0_s1_translator:av_read -> sdram_0:az_rd_n
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        wire   [15:0] sdram_0_s1_translator_avalon_anti_slave_0_readdata;                                                  // sdram_0:za_data -> sdram_0_s1_translator:av_readdata
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        wire          sdram_0_s1_translator_avalon_anti_slave_0_readdatavalid;                                             // sdram_0:za_valid -> sdram_0_s1_translator:av_readdatavalid
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        wire    [1:0] sdram_0_s1_translator_avalon_anti_slave_0_byteenable;                                                // sdram_0_s1_translator:av_byteenable -> sdram_0:az_be_n
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        wire          jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest;                            // jtag_uart_1:av_waitrequest -> jtag_uart_1_avalon_jtag_slave_translator:av_waitrequest
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        wire   [31:0] jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata;                              // jtag_uart_1_avalon_jtag_slave_translator:av_writedata -> jtag_uart_1:av_writedata
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        wire    [0:0] jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_address;                                // jtag_uart_1_avalon_jtag_slave_translator:av_address -> jtag_uart_1:av_address
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        wire          jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect;                             // jtag_uart_1_avalon_jtag_slave_translator:av_chipselect -> jtag_uart_1:av_chipselect
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        wire          jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_write;                                  // jtag_uart_1_avalon_jtag_slave_translator:av_write -> jtag_uart_1:av_write_n
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        wire          jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_read;                                   // jtag_uart_1_avalon_jtag_slave_translator:av_read -> jtag_uart_1:av_read_n
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        wire   [31:0] jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata;                               // jtag_uart_1:av_readdata -> jtag_uart_1_avalon_jtag_slave_translator:av_readdata
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        wire   [15:0] timer_1_s1_translator_avalon_anti_slave_0_writedata;                                                 // timer_1_s1_translator:av_writedata -> timer_1:writedata
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        wire    [2:0] timer_1_s1_translator_avalon_anti_slave_0_address;                                                   // timer_1_s1_translator:av_address -> timer_1:address
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        wire          timer_1_s1_translator_avalon_anti_slave_0_chipselect;                                                // timer_1_s1_translator:av_chipselect -> timer_1:chipselect
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        wire          timer_1_s1_translator_avalon_anti_slave_0_write;                                                     // timer_1_s1_translator:av_write -> timer_1:write_n
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        wire   [15:0] timer_1_s1_translator_avalon_anti_slave_0_readdata;                                                  // timer_1:readdata -> timer_1_s1_translator:av_readdata
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        wire   [15:0] timer_0_s1_translator_avalon_anti_slave_0_writedata;                                                 // timer_0_s1_translator:av_writedata -> timer_0:writedata
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        wire    [2:0] timer_0_s1_translator_avalon_anti_slave_0_address;                                                   // timer_0_s1_translator:av_address -> timer_0:address
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        wire          timer_0_s1_translator_avalon_anti_slave_0_chipselect;                                                // timer_0_s1_translator:av_chipselect -> timer_0:chipselect
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        wire          timer_0_s1_translator_avalon_anti_slave_0_write;                                                     // timer_0_s1_translator:av_write -> timer_0:write_n
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        wire   [15:0] timer_0_s1_translator_avalon_anti_slave_0_readdata;                                                  // timer_0:readdata -> timer_0_s1_translator:av_readdata
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        wire    [0:0] sysid_qsys_1_control_slave_translator_avalon_anti_slave_0_address;                                   // sysid_qsys_1_control_slave_translator:av_address -> sysid_qsys_1:address
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        wire   [31:0] sysid_qsys_1_control_slave_translator_avalon_anti_slave_0_readdata;                                  // sysid_qsys_1:readdata -> sysid_qsys_1_control_slave_translator:av_readdata
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        wire   [31:0] onchip_memory2_1_s1_translator_avalon_anti_slave_0_writedata;                                        // onchip_memory2_1_s1_translator:av_writedata -> onchip_memory2_1:writedata
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        wire   [10:0] onchip_memory2_1_s1_translator_avalon_anti_slave_0_address;                                          // onchip_memory2_1_s1_translator:av_address -> onchip_memory2_1:address
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        wire          onchip_memory2_1_s1_translator_avalon_anti_slave_0_chipselect;                                       // onchip_memory2_1_s1_translator:av_chipselect -> onchip_memory2_1:chipselect
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        wire          onchip_memory2_1_s1_translator_avalon_anti_slave_0_clken;                                            // onchip_memory2_1_s1_translator:av_clken -> onchip_memory2_1:clken
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        wire          onchip_memory2_1_s1_translator_avalon_anti_slave_0_write;                                            // onchip_memory2_1_s1_translator:av_write -> onchip_memory2_1:write
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        wire   [31:0] onchip_memory2_1_s1_translator_avalon_anti_slave_0_readdata;                                         // onchip_memory2_1:readdata -> onchip_memory2_1_s1_translator:av_readdata
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        wire    [3:0] onchip_memory2_1_s1_translator_avalon_anti_slave_0_byteenable;                                       // onchip_memory2_1_s1_translator:av_byteenable -> onchip_memory2_1:byteenable
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        wire          hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest;                             // hibi_pe_dma_0:avalon_cfg_waitrequest_out -> hibi_pe_dma_0_avalon_slave_0_translator:av_waitrequest
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        wire   [31:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata;                               // hibi_pe_dma_0_avalon_slave_0_translator:av_writedata -> hibi_pe_dma_0:avalon_cfg_writedata_in
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        wire    [6:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_address;                                 // hibi_pe_dma_0_avalon_slave_0_translator:av_address -> hibi_pe_dma_0:avalon_cfg_addr_in
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        wire          hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_chipselect;                              // hibi_pe_dma_0_avalon_slave_0_translator:av_chipselect -> hibi_pe_dma_0:avalon_cfg_cs_in
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        wire          hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_write;                                   // hibi_pe_dma_0_avalon_slave_0_translator:av_write -> hibi_pe_dma_0:avalon_cfg_we_in
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        wire          hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_read;                                    // hibi_pe_dma_0_avalon_slave_0_translator:av_read -> hibi_pe_dma_0:avalon_cfg_re_in
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        wire   [31:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata;                                // hibi_pe_dma_0:avalon_cfg_readdata_out -> hibi_pe_dma_0_avalon_slave_0_translator:av_readdata
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        wire          hibi_pe_dma_0_avalon_master_waitrequest;                                                             // hibi_pe_dma_0_avalon_master_translator:av_waitrequest -> hibi_pe_dma_0:avalon_waitrequest_in_rx
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        wire   [31:0] hibi_pe_dma_0_avalon_master_writedata;                                                               // hibi_pe_dma_0:avalon_writedata_out_rx -> hibi_pe_dma_0_avalon_master_translator:av_writedata
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        wire   [31:0] hibi_pe_dma_0_avalon_master_address;                                                                 // hibi_pe_dma_0:avalon_addr_out_rx -> hibi_pe_dma_0_avalon_master_translator:av_address
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        wire          hibi_pe_dma_0_avalon_master_write;                                                                   // hibi_pe_dma_0:avalon_we_out_rx -> hibi_pe_dma_0_avalon_master_translator:av_write
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        wire    [3:0] hibi_pe_dma_0_avalon_master_byteenable;                                                              // hibi_pe_dma_0:avalon_be_out_rx -> hibi_pe_dma_0_avalon_master_translator:av_byteenable
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        wire          hibi_pe_dma_0_avalon_master_1_waitrequest;                                                           // hibi_pe_dma_0_avalon_master_1_translator:av_waitrequest -> hibi_pe_dma_0:avalon_waitrequest_in_tx
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        wire   [31:0] hibi_pe_dma_0_avalon_master_1_address;                                                               // hibi_pe_dma_0:avalon_addr_out_tx -> hibi_pe_dma_0_avalon_master_1_translator:av_address
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        wire          hibi_pe_dma_0_avalon_master_1_read;                                                                  // hibi_pe_dma_0:avalon_re_out_tx -> hibi_pe_dma_0_avalon_master_1_translator:av_read
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        wire   [31:0] hibi_pe_dma_0_avalon_master_1_readdata;                                                              // hibi_pe_dma_0_avalon_master_1_translator:av_readdata -> hibi_pe_dma_0:avalon_readdata_in_tx
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        wire          hibi_pe_dma_0_avalon_master_1_readdatavalid;                                                         // hibi_pe_dma_0_avalon_master_1_translator:av_readdatavalid -> hibi_pe_dma_0:avalon_readdatavalid_in_tx
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        wire   [31:0] onchip_memory2_1_s2_translator_avalon_anti_slave_0_writedata;                                        // onchip_memory2_1_s2_translator:av_writedata -> onchip_memory2_1:writedata2
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        wire   [10:0] onchip_memory2_1_s2_translator_avalon_anti_slave_0_address;                                          // onchip_memory2_1_s2_translator:av_address -> onchip_memory2_1:address2
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        wire          onchip_memory2_1_s2_translator_avalon_anti_slave_0_chipselect;                                       // onchip_memory2_1_s2_translator:av_chipselect -> onchip_memory2_1:chipselect2
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        wire          onchip_memory2_1_s2_translator_avalon_anti_slave_0_clken;                                            // onchip_memory2_1_s2_translator:av_clken -> onchip_memory2_1:clken2
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        wire          onchip_memory2_1_s2_translator_avalon_anti_slave_0_write;                                            // onchip_memory2_1_s2_translator:av_write -> onchip_memory2_1:write2
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        wire   [31:0] onchip_memory2_1_s2_translator_avalon_anti_slave_0_readdata;                                         // onchip_memory2_1:readdata2 -> onchip_memory2_1_s2_translator:av_readdata
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        wire    [3:0] onchip_memory2_1_s2_translator_avalon_anti_slave_0_byteenable;                                       // onchip_memory2_1_s2_translator:av_byteenable -> onchip_memory2_1:byteenable2
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        wire          nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_waitrequest;                    // nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:av_waitrequest -> nios2_qsys_1_instruction_master_translator:uav_waitrequest
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        wire    [2:0] nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_burstcount;                     // nios2_qsys_1_instruction_master_translator:uav_burstcount -> nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:av_burstcount
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        wire   [31:0] nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_writedata;                      // nios2_qsys_1_instruction_master_translator:uav_writedata -> nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:av_writedata
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        wire   [25:0] nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_address;                        // nios2_qsys_1_instruction_master_translator:uav_address -> nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:av_address
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        wire          nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_lock;                           // nios2_qsys_1_instruction_master_translator:uav_lock -> nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:av_lock
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        wire          nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_write;                          // nios2_qsys_1_instruction_master_translator:uav_write -> nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:av_write
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        wire          nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_read;                           // nios2_qsys_1_instruction_master_translator:uav_read -> nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:av_read
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        wire   [31:0] nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_readdata;                       // nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:av_readdata -> nios2_qsys_1_instruction_master_translator:uav_readdata
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        wire          nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_debugaccess;                    // nios2_qsys_1_instruction_master_translator:uav_debugaccess -> nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:av_debugaccess
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        wire    [3:0] nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_byteenable;                     // nios2_qsys_1_instruction_master_translator:uav_byteenable -> nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:av_byteenable
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        wire          nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_readdatavalid;                  // nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> nios2_qsys_1_instruction_master_translator:uav_readdatavalid
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        wire          nios2_qsys_1_data_master_translator_avalon_universal_master_0_waitrequest;                           // nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:av_waitrequest -> nios2_qsys_1_data_master_translator:uav_waitrequest
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        wire    [2:0] nios2_qsys_1_data_master_translator_avalon_universal_master_0_burstcount;                            // nios2_qsys_1_data_master_translator:uav_burstcount -> nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:av_burstcount
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        wire   [31:0] nios2_qsys_1_data_master_translator_avalon_universal_master_0_writedata;                             // nios2_qsys_1_data_master_translator:uav_writedata -> nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:av_writedata
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        wire   [25:0] nios2_qsys_1_data_master_translator_avalon_universal_master_0_address;                               // nios2_qsys_1_data_master_translator:uav_address -> nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:av_address
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        wire          nios2_qsys_1_data_master_translator_avalon_universal_master_0_lock;                                  // nios2_qsys_1_data_master_translator:uav_lock -> nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:av_lock
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        wire          nios2_qsys_1_data_master_translator_avalon_universal_master_0_write;                                 // nios2_qsys_1_data_master_translator:uav_write -> nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:av_write
128 
        wire          nios2_qsys_1_data_master_translator_avalon_universal_master_0_read;                                  // nios2_qsys_1_data_master_translator:uav_read -> nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:av_read
129 
        wire   [31:0] nios2_qsys_1_data_master_translator_avalon_universal_master_0_readdata;                              // nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:av_readdata -> nios2_qsys_1_data_master_translator:uav_readdata
130 
        wire          nios2_qsys_1_data_master_translator_avalon_universal_master_0_debugaccess;                           // nios2_qsys_1_data_master_translator:uav_debugaccess -> nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:av_debugaccess
131 
        wire    [3:0] nios2_qsys_1_data_master_translator_avalon_universal_master_0_byteenable;                            // nios2_qsys_1_data_master_translator:uav_byteenable -> nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:av_byteenable
132 
        wire          nios2_qsys_1_data_master_translator_avalon_universal_master_0_readdatavalid;                         // nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> nios2_qsys_1_data_master_translator:uav_readdatavalid
133 
        wire          nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest;             // nios2_qsys_1_jtag_debug_module_translator:uav_waitrequest -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_waitrequest
134 
        wire    [2:0] nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount;              // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_burstcount -> nios2_qsys_1_jtag_debug_module_translator:uav_burstcount
135 
        wire   [31:0] nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata;               // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_writedata -> nios2_qsys_1_jtag_debug_module_translator:uav_writedata
136 
        wire   [25:0] nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address;                 // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_address -> nios2_qsys_1_jtag_debug_module_translator:uav_address
137 
        wire          nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write;                   // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_write -> nios2_qsys_1_jtag_debug_module_translator:uav_write
138 
        wire          nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock;                    // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_lock -> nios2_qsys_1_jtag_debug_module_translator:uav_lock
139 
        wire          nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read;                    // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_read -> nios2_qsys_1_jtag_debug_module_translator:uav_read
140 
        wire   [31:0] nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata;                // nios2_qsys_1_jtag_debug_module_translator:uav_readdata -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdata
141 
        wire          nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid;           // nios2_qsys_1_jtag_debug_module_translator:uav_readdatavalid -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdatavalid
142 
        wire          nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess;             // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_debugaccess -> nios2_qsys_1_jtag_debug_module_translator:uav_debugaccess
143 
        wire    [3:0] nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable;              // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_byteenable -> nios2_qsys_1_jtag_debug_module_translator:uav_byteenable
144 
        wire          nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;      // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
145 
        wire          nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid;            // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_valid -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
146 
        wire          nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;    // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
147 
        wire   [99:0] nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data;             // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_data -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
148 
        wire          nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready;            // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_ready
149 
        wire          nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;   // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
150 
        wire          nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;         // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_valid
151 
        wire          nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
152 
        wire   [99:0] nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;          // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_data
153 
        wire          nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;         // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_ready -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
154 
        wire          nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;       // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
155 
        wire   [31:0] nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;        // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
156 
        wire          nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;       // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
157 
        wire          sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest;                                 // sdram_0_s1_translator:uav_waitrequest -> sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
158 
        wire    [1:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount;                                  // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> sdram_0_s1_translator:uav_burstcount
159 
        wire   [15:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata;                                   // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> sdram_0_s1_translator:uav_writedata
160 
        wire   [25:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_address;                                     // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_address -> sdram_0_s1_translator:uav_address
161 
        wire          sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_write;                                       // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_write -> sdram_0_s1_translator:uav_write
162 
        wire          sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_lock;                                        // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> sdram_0_s1_translator:uav_lock
163 
        wire          sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_read;                                        // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_read -> sdram_0_s1_translator:uav_read
164 
        wire   [15:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata;                                    // sdram_0_s1_translator:uav_readdata -> sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_readdata
165 
        wire          sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid;                               // sdram_0_s1_translator:uav_readdatavalid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
166 
        wire          sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess;                                 // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sdram_0_s1_translator:uav_debugaccess
167 
        wire    [1:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable;                                  // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> sdram_0_s1_translator:uav_byteenable
168 
        wire          sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;                          // sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
169 
        wire          sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid;                                // sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
170 
        wire          sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;                        // sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
171 
        wire   [81:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data;                                 // sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
172 
        wire          sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready;                                // sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
173 
        wire          sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;                       // sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
174 
        wire          sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;                             // sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
175 
        wire          sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;                     // sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
176 
        wire   [81:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;                              // sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
177 
        wire          sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;                             // sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
178 
        wire          sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;                           // sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
179 
        wire   [15:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;                            // sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
180 
        wire          sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;                           // sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
181 
        wire          jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest;              // jtag_uart_1_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
182 
        wire    [2:0] jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount;               // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> jtag_uart_1_avalon_jtag_slave_translator:uav_burstcount
183 
        wire   [31:0] jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata;                // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> jtag_uart_1_avalon_jtag_slave_translator:uav_writedata
184 
        wire   [25:0] jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address;                  // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_address -> jtag_uart_1_avalon_jtag_slave_translator:uav_address
185 
        wire          jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write;                    // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_write -> jtag_uart_1_avalon_jtag_slave_translator:uav_write
186 
        wire          jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock;                     // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_lock -> jtag_uart_1_avalon_jtag_slave_translator:uav_lock
187 
        wire          jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read;                     // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_read -> jtag_uart_1_avalon_jtag_slave_translator:uav_read
188 
        wire   [31:0] jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata;                 // jtag_uart_1_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdata
189 
        wire          jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid;            // jtag_uart_1_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
190 
        wire          jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess;              // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> jtag_uart_1_avalon_jtag_slave_translator:uav_debugaccess
191 
        wire    [3:0] jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable;               // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> jtag_uart_1_avalon_jtag_slave_translator:uav_byteenable
192 
        wire          jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;       // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
193 
        wire          jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid;             // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
194 
        wire          jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;     // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
195 
        wire   [99:0] jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data;              // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
196 
        wire          jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready;             // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
197 
        wire          jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;    // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
198 
        wire          jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;          // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
199 
        wire          jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;  // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
200 
        wire   [99:0] jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;           // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
201 
        wire          jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;          // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
202 
        wire          jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;        // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
203 
        wire   [31:0] jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;         // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
204 
        wire          jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;        // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
205 
        wire          timer_1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest;                                 // timer_1_s1_translator:uav_waitrequest -> timer_1_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
206 
        wire    [2:0] timer_1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount;                                  // timer_1_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> timer_1_s1_translator:uav_burstcount
207 
        wire   [31:0] timer_1_s1_translator_avalon_universal_slave_0_agent_m0_writedata;                                   // timer_1_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> timer_1_s1_translator:uav_writedata
208 
        wire   [25:0] timer_1_s1_translator_avalon_universal_slave_0_agent_m0_address;                                     // timer_1_s1_translator_avalon_universal_slave_0_agent:m0_address -> timer_1_s1_translator:uav_address
209 
        wire          timer_1_s1_translator_avalon_universal_slave_0_agent_m0_write;                                       // timer_1_s1_translator_avalon_universal_slave_0_agent:m0_write -> timer_1_s1_translator:uav_write
210 
        wire          timer_1_s1_translator_avalon_universal_slave_0_agent_m0_lock;                                        // timer_1_s1_translator_avalon_universal_slave_0_agent:m0_lock -> timer_1_s1_translator:uav_lock
211 
        wire          timer_1_s1_translator_avalon_universal_slave_0_agent_m0_read;                                        // timer_1_s1_translator_avalon_universal_slave_0_agent:m0_read -> timer_1_s1_translator:uav_read
212 
        wire   [31:0] timer_1_s1_translator_avalon_universal_slave_0_agent_m0_readdata;                                    // timer_1_s1_translator:uav_readdata -> timer_1_s1_translator_avalon_universal_slave_0_agent:m0_readdata
213 
        wire          timer_1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid;                               // timer_1_s1_translator:uav_readdatavalid -> timer_1_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
214 
        wire          timer_1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess;                                 // timer_1_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> timer_1_s1_translator:uav_debugaccess
215 
        wire    [3:0] timer_1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable;                                  // timer_1_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> timer_1_s1_translator:uav_byteenable
216 
        wire          timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;                          // timer_1_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
217 
        wire          timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid;                                // timer_1_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
218 
        wire          timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;                        // timer_1_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
219 
        wire   [99:0] timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_data;                                 // timer_1_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
220 
        wire          timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready;                                // timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> timer_1_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
221 
        wire          timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;                       // timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> timer_1_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
222 
        wire          timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;                             // timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> timer_1_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
223 
        wire          timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;                     // timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> timer_1_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
224 
        wire   [99:0] timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;                              // timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> timer_1_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
225 
        wire          timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;                             // timer_1_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
226 
        wire          timer_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;                           // timer_1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> timer_1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
227 
        wire   [31:0] timer_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;                            // timer_1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> timer_1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
228 
        wire          timer_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;                           // timer_1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> timer_1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
229 
        wire          timer_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest;                                 // timer_0_s1_translator:uav_waitrequest -> timer_0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
230 
        wire    [2:0] timer_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount;                                  // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> timer_0_s1_translator:uav_burstcount
231 
        wire   [31:0] timer_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata;                                   // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> timer_0_s1_translator:uav_writedata
232 
        wire   [25:0] timer_0_s1_translator_avalon_universal_slave_0_agent_m0_address;                                     // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_address -> timer_0_s1_translator:uav_address
233 
        wire          timer_0_s1_translator_avalon_universal_slave_0_agent_m0_write;                                       // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_write -> timer_0_s1_translator:uav_write
234 
        wire          timer_0_s1_translator_avalon_universal_slave_0_agent_m0_lock;                                        // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> timer_0_s1_translator:uav_lock
235 
        wire          timer_0_s1_translator_avalon_universal_slave_0_agent_m0_read;                                        // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_read -> timer_0_s1_translator:uav_read
236 
        wire   [31:0] timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata;                                    // timer_0_s1_translator:uav_readdata -> timer_0_s1_translator_avalon_universal_slave_0_agent:m0_readdata
237 
        wire          timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid;                               // timer_0_s1_translator:uav_readdatavalid -> timer_0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
238 
        wire          timer_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess;                                 // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> timer_0_s1_translator:uav_debugaccess
239 
        wire    [3:0] timer_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable;                                  // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> timer_0_s1_translator:uav_byteenable
240 
        wire          timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;                          // timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
241 
        wire          timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid;                                // timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
242 
        wire          timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;                        // timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
243 
        wire   [99:0] timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data;                                 // timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
244 
        wire          timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready;                                // timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
245 
        wire          timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;                       // timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
246 
        wire          timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;                             // timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
247 
        wire          timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;                     // timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
248 
        wire   [99:0] timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;                              // timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
249 
        wire          timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;                             // timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
250 
        wire          timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;                           // timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
251 
        wire   [31:0] timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;                            // timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
252 
        wire          timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;                           // timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
253 
        wire          sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest;                 // sysid_qsys_1_control_slave_translator:uav_waitrequest -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
254 
        wire    [2:0] sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount;                  // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> sysid_qsys_1_control_slave_translator:uav_burstcount
255 
        wire   [31:0] sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata;                   // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> sysid_qsys_1_control_slave_translator:uav_writedata
256 
        wire   [25:0] sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_address;                     // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:m0_address -> sysid_qsys_1_control_slave_translator:uav_address
257 
        wire          sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_write;                       // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:m0_write -> sysid_qsys_1_control_slave_translator:uav_write
258 
        wire          sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_lock;                        // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:m0_lock -> sysid_qsys_1_control_slave_translator:uav_lock
259 
        wire          sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_read;                        // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:m0_read -> sysid_qsys_1_control_slave_translator:uav_read
260 
        wire   [31:0] sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata;                    // sysid_qsys_1_control_slave_translator:uav_readdata -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:m0_readdata
261 
        wire          sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid;               // sysid_qsys_1_control_slave_translator:uav_readdatavalid -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
262 
        wire          sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess;                 // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sysid_qsys_1_control_slave_translator:uav_debugaccess
263 
        wire    [3:0] sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable;                  // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> sysid_qsys_1_control_slave_translator:uav_byteenable
264 
        wire          sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;          // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
265 
        wire          sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid;                // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
266 
        wire          sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;        // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
267 
        wire   [99:0] sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data;                 // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
268 
        wire          sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready;                // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
269 
        wire          sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;       // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
270 
        wire          sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;             // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
271 
        wire          sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;     // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
272 
        wire   [99:0] sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;              // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
273 
        wire          sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;             // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
274 
        wire          sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;           // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
275 
        wire   [31:0] sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;            // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
276 
        wire          sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;           // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
277 
        wire          onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest;                        // onchip_memory2_1_s1_translator:uav_waitrequest -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
278 
        wire    [2:0] onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount;                         // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> onchip_memory2_1_s1_translator:uav_burstcount
279 
        wire   [31:0] onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_writedata;                          // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> onchip_memory2_1_s1_translator:uav_writedata
280 
        wire   [25:0] onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_address;                            // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:m0_address -> onchip_memory2_1_s1_translator:uav_address
281 
        wire          onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_write;                              // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:m0_write -> onchip_memory2_1_s1_translator:uav_write
282 
        wire          onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_lock;                               // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:m0_lock -> onchip_memory2_1_s1_translator:uav_lock
283 
        wire          onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_read;                               // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:m0_read -> onchip_memory2_1_s1_translator:uav_read
284 
        wire   [31:0] onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_readdata;                           // onchip_memory2_1_s1_translator:uav_readdata -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:m0_readdata
285 
        wire          onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid;                      // onchip_memory2_1_s1_translator:uav_readdatavalid -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
286 
        wire          onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess;                        // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> onchip_memory2_1_s1_translator:uav_debugaccess
287 
        wire    [3:0] onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable;                         // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> onchip_memory2_1_s1_translator:uav_byteenable
288 
        wire          onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;                 // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
289 
        wire          onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid;                       // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
290 
        wire          onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;               // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
291 
        wire   [99:0] onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_data;                        // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
292 
        wire          onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready;                       // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
293 
        wire          onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;              // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
294 
        wire          onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;                    // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
295 
        wire          onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;            // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
296 
        wire   [99:0] onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;                     // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
297 
        wire          onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;                    // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
298 
        wire          onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;                  // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
299 
        wire   [31:0] onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;                   // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
300 
        wire          onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;                  // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
301 
        wire          hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest;               // hibi_pe_dma_0_avalon_slave_0_translator:uav_waitrequest -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_waitrequest
302 
        wire    [2:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount;                // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_burstcount -> hibi_pe_dma_0_avalon_slave_0_translator:uav_burstcount
303 
        wire   [31:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata;                 // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_writedata -> hibi_pe_dma_0_avalon_slave_0_translator:uav_writedata
304 
        wire   [25:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address;                   // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_address -> hibi_pe_dma_0_avalon_slave_0_translator:uav_address
305 
        wire          hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write;                     // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_write -> hibi_pe_dma_0_avalon_slave_0_translator:uav_write
306 
        wire          hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock;                      // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_lock -> hibi_pe_dma_0_avalon_slave_0_translator:uav_lock
307 
        wire          hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read;                      // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_read -> hibi_pe_dma_0_avalon_slave_0_translator:uav_read
308 
        wire   [31:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata;                  // hibi_pe_dma_0_avalon_slave_0_translator:uav_readdata -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdata
309 
        wire          hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid;             // hibi_pe_dma_0_avalon_slave_0_translator:uav_readdatavalid -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdatavalid
310 
        wire          hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess;               // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hibi_pe_dma_0_avalon_slave_0_translator:uav_debugaccess
311 
        wire    [3:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable;                // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_byteenable -> hibi_pe_dma_0_avalon_slave_0_translator:uav_byteenable
312 
        wire          hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;        // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
313 
        wire          hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid;              // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_valid -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
314 
        wire          hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;      // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
315 
        wire   [99:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data;               // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_data -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
316 
        wire          hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready;              // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_ready
317 
        wire          hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;     // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
318 
        wire          hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;           // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_valid
319 
        wire          hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;   // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
320 
        wire   [99:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;            // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_data
321 
        wire          hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;           // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
322 
        wire          hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;         // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
323 
        wire   [31:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;          // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
324 
        wire          hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;         // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
325 
        wire          hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_waitrequest;                        // hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:av_waitrequest -> hibi_pe_dma_0_avalon_master_translator:uav_waitrequest
326 
        wire    [2:0] hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_burstcount;                         // hibi_pe_dma_0_avalon_master_translator:uav_burstcount -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:av_burstcount
327 
        wire   [31:0] hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_writedata;                          // hibi_pe_dma_0_avalon_master_translator:uav_writedata -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:av_writedata
328 
        wire   [31:0] hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_address;                            // hibi_pe_dma_0_avalon_master_translator:uav_address -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:av_address
329 
        wire          hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_lock;                               // hibi_pe_dma_0_avalon_master_translator:uav_lock -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:av_lock
330 
        wire          hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_write;                              // hibi_pe_dma_0_avalon_master_translator:uav_write -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:av_write
331 
        wire          hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_read;                               // hibi_pe_dma_0_avalon_master_translator:uav_read -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:av_read
332 
        wire   [31:0] hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_readdata;                           // hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:av_readdata -> hibi_pe_dma_0_avalon_master_translator:uav_readdata
333 
        wire          hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_debugaccess;                        // hibi_pe_dma_0_avalon_master_translator:uav_debugaccess -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:av_debugaccess
334 
        wire    [3:0] hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_byteenable;                         // hibi_pe_dma_0_avalon_master_translator:uav_byteenable -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:av_byteenable
335 
        wire          hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_readdatavalid;                      // hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> hibi_pe_dma_0_avalon_master_translator:uav_readdatavalid
336 
        wire          hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_waitrequest;                      // hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:av_waitrequest -> hibi_pe_dma_0_avalon_master_1_translator:uav_waitrequest
337 
        wire    [2:0] hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_burstcount;                       // hibi_pe_dma_0_avalon_master_1_translator:uav_burstcount -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:av_burstcount
338 
        wire   [31:0] hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_writedata;                        // hibi_pe_dma_0_avalon_master_1_translator:uav_writedata -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:av_writedata
339 
        wire   [31:0] hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_address;                          // hibi_pe_dma_0_avalon_master_1_translator:uav_address -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:av_address
340 
        wire          hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_lock;                             // hibi_pe_dma_0_avalon_master_1_translator:uav_lock -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:av_lock
341 
        wire          hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_write;                            // hibi_pe_dma_0_avalon_master_1_translator:uav_write -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:av_write
342 
        wire          hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_read;                             // hibi_pe_dma_0_avalon_master_1_translator:uav_read -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:av_read
343 
        wire   [31:0] hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_readdata;                         // hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:av_readdata -> hibi_pe_dma_0_avalon_master_1_translator:uav_readdata
344 
        wire          hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_debugaccess;                      // hibi_pe_dma_0_avalon_master_1_translator:uav_debugaccess -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:av_debugaccess
345 
        wire    [3:0] hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_byteenable;                       // hibi_pe_dma_0_avalon_master_1_translator:uav_byteenable -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:av_byteenable
346 
        wire          hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_readdatavalid;                    // hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:av_readdatavalid -> hibi_pe_dma_0_avalon_master_1_translator:uav_readdatavalid
347 
        wire          onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_waitrequest;                        // onchip_memory2_1_s2_translator:uav_waitrequest -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:m0_waitrequest
348 
        wire    [2:0] onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_burstcount;                         // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:m0_burstcount -> onchip_memory2_1_s2_translator:uav_burstcount
349 
        wire   [31:0] onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_writedata;                          // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:m0_writedata -> onchip_memory2_1_s2_translator:uav_writedata
350 
        wire   [31:0] onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_address;                            // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:m0_address -> onchip_memory2_1_s2_translator:uav_address
351 
        wire          onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_write;                              // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:m0_write -> onchip_memory2_1_s2_translator:uav_write
352 
        wire          onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_lock;                               // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:m0_lock -> onchip_memory2_1_s2_translator:uav_lock
353 
        wire          onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_read;                               // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:m0_read -> onchip_memory2_1_s2_translator:uav_read
354 
        wire   [31:0] onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_readdata;                           // onchip_memory2_1_s2_translator:uav_readdata -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:m0_readdata
355 
        wire          onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_readdatavalid;                      // onchip_memory2_1_s2_translator:uav_readdatavalid -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:m0_readdatavalid
356 
        wire          onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_debugaccess;                        // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:m0_debugaccess -> onchip_memory2_1_s2_translator:uav_debugaccess
357 
        wire    [3:0] onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_byteenable;                         // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:m0_byteenable -> onchip_memory2_1_s2_translator:uav_byteenable
358 
        wire          onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;                 // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
359 
        wire          onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_valid;                       // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rf_source_valid -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
360 
        wire          onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;               // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
361 
        wire  [101:0] onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_data;                        // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rf_source_data -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
362 
        wire          onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_ready;                       // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rf_source_ready
363 
        wire          onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;              // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
364 
        wire          onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;                    // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rf_sink_valid
365 
        wire          onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;            // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
366 
        wire  [101:0] onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;                     // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rf_sink_data
367 
        wire          onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;                    // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rf_sink_ready -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
368 
        wire          onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;                  // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
369 
        wire   [31:0] onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;                   // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
370 
        wire          onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;                  // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
371 
        wire          nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket;           // nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket
372 
        wire          nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_valid;                 // nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid
373 
        wire          nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket;         // nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket
374 
        wire   [98:0] nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_data;                  // nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data
375 
        wire          nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_ready;                 // addr_router:sink_ready -> nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:cp_ready
376 
        wire          nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket;                  // nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_001:sink_endofpacket
377 
        wire          nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_valid;                        // nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_001:sink_valid
378 
        wire          nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket;                // nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_001:sink_startofpacket
379 
        wire   [98:0] nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_data;                         // nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_001:sink_data
380 
        wire          nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_ready;                        // addr_router_001:sink_ready -> nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:cp_ready
381 
        wire          nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket;             // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket
382 
        wire          nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid;                   // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid
383 
        wire          nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket;           // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket
384 
        wire   [98:0] nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data;                    // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data
385 
        wire          nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready;                   // id_router:sink_ready -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_ready
386 
        wire          sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket;                                 // sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket
387 
        wire          sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_valid;                                       // sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid
388 
        wire          sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket;                               // sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket
389 
        wire   [80:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_data;                                        // sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data
390 
        wire          sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_ready;                                       // id_router_001:sink_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_ready
391 
        wire          jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket;              // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_002:sink_endofpacket
392 
        wire          jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid;                    // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_002:sink_valid
393 
        wire          jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket;            // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_002:sink_startofpacket
394 
        wire   [98:0] jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data;                     // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_002:sink_data
395 
        wire          jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready;                    // id_router_002:sink_ready -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_ready
396 
        wire          timer_1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket;                                 // timer_1_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_003:sink_endofpacket
397 
        wire          timer_1_s1_translator_avalon_universal_slave_0_agent_rp_valid;                                       // timer_1_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_003:sink_valid
398 
        wire          timer_1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket;                               // timer_1_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_003:sink_startofpacket
399 
        wire   [98:0] timer_1_s1_translator_avalon_universal_slave_0_agent_rp_data;                                        // timer_1_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_003:sink_data
400 
        wire          timer_1_s1_translator_avalon_universal_slave_0_agent_rp_ready;                                       // id_router_003:sink_ready -> timer_1_s1_translator_avalon_universal_slave_0_agent:rp_ready
401 
        wire          timer_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket;                                 // timer_0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_004:sink_endofpacket
402 
        wire          timer_0_s1_translator_avalon_universal_slave_0_agent_rp_valid;                                       // timer_0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_004:sink_valid
403 
        wire          timer_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket;                               // timer_0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_004:sink_startofpacket
404 
        wire   [98:0] timer_0_s1_translator_avalon_universal_slave_0_agent_rp_data;                                        // timer_0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_004:sink_data
405 
        wire          timer_0_s1_translator_avalon_universal_slave_0_agent_rp_ready;                                       // id_router_004:sink_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent:rp_ready
406 
        wire          sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket;                 // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_005:sink_endofpacket
407 
        wire          sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_valid;                       // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_005:sink_valid
408 
        wire          sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket;               // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_005:sink_startofpacket
409 
        wire   [98:0] sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_data;                        // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_005:sink_data
410 
        wire          sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_ready;                       // id_router_005:sink_ready -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rp_ready
411 
        wire          onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket;                        // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_006:sink_endofpacket
412 
        wire          onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_valid;                              // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_006:sink_valid
413 
        wire          onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket;                      // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_006:sink_startofpacket
414 
        wire   [98:0] onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_data;                               // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_006:sink_data
415 
        wire          onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_ready;                              // id_router_006:sink_ready -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rp_ready
416 
        wire          hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket;               // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_007:sink_endofpacket
417 
        wire          hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid;                     // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_007:sink_valid
418 
        wire          hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket;             // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_007:sink_startofpacket
419 
        wire   [98:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data;                      // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_data -> id_router_007:sink_data
420 
        wire          hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready;                     // id_router_007:sink_ready -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_ready
421 
        wire          hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_endofpacket;               // hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_002:sink_endofpacket
422 
        wire          hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_valid;                     // hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_002:sink_valid
423 
        wire          hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_startofpacket;             // hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_002:sink_startofpacket
424 
        wire  [100:0] hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_data;                      // hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_002:sink_data
425 
        wire          hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_ready;                     // addr_router_002:sink_ready -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:cp_ready
426 
        wire          hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_endofpacket;             // hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_003:sink_endofpacket
427 
        wire          hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_valid;                   // hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_003:sink_valid
428 
        wire          hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_startofpacket;           // hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_003:sink_startofpacket
429 
        wire  [100:0] hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_data;                    // hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:cp_data -> addr_router_003:sink_data
430 
        wire          hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_ready;                   // addr_router_003:sink_ready -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:cp_ready
431 
        wire          onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_endofpacket;                        // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_008:sink_endofpacket
432 
        wire          onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_valid;                              // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_008:sink_valid
433 
        wire          onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_startofpacket;                      // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_008:sink_startofpacket
434 
        wire  [100:0] onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_data;                               // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rp_data -> id_router_008:sink_data
435 
        wire          onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_ready;                              // id_router_008:sink_ready -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rp_ready
436 
        wire          addr_router_src_endofpacket;                                                                         // addr_router:src_endofpacket -> limiter:cmd_sink_endofpacket
437 
        wire          addr_router_src_valid;                                                                               // addr_router:src_valid -> limiter:cmd_sink_valid
438 
        wire          addr_router_src_startofpacket;                                                                       // addr_router:src_startofpacket -> limiter:cmd_sink_startofpacket
439 
        wire   [98:0] addr_router_src_data;                                                                                // addr_router:src_data -> limiter:cmd_sink_data
440 
        wire    [7:0] addr_router_src_channel;                                                                             // addr_router:src_channel -> limiter:cmd_sink_channel
441 
        wire          addr_router_src_ready;                                                                               // limiter:cmd_sink_ready -> addr_router:src_ready
442 
        wire          limiter_rsp_src_endofpacket;                                                                         // limiter:rsp_src_endofpacket -> nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:rp_endofpacket
443 
        wire          limiter_rsp_src_valid;                                                                               // limiter:rsp_src_valid -> nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:rp_valid
444 
        wire          limiter_rsp_src_startofpacket;                                                                       // limiter:rsp_src_startofpacket -> nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:rp_startofpacket
445 
        wire   [98:0] limiter_rsp_src_data;                                                                                // limiter:rsp_src_data -> nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:rp_data
446 
        wire    [7:0] limiter_rsp_src_channel;                                                                             // limiter:rsp_src_channel -> nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:rp_channel
447 
        wire          limiter_rsp_src_ready;                                                                               // nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:rp_ready -> limiter:rsp_src_ready
448 
        wire          addr_router_001_src_endofpacket;                                                                     // addr_router_001:src_endofpacket -> limiter_001:cmd_sink_endofpacket
449 
        wire          addr_router_001_src_valid;                                                                           // addr_router_001:src_valid -> limiter_001:cmd_sink_valid
450 
        wire          addr_router_001_src_startofpacket;                                                                   // addr_router_001:src_startofpacket -> limiter_001:cmd_sink_startofpacket
451 
        wire   [98:0] addr_router_001_src_data;                                                                            // addr_router_001:src_data -> limiter_001:cmd_sink_data
452 
        wire    [7:0] addr_router_001_src_channel;                                                                         // addr_router_001:src_channel -> limiter_001:cmd_sink_channel
453 
        wire          addr_router_001_src_ready;                                                                           // limiter_001:cmd_sink_ready -> addr_router_001:src_ready
454 
        wire          limiter_001_rsp_src_endofpacket;                                                                     // limiter_001:rsp_src_endofpacket -> nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:rp_endofpacket
455 
        wire          limiter_001_rsp_src_valid;                                                                           // limiter_001:rsp_src_valid -> nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:rp_valid
456 
        wire          limiter_001_rsp_src_startofpacket;                                                                   // limiter_001:rsp_src_startofpacket -> nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:rp_startofpacket
457 
        wire   [98:0] limiter_001_rsp_src_data;                                                                            // limiter_001:rsp_src_data -> nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:rp_data
458 
        wire    [7:0] limiter_001_rsp_src_channel;                                                                         // limiter_001:rsp_src_channel -> nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:rp_channel
459 
        wire          limiter_001_rsp_src_ready;                                                                           // nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:rp_ready -> limiter_001:rsp_src_ready
460 
        wire          burst_adapter_source0_endofpacket;                                                                   // burst_adapter:source0_endofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
461 
        wire          burst_adapter_source0_valid;                                                                         // burst_adapter:source0_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_valid
462 
        wire          burst_adapter_source0_startofpacket;                                                                 // burst_adapter:source0_startofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
463 
        wire   [80:0] burst_adapter_source0_data;                                                                          // burst_adapter:source0_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_data
464 
        wire          burst_adapter_source0_ready;                                                                         // sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter:source0_ready
465 
        wire    [7:0] burst_adapter_source0_channel;                                                                       // burst_adapter:source0_channel -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_channel
466 
        wire          rst_controller_reset_out_reset;                                                                      // rst_controller:reset_out -> [addr_router:reset, addr_router_001:reset, addr_router_002:reset, addr_router_003:reset, burst_adapter:reset, cmd_xbar_demux:reset, cmd_xbar_demux_001:reset, cmd_xbar_demux_002:reset, cmd_xbar_demux_003:reset, cmd_xbar_mux:reset, cmd_xbar_mux_001:reset, cmd_xbar_mux_008:reset, hibi_pe_dma_0:rst_n, hibi_pe_dma_0_avalon_master_1_translator:reset, hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:reset, hibi_pe_dma_0_avalon_master_translator:reset, hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:reset, hibi_pe_dma_0_avalon_slave_0_translator:reset, hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:reset, hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, id_router:reset, id_router_001:reset, id_router_002:reset, id_router_003:reset, id_router_004:reset, id_router_005:reset, id_router_006:reset, id_router_007:reset, id_router_008:reset, irq_mapper:reset, jtag_uart_1:rst_n, jtag_uart_1_avalon_jtag_slave_translator:reset, jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:reset, jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, limiter:reset, limiter_001:reset, nios2_qsys_1:reset_n, nios2_qsys_1_data_master_translator:reset, nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:reset, nios2_qsys_1_instruction_master_translator:reset, nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:reset, nios2_qsys_1_jtag_debug_module_translator:reset, nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:reset, nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, onchip_memory2_1:reset, onchip_memory2_1:reset2, onchip_memory2_1_s1_translator:reset, onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:reset, onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, onchip_memory2_1_s2_translator:reset, onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:reset, onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rsp_xbar_demux:reset, rsp_xbar_demux_001:reset, rsp_xbar_demux_002:reset, rsp_xbar_demux_003:reset, rsp_xbar_demux_004:reset, rsp_xbar_demux_005:reset, rsp_xbar_demux_006:reset, rsp_xbar_demux_007:reset, rsp_xbar_demux_008:reset, rsp_xbar_mux:reset, rsp_xbar_mux_001:reset, sdram_0:reset_n, sdram_0_s1_translator:reset, sdram_0_s1_translator_avalon_universal_slave_0_agent:reset, sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sysid_qsys_1:reset_n, sysid_qsys_1_control_slave_translator:reset, sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:reset, sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, timer_0:reset_n, timer_0_s1_translator:reset, timer_0_s1_translator_avalon_universal_slave_0_agent:reset, timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, timer_1:reset_n, timer_1_s1_translator:reset, timer_1_s1_translator_avalon_universal_slave_0_agent:reset, timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, width_adapter:reset, width_adapter_001:reset]
467 
        wire          cmd_xbar_demux_src0_endofpacket;                                                                     // cmd_xbar_demux:src0_endofpacket -> cmd_xbar_mux:sink0_endofpacket
468 
        wire          cmd_xbar_demux_src0_valid;                                                                           // cmd_xbar_demux:src0_valid -> cmd_xbar_mux:sink0_valid
469 
        wire          cmd_xbar_demux_src0_startofpacket;                                                                   // cmd_xbar_demux:src0_startofpacket -> cmd_xbar_mux:sink0_startofpacket
470 
        wire   [98:0] cmd_xbar_demux_src0_data;                                                                            // cmd_xbar_demux:src0_data -> cmd_xbar_mux:sink0_data
471 
        wire    [7:0] cmd_xbar_demux_src0_channel;                                                                         // cmd_xbar_demux:src0_channel -> cmd_xbar_mux:sink0_channel
472 
        wire          cmd_xbar_demux_src0_ready;                                                                           // cmd_xbar_mux:sink0_ready -> cmd_xbar_demux:src0_ready
473 
        wire          cmd_xbar_demux_src1_endofpacket;                                                                     // cmd_xbar_demux:src1_endofpacket -> cmd_xbar_mux_001:sink0_endofpacket
474 
        wire          cmd_xbar_demux_src1_valid;                                                                           // cmd_xbar_demux:src1_valid -> cmd_xbar_mux_001:sink0_valid
475 
        wire          cmd_xbar_demux_src1_startofpacket;                                                                   // cmd_xbar_demux:src1_startofpacket -> cmd_xbar_mux_001:sink0_startofpacket
476 
        wire   [98:0] cmd_xbar_demux_src1_data;                                                                            // cmd_xbar_demux:src1_data -> cmd_xbar_mux_001:sink0_data
477 
        wire    [7:0] cmd_xbar_demux_src1_channel;                                                                         // cmd_xbar_demux:src1_channel -> cmd_xbar_mux_001:sink0_channel
478 
        wire          cmd_xbar_demux_src1_ready;                                                                           // cmd_xbar_mux_001:sink0_ready -> cmd_xbar_demux:src1_ready
479 
        wire          cmd_xbar_demux_001_src0_endofpacket;                                                                 // cmd_xbar_demux_001:src0_endofpacket -> cmd_xbar_mux:sink1_endofpacket
480 
        wire          cmd_xbar_demux_001_src0_valid;                                                                       // cmd_xbar_demux_001:src0_valid -> cmd_xbar_mux:sink1_valid
481 
        wire          cmd_xbar_demux_001_src0_startofpacket;                                                               // cmd_xbar_demux_001:src0_startofpacket -> cmd_xbar_mux:sink1_startofpacket
482 
        wire   [98:0] cmd_xbar_demux_001_src0_data;                                                                        // cmd_xbar_demux_001:src0_data -> cmd_xbar_mux:sink1_data
483 
        wire    [7:0] cmd_xbar_demux_001_src0_channel;                                                                     // cmd_xbar_demux_001:src0_channel -> cmd_xbar_mux:sink1_channel
484 
        wire          cmd_xbar_demux_001_src0_ready;                                                                       // cmd_xbar_mux:sink1_ready -> cmd_xbar_demux_001:src0_ready
485 
        wire          cmd_xbar_demux_001_src1_endofpacket;                                                                 // cmd_xbar_demux_001:src1_endofpacket -> cmd_xbar_mux_001:sink1_endofpacket
486 
        wire          cmd_xbar_demux_001_src1_valid;                                                                       // cmd_xbar_demux_001:src1_valid -> cmd_xbar_mux_001:sink1_valid
487 
        wire          cmd_xbar_demux_001_src1_startofpacket;                                                               // cmd_xbar_demux_001:src1_startofpacket -> cmd_xbar_mux_001:sink1_startofpacket
488 
        wire   [98:0] cmd_xbar_demux_001_src1_data;                                                                        // cmd_xbar_demux_001:src1_data -> cmd_xbar_mux_001:sink1_data
489 
        wire    [7:0] cmd_xbar_demux_001_src1_channel;                                                                     // cmd_xbar_demux_001:src1_channel -> cmd_xbar_mux_001:sink1_channel
490 
        wire          cmd_xbar_demux_001_src1_ready;                                                                       // cmd_xbar_mux_001:sink1_ready -> cmd_xbar_demux_001:src1_ready
491 
        wire          cmd_xbar_demux_001_src2_endofpacket;                                                                 // cmd_xbar_demux_001:src2_endofpacket -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
492 
        wire          cmd_xbar_demux_001_src2_valid;                                                                       // cmd_xbar_demux_001:src2_valid -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_valid
493 
        wire          cmd_xbar_demux_001_src2_startofpacket;                                                               // cmd_xbar_demux_001:src2_startofpacket -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
494 
        wire   [98:0] cmd_xbar_demux_001_src2_data;                                                                        // cmd_xbar_demux_001:src2_data -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_data
495 
        wire    [7:0] cmd_xbar_demux_001_src2_channel;                                                                     // cmd_xbar_demux_001:src2_channel -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_channel
496 
        wire          cmd_xbar_demux_001_src3_endofpacket;                                                                 // cmd_xbar_demux_001:src3_endofpacket -> timer_1_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
497 
        wire          cmd_xbar_demux_001_src3_valid;                                                                       // cmd_xbar_demux_001:src3_valid -> timer_1_s1_translator_avalon_universal_slave_0_agent:cp_valid
498 
        wire          cmd_xbar_demux_001_src3_startofpacket;                                                               // cmd_xbar_demux_001:src3_startofpacket -> timer_1_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
499 
        wire   [98:0] cmd_xbar_demux_001_src3_data;                                                                        // cmd_xbar_demux_001:src3_data -> timer_1_s1_translator_avalon_universal_slave_0_agent:cp_data
500 
        wire    [7:0] cmd_xbar_demux_001_src3_channel;                                                                     // cmd_xbar_demux_001:src3_channel -> timer_1_s1_translator_avalon_universal_slave_0_agent:cp_channel
501 
        wire          cmd_xbar_demux_001_src4_endofpacket;                                                                 // cmd_xbar_demux_001:src4_endofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
502 
        wire          cmd_xbar_demux_001_src4_valid;                                                                       // cmd_xbar_demux_001:src4_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_valid
503 
        wire          cmd_xbar_demux_001_src4_startofpacket;                                                               // cmd_xbar_demux_001:src4_startofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
504 
        wire   [98:0] cmd_xbar_demux_001_src4_data;                                                                        // cmd_xbar_demux_001:src4_data -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_data
505 
        wire    [7:0] cmd_xbar_demux_001_src4_channel;                                                                     // cmd_xbar_demux_001:src4_channel -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_channel
506 
        wire          cmd_xbar_demux_001_src5_endofpacket;                                                                 // cmd_xbar_demux_001:src5_endofpacket -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
507 
        wire          cmd_xbar_demux_001_src5_valid;                                                                       // cmd_xbar_demux_001:src5_valid -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:cp_valid
508 
        wire          cmd_xbar_demux_001_src5_startofpacket;                                                               // cmd_xbar_demux_001:src5_startofpacket -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
509 
        wire   [98:0] cmd_xbar_demux_001_src5_data;                                                                        // cmd_xbar_demux_001:src5_data -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:cp_data
510 
        wire    [7:0] cmd_xbar_demux_001_src5_channel;                                                                     // cmd_xbar_demux_001:src5_channel -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:cp_channel
511 
        wire          cmd_xbar_demux_001_src6_endofpacket;                                                                 // cmd_xbar_demux_001:src6_endofpacket -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
512 
        wire          cmd_xbar_demux_001_src6_valid;                                                                       // cmd_xbar_demux_001:src6_valid -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:cp_valid
513 
        wire          cmd_xbar_demux_001_src6_startofpacket;                                                               // cmd_xbar_demux_001:src6_startofpacket -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
514 
        wire   [98:0] cmd_xbar_demux_001_src6_data;                                                                        // cmd_xbar_demux_001:src6_data -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:cp_data
515 
        wire    [7:0] cmd_xbar_demux_001_src6_channel;                                                                     // cmd_xbar_demux_001:src6_channel -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:cp_channel
516 
        wire          cmd_xbar_demux_001_src7_endofpacket;                                                                 // cmd_xbar_demux_001:src7_endofpacket -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_endofpacket
517 
        wire          cmd_xbar_demux_001_src7_valid;                                                                       // cmd_xbar_demux_001:src7_valid -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_valid
518 
        wire          cmd_xbar_demux_001_src7_startofpacket;                                                               // cmd_xbar_demux_001:src7_startofpacket -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_startofpacket
519 
        wire   [98:0] cmd_xbar_demux_001_src7_data;                                                                        // cmd_xbar_demux_001:src7_data -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_data
520 
        wire    [7:0] cmd_xbar_demux_001_src7_channel;                                                                     // cmd_xbar_demux_001:src7_channel -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_channel
521 
        wire          rsp_xbar_demux_src0_endofpacket;                                                                     // rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket
522 
        wire          rsp_xbar_demux_src0_valid;                                                                           // rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid
523 
        wire          rsp_xbar_demux_src0_startofpacket;                                                                   // rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket
524 
        wire   [98:0] rsp_xbar_demux_src0_data;                                                                            // rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data
525 
        wire    [7:0] rsp_xbar_demux_src0_channel;                                                                         // rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel
526 
        wire          rsp_xbar_demux_src0_ready;                                                                           // rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready
527 
        wire          rsp_xbar_demux_src1_endofpacket;                                                                     // rsp_xbar_demux:src1_endofpacket -> rsp_xbar_mux_001:sink0_endofpacket
528 
        wire          rsp_xbar_demux_src1_valid;                                                                           // rsp_xbar_demux:src1_valid -> rsp_xbar_mux_001:sink0_valid
529 
        wire          rsp_xbar_demux_src1_startofpacket;                                                                   // rsp_xbar_demux:src1_startofpacket -> rsp_xbar_mux_001:sink0_startofpacket
530 
        wire   [98:0] rsp_xbar_demux_src1_data;                                                                            // rsp_xbar_demux:src1_data -> rsp_xbar_mux_001:sink0_data
531 
        wire    [7:0] rsp_xbar_demux_src1_channel;                                                                         // rsp_xbar_demux:src1_channel -> rsp_xbar_mux_001:sink0_channel
532 
        wire          rsp_xbar_demux_src1_ready;                                                                           // rsp_xbar_mux_001:sink0_ready -> rsp_xbar_demux:src1_ready
533 
        wire          rsp_xbar_demux_001_src0_endofpacket;                                                                 // rsp_xbar_demux_001:src0_endofpacket -> rsp_xbar_mux:sink1_endofpacket
534 
        wire          rsp_xbar_demux_001_src0_valid;                                                                       // rsp_xbar_demux_001:src0_valid -> rsp_xbar_mux:sink1_valid
535 
        wire          rsp_xbar_demux_001_src0_startofpacket;                                                               // rsp_xbar_demux_001:src0_startofpacket -> rsp_xbar_mux:sink1_startofpacket
536 
        wire   [98:0] rsp_xbar_demux_001_src0_data;                                                                        // rsp_xbar_demux_001:src0_data -> rsp_xbar_mux:sink1_data
537 
        wire    [7:0] rsp_xbar_demux_001_src0_channel;                                                                     // rsp_xbar_demux_001:src0_channel -> rsp_xbar_mux:sink1_channel
538 
        wire          rsp_xbar_demux_001_src0_ready;                                                                       // rsp_xbar_mux:sink1_ready -> rsp_xbar_demux_001:src0_ready
539 
        wire          rsp_xbar_demux_001_src1_endofpacket;                                                                 // rsp_xbar_demux_001:src1_endofpacket -> rsp_xbar_mux_001:sink1_endofpacket
540 
        wire          rsp_xbar_demux_001_src1_valid;                                                                       // rsp_xbar_demux_001:src1_valid -> rsp_xbar_mux_001:sink1_valid
541 
        wire          rsp_xbar_demux_001_src1_startofpacket;                                                               // rsp_xbar_demux_001:src1_startofpacket -> rsp_xbar_mux_001:sink1_startofpacket
542 
        wire   [98:0] rsp_xbar_demux_001_src1_data;                                                                        // rsp_xbar_demux_001:src1_data -> rsp_xbar_mux_001:sink1_data
543 
        wire    [7:0] rsp_xbar_demux_001_src1_channel;                                                                     // rsp_xbar_demux_001:src1_channel -> rsp_xbar_mux_001:sink1_channel
544 
        wire          rsp_xbar_demux_001_src1_ready;                                                                       // rsp_xbar_mux_001:sink1_ready -> rsp_xbar_demux_001:src1_ready
545 
        wire          rsp_xbar_demux_002_src0_endofpacket;                                                                 // rsp_xbar_demux_002:src0_endofpacket -> rsp_xbar_mux_001:sink2_endofpacket
546 
        wire          rsp_xbar_demux_002_src0_valid;                                                                       // rsp_xbar_demux_002:src0_valid -> rsp_xbar_mux_001:sink2_valid
547 
        wire          rsp_xbar_demux_002_src0_startofpacket;                                                               // rsp_xbar_demux_002:src0_startofpacket -> rsp_xbar_mux_001:sink2_startofpacket
548 
        wire   [98:0] rsp_xbar_demux_002_src0_data;                                                                        // rsp_xbar_demux_002:src0_data -> rsp_xbar_mux_001:sink2_data
549 
        wire    [7:0] rsp_xbar_demux_002_src0_channel;                                                                     // rsp_xbar_demux_002:src0_channel -> rsp_xbar_mux_001:sink2_channel
550 
        wire          rsp_xbar_demux_002_src0_ready;                                                                       // rsp_xbar_mux_001:sink2_ready -> rsp_xbar_demux_002:src0_ready
551 
        wire          rsp_xbar_demux_003_src0_endofpacket;                                                                 // rsp_xbar_demux_003:src0_endofpacket -> rsp_xbar_mux_001:sink3_endofpacket
552 
        wire          rsp_xbar_demux_003_src0_valid;                                                                       // rsp_xbar_demux_003:src0_valid -> rsp_xbar_mux_001:sink3_valid
553 
        wire          rsp_xbar_demux_003_src0_startofpacket;                                                               // rsp_xbar_demux_003:src0_startofpacket -> rsp_xbar_mux_001:sink3_startofpacket
554 
        wire   [98:0] rsp_xbar_demux_003_src0_data;                                                                        // rsp_xbar_demux_003:src0_data -> rsp_xbar_mux_001:sink3_data
555 
        wire    [7:0] rsp_xbar_demux_003_src0_channel;                                                                     // rsp_xbar_demux_003:src0_channel -> rsp_xbar_mux_001:sink3_channel
556 
        wire          rsp_xbar_demux_003_src0_ready;                                                                       // rsp_xbar_mux_001:sink3_ready -> rsp_xbar_demux_003:src0_ready
557 
        wire          rsp_xbar_demux_004_src0_endofpacket;                                                                 // rsp_xbar_demux_004:src0_endofpacket -> rsp_xbar_mux_001:sink4_endofpacket
558 
        wire          rsp_xbar_demux_004_src0_valid;                                                                       // rsp_xbar_demux_004:src0_valid -> rsp_xbar_mux_001:sink4_valid
559 
        wire          rsp_xbar_demux_004_src0_startofpacket;                                                               // rsp_xbar_demux_004:src0_startofpacket -> rsp_xbar_mux_001:sink4_startofpacket
560 
        wire   [98:0] rsp_xbar_demux_004_src0_data;                                                                        // rsp_xbar_demux_004:src0_data -> rsp_xbar_mux_001:sink4_data
561 
        wire    [7:0] rsp_xbar_demux_004_src0_channel;                                                                     // rsp_xbar_demux_004:src0_channel -> rsp_xbar_mux_001:sink4_channel
562 
        wire          rsp_xbar_demux_004_src0_ready;                                                                       // rsp_xbar_mux_001:sink4_ready -> rsp_xbar_demux_004:src0_ready
563 
        wire          rsp_xbar_demux_005_src0_endofpacket;                                                                 // rsp_xbar_demux_005:src0_endofpacket -> rsp_xbar_mux_001:sink5_endofpacket
564 
        wire          rsp_xbar_demux_005_src0_valid;                                                                       // rsp_xbar_demux_005:src0_valid -> rsp_xbar_mux_001:sink5_valid
565 
        wire          rsp_xbar_demux_005_src0_startofpacket;                                                               // rsp_xbar_demux_005:src0_startofpacket -> rsp_xbar_mux_001:sink5_startofpacket
566 
        wire   [98:0] rsp_xbar_demux_005_src0_data;                                                                        // rsp_xbar_demux_005:src0_data -> rsp_xbar_mux_001:sink5_data
567 
        wire    [7:0] rsp_xbar_demux_005_src0_channel;                                                                     // rsp_xbar_demux_005:src0_channel -> rsp_xbar_mux_001:sink5_channel
568 
        wire          rsp_xbar_demux_005_src0_ready;                                                                       // rsp_xbar_mux_001:sink5_ready -> rsp_xbar_demux_005:src0_ready
569 
        wire          rsp_xbar_demux_006_src0_endofpacket;                                                                 // rsp_xbar_demux_006:src0_endofpacket -> rsp_xbar_mux_001:sink6_endofpacket
570 
        wire          rsp_xbar_demux_006_src0_valid;                                                                       // rsp_xbar_demux_006:src0_valid -> rsp_xbar_mux_001:sink6_valid
571 
        wire          rsp_xbar_demux_006_src0_startofpacket;                                                               // rsp_xbar_demux_006:src0_startofpacket -> rsp_xbar_mux_001:sink6_startofpacket
572 
        wire   [98:0] rsp_xbar_demux_006_src0_data;                                                                        // rsp_xbar_demux_006:src0_data -> rsp_xbar_mux_001:sink6_data
573 
        wire    [7:0] rsp_xbar_demux_006_src0_channel;                                                                     // rsp_xbar_demux_006:src0_channel -> rsp_xbar_mux_001:sink6_channel
574 
        wire          rsp_xbar_demux_006_src0_ready;                                                                       // rsp_xbar_mux_001:sink6_ready -> rsp_xbar_demux_006:src0_ready
575 
        wire          rsp_xbar_demux_007_src0_endofpacket;                                                                 // rsp_xbar_demux_007:src0_endofpacket -> rsp_xbar_mux_001:sink7_endofpacket
576 
        wire          rsp_xbar_demux_007_src0_valid;                                                                       // rsp_xbar_demux_007:src0_valid -> rsp_xbar_mux_001:sink7_valid
577 
        wire          rsp_xbar_demux_007_src0_startofpacket;                                                               // rsp_xbar_demux_007:src0_startofpacket -> rsp_xbar_mux_001:sink7_startofpacket
578 
        wire   [98:0] rsp_xbar_demux_007_src0_data;                                                                        // rsp_xbar_demux_007:src0_data -> rsp_xbar_mux_001:sink7_data
579 
        wire    [7:0] rsp_xbar_demux_007_src0_channel;                                                                     // rsp_xbar_demux_007:src0_channel -> rsp_xbar_mux_001:sink7_channel
580 
        wire          rsp_xbar_demux_007_src0_ready;                                                                       // rsp_xbar_mux_001:sink7_ready -> rsp_xbar_demux_007:src0_ready
581 
        wire          limiter_cmd_src_endofpacket;                                                                         // limiter:cmd_src_endofpacket -> cmd_xbar_demux:sink_endofpacket
582 
        wire          limiter_cmd_src_startofpacket;                                                                       // limiter:cmd_src_startofpacket -> cmd_xbar_demux:sink_startofpacket
583 
        wire   [98:0] limiter_cmd_src_data;                                                                                // limiter:cmd_src_data -> cmd_xbar_demux:sink_data
584 
        wire    [7:0] limiter_cmd_src_channel;                                                                             // limiter:cmd_src_channel -> cmd_xbar_demux:sink_channel
585 
        wire          limiter_cmd_src_ready;                                                                               // cmd_xbar_demux:sink_ready -> limiter:cmd_src_ready
586 
        wire          rsp_xbar_mux_src_endofpacket;                                                                        // rsp_xbar_mux:src_endofpacket -> limiter:rsp_sink_endofpacket
587 
        wire          rsp_xbar_mux_src_valid;                                                                              // rsp_xbar_mux:src_valid -> limiter:rsp_sink_valid
588 
        wire          rsp_xbar_mux_src_startofpacket;                                                                      // rsp_xbar_mux:src_startofpacket -> limiter:rsp_sink_startofpacket
589 
        wire   [98:0] rsp_xbar_mux_src_data;                                                                               // rsp_xbar_mux:src_data -> limiter:rsp_sink_data
590 
        wire    [7:0] rsp_xbar_mux_src_channel;                                                                            // rsp_xbar_mux:src_channel -> limiter:rsp_sink_channel
591 
        wire          rsp_xbar_mux_src_ready;                                                                              // limiter:rsp_sink_ready -> rsp_xbar_mux:src_ready
592 
        wire          limiter_001_cmd_src_endofpacket;                                                                     // limiter_001:cmd_src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket
593 
        wire          limiter_001_cmd_src_startofpacket;                                                                   // limiter_001:cmd_src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket
594 
        wire   [98:0] limiter_001_cmd_src_data;                                                                            // limiter_001:cmd_src_data -> cmd_xbar_demux_001:sink_data
595 
        wire    [7:0] limiter_001_cmd_src_channel;                                                                         // limiter_001:cmd_src_channel -> cmd_xbar_demux_001:sink_channel
596 
        wire          limiter_001_cmd_src_ready;                                                                           // cmd_xbar_demux_001:sink_ready -> limiter_001:cmd_src_ready
597 
        wire          rsp_xbar_mux_001_src_endofpacket;                                                                    // rsp_xbar_mux_001:src_endofpacket -> limiter_001:rsp_sink_endofpacket
598 
        wire          rsp_xbar_mux_001_src_valid;                                                                          // rsp_xbar_mux_001:src_valid -> limiter_001:rsp_sink_valid
599 
        wire          rsp_xbar_mux_001_src_startofpacket;                                                                  // rsp_xbar_mux_001:src_startofpacket -> limiter_001:rsp_sink_startofpacket
600 
        wire   [98:0] rsp_xbar_mux_001_src_data;                                                                           // rsp_xbar_mux_001:src_data -> limiter_001:rsp_sink_data
601 
        wire    [7:0] rsp_xbar_mux_001_src_channel;                                                                        // rsp_xbar_mux_001:src_channel -> limiter_001:rsp_sink_channel
602 
        wire          rsp_xbar_mux_001_src_ready;                                                                          // limiter_001:rsp_sink_ready -> rsp_xbar_mux_001:src_ready
603 
        wire          cmd_xbar_mux_src_endofpacket;                                                                        // cmd_xbar_mux:src_endofpacket -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_endofpacket
604 
        wire          cmd_xbar_mux_src_valid;                                                                              // cmd_xbar_mux:src_valid -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_valid
605 
        wire          cmd_xbar_mux_src_startofpacket;                                                                      // cmd_xbar_mux:src_startofpacket -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_startofpacket
606 
        wire   [98:0] cmd_xbar_mux_src_data;                                                                               // cmd_xbar_mux:src_data -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_data
607 
        wire    [7:0] cmd_xbar_mux_src_channel;                                                                            // cmd_xbar_mux:src_channel -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_channel
608 
        wire          cmd_xbar_mux_src_ready;                                                                              // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux:src_ready
609 
        wire          id_router_src_endofpacket;                                                                           // id_router:src_endofpacket -> rsp_xbar_demux:sink_endofpacket
610 
        wire          id_router_src_valid;                                                                                 // id_router:src_valid -> rsp_xbar_demux:sink_valid
611 
        wire          id_router_src_startofpacket;                                                                         // id_router:src_startofpacket -> rsp_xbar_demux:sink_startofpacket
612 
        wire   [98:0] id_router_src_data;                                                                                  // id_router:src_data -> rsp_xbar_demux:sink_data
613 
        wire    [7:0] id_router_src_channel;                                                                               // id_router:src_channel -> rsp_xbar_demux:sink_channel
614 
        wire          id_router_src_ready;                                                                                 // rsp_xbar_demux:sink_ready -> id_router:src_ready
615 
        wire          cmd_xbar_demux_001_src2_ready;                                                                       // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src2_ready
616 
        wire          id_router_002_src_endofpacket;                                                                       // id_router_002:src_endofpacket -> rsp_xbar_demux_002:sink_endofpacket
617 
        wire          id_router_002_src_valid;                                                                             // id_router_002:src_valid -> rsp_xbar_demux_002:sink_valid
618 
        wire          id_router_002_src_startofpacket;                                                                     // id_router_002:src_startofpacket -> rsp_xbar_demux_002:sink_startofpacket
619 
        wire   [98:0] id_router_002_src_data;                                                                              // id_router_002:src_data -> rsp_xbar_demux_002:sink_data
620 
        wire    [7:0] id_router_002_src_channel;                                                                           // id_router_002:src_channel -> rsp_xbar_demux_002:sink_channel
621 
        wire          id_router_002_src_ready;                                                                             // rsp_xbar_demux_002:sink_ready -> id_router_002:src_ready
622 
        wire          cmd_xbar_demux_001_src3_ready;                                                                       // timer_1_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src3_ready
623 
        wire          id_router_003_src_endofpacket;                                                                       // id_router_003:src_endofpacket -> rsp_xbar_demux_003:sink_endofpacket
624 
        wire          id_router_003_src_valid;                                                                             // id_router_003:src_valid -> rsp_xbar_demux_003:sink_valid
625 
        wire          id_router_003_src_startofpacket;                                                                     // id_router_003:src_startofpacket -> rsp_xbar_demux_003:sink_startofpacket
626 
        wire   [98:0] id_router_003_src_data;                                                                              // id_router_003:src_data -> rsp_xbar_demux_003:sink_data
627 
        wire    [7:0] id_router_003_src_channel;                                                                           // id_router_003:src_channel -> rsp_xbar_demux_003:sink_channel
628 
        wire          id_router_003_src_ready;                                                                             // rsp_xbar_demux_003:sink_ready -> id_router_003:src_ready
629 
        wire          cmd_xbar_demux_001_src4_ready;                                                                       // timer_0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src4_ready
630 
        wire          id_router_004_src_endofpacket;                                                                       // id_router_004:src_endofpacket -> rsp_xbar_demux_004:sink_endofpacket
631 
        wire          id_router_004_src_valid;                                                                             // id_router_004:src_valid -> rsp_xbar_demux_004:sink_valid
632 
        wire          id_router_004_src_startofpacket;                                                                     // id_router_004:src_startofpacket -> rsp_xbar_demux_004:sink_startofpacket
633 
        wire   [98:0] id_router_004_src_data;                                                                              // id_router_004:src_data -> rsp_xbar_demux_004:sink_data
634 
        wire    [7:0] id_router_004_src_channel;                                                                           // id_router_004:src_channel -> rsp_xbar_demux_004:sink_channel
635 
        wire          id_router_004_src_ready;                                                                             // rsp_xbar_demux_004:sink_ready -> id_router_004:src_ready
636 
        wire          cmd_xbar_demux_001_src5_ready;                                                                       // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src5_ready
637 
        wire          id_router_005_src_endofpacket;                                                                       // id_router_005:src_endofpacket -> rsp_xbar_demux_005:sink_endofpacket
638 
        wire          id_router_005_src_valid;                                                                             // id_router_005:src_valid -> rsp_xbar_demux_005:sink_valid
639 
        wire          id_router_005_src_startofpacket;                                                                     // id_router_005:src_startofpacket -> rsp_xbar_demux_005:sink_startofpacket
640 
        wire   [98:0] id_router_005_src_data;                                                                              // id_router_005:src_data -> rsp_xbar_demux_005:sink_data
641 
        wire    [7:0] id_router_005_src_channel;                                                                           // id_router_005:src_channel -> rsp_xbar_demux_005:sink_channel
642 
        wire          id_router_005_src_ready;                                                                             // rsp_xbar_demux_005:sink_ready -> id_router_005:src_ready
643 
        wire          cmd_xbar_demux_001_src6_ready;                                                                       // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src6_ready
644 
        wire          id_router_006_src_endofpacket;                                                                       // id_router_006:src_endofpacket -> rsp_xbar_demux_006:sink_endofpacket
645 
        wire          id_router_006_src_valid;                                                                             // id_router_006:src_valid -> rsp_xbar_demux_006:sink_valid
646 
        wire          id_router_006_src_startofpacket;                                                                     // id_router_006:src_startofpacket -> rsp_xbar_demux_006:sink_startofpacket
647 
        wire   [98:0] id_router_006_src_data;                                                                              // id_router_006:src_data -> rsp_xbar_demux_006:sink_data
648 
        wire    [7:0] id_router_006_src_channel;                                                                           // id_router_006:src_channel -> rsp_xbar_demux_006:sink_channel
649 
        wire          id_router_006_src_ready;                                                                             // rsp_xbar_demux_006:sink_ready -> id_router_006:src_ready
650 
        wire          cmd_xbar_demux_001_src7_ready;                                                                       // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src7_ready
651 
        wire          id_router_007_src_endofpacket;                                                                       // id_router_007:src_endofpacket -> rsp_xbar_demux_007:sink_endofpacket
652 
        wire          id_router_007_src_valid;                                                                             // id_router_007:src_valid -> rsp_xbar_demux_007:sink_valid
653 
        wire          id_router_007_src_startofpacket;                                                                     // id_router_007:src_startofpacket -> rsp_xbar_demux_007:sink_startofpacket
654 
        wire   [98:0] id_router_007_src_data;                                                                              // id_router_007:src_data -> rsp_xbar_demux_007:sink_data
655 
        wire    [7:0] id_router_007_src_channel;                                                                           // id_router_007:src_channel -> rsp_xbar_demux_007:sink_channel
656 
        wire          id_router_007_src_ready;                                                                             // rsp_xbar_demux_007:sink_ready -> id_router_007:src_ready
657 
        wire          cmd_xbar_demux_002_src0_endofpacket;                                                                 // cmd_xbar_demux_002:src0_endofpacket -> cmd_xbar_mux_008:sink0_endofpacket
658 
        wire          cmd_xbar_demux_002_src0_valid;                                                                       // cmd_xbar_demux_002:src0_valid -> cmd_xbar_mux_008:sink0_valid
659 
        wire          cmd_xbar_demux_002_src0_startofpacket;                                                               // cmd_xbar_demux_002:src0_startofpacket -> cmd_xbar_mux_008:sink0_startofpacket
660 
        wire  [100:0] cmd_xbar_demux_002_src0_data;                                                                        // cmd_xbar_demux_002:src0_data -> cmd_xbar_mux_008:sink0_data
661 
        wire    [1:0] cmd_xbar_demux_002_src0_channel;                                                                     // cmd_xbar_demux_002:src0_channel -> cmd_xbar_mux_008:sink0_channel
662 
        wire          cmd_xbar_demux_002_src0_ready;                                                                       // cmd_xbar_mux_008:sink0_ready -> cmd_xbar_demux_002:src0_ready
663 
        wire          cmd_xbar_demux_003_src0_endofpacket;                                                                 // cmd_xbar_demux_003:src0_endofpacket -> cmd_xbar_mux_008:sink1_endofpacket
664 
        wire          cmd_xbar_demux_003_src0_valid;                                                                       // cmd_xbar_demux_003:src0_valid -> cmd_xbar_mux_008:sink1_valid
665 
        wire          cmd_xbar_demux_003_src0_startofpacket;                                                               // cmd_xbar_demux_003:src0_startofpacket -> cmd_xbar_mux_008:sink1_startofpacket
666 
        wire  [100:0] cmd_xbar_demux_003_src0_data;                                                                        // cmd_xbar_demux_003:src0_data -> cmd_xbar_mux_008:sink1_data
667 
        wire    [1:0] cmd_xbar_demux_003_src0_channel;                                                                     // cmd_xbar_demux_003:src0_channel -> cmd_xbar_mux_008:sink1_channel
668 
        wire          cmd_xbar_demux_003_src0_ready;                                                                       // cmd_xbar_mux_008:sink1_ready -> cmd_xbar_demux_003:src0_ready
669 
        wire          rsp_xbar_demux_008_src0_endofpacket;                                                                 // rsp_xbar_demux_008:src0_endofpacket -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:rp_endofpacket
670 
        wire          rsp_xbar_demux_008_src0_valid;                                                                       // rsp_xbar_demux_008:src0_valid -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:rp_valid
671 
        wire          rsp_xbar_demux_008_src0_startofpacket;                                                               // rsp_xbar_demux_008:src0_startofpacket -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:rp_startofpacket
672 
        wire  [100:0] rsp_xbar_demux_008_src0_data;                                                                        // rsp_xbar_demux_008:src0_data -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:rp_data
673 
        wire    [1:0] rsp_xbar_demux_008_src0_channel;                                                                     // rsp_xbar_demux_008:src0_channel -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:rp_channel
674 
        wire          rsp_xbar_demux_008_src1_endofpacket;                                                                 // rsp_xbar_demux_008:src1_endofpacket -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:rp_endofpacket
675 
        wire          rsp_xbar_demux_008_src1_valid;                                                                       // rsp_xbar_demux_008:src1_valid -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:rp_valid
676 
        wire          rsp_xbar_demux_008_src1_startofpacket;                                                               // rsp_xbar_demux_008:src1_startofpacket -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:rp_startofpacket
677 
        wire  [100:0] rsp_xbar_demux_008_src1_data;                                                                        // rsp_xbar_demux_008:src1_data -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:rp_data
678 
        wire    [1:0] rsp_xbar_demux_008_src1_channel;                                                                     // rsp_xbar_demux_008:src1_channel -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:rp_channel
679 
        wire          addr_router_002_src_endofpacket;                                                                     // addr_router_002:src_endofpacket -> cmd_xbar_demux_002:sink_endofpacket
680 
        wire          addr_router_002_src_valid;                                                                           // addr_router_002:src_valid -> cmd_xbar_demux_002:sink_valid
681 
        wire          addr_router_002_src_startofpacket;                                                                   // addr_router_002:src_startofpacket -> cmd_xbar_demux_002:sink_startofpacket
682 
        wire  [100:0] addr_router_002_src_data;                                                                            // addr_router_002:src_data -> cmd_xbar_demux_002:sink_data
683 
        wire    [1:0] addr_router_002_src_channel;                                                                         // addr_router_002:src_channel -> cmd_xbar_demux_002:sink_channel
684 
        wire          addr_router_002_src_ready;                                                                           // cmd_xbar_demux_002:sink_ready -> addr_router_002:src_ready
685 
        wire          rsp_xbar_demux_008_src0_ready;                                                                       // hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_demux_008:src0_ready
686 
        wire          addr_router_003_src_endofpacket;                                                                     // addr_router_003:src_endofpacket -> cmd_xbar_demux_003:sink_endofpacket
687 
        wire          addr_router_003_src_valid;                                                                           // addr_router_003:src_valid -> cmd_xbar_demux_003:sink_valid
688 
        wire          addr_router_003_src_startofpacket;                                                                   // addr_router_003:src_startofpacket -> cmd_xbar_demux_003:sink_startofpacket
689 
        wire  [100:0] addr_router_003_src_data;                                                                            // addr_router_003:src_data -> cmd_xbar_demux_003:sink_data
690 
        wire    [1:0] addr_router_003_src_channel;                                                                         // addr_router_003:src_channel -> cmd_xbar_demux_003:sink_channel
691 
        wire          addr_router_003_src_ready;                                                                           // cmd_xbar_demux_003:sink_ready -> addr_router_003:src_ready
692 
        wire          rsp_xbar_demux_008_src1_ready;                                                                       // hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_demux_008:src1_ready
693 
        wire          cmd_xbar_mux_008_src_endofpacket;                                                                    // cmd_xbar_mux_008:src_endofpacket -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:cp_endofpacket
694 
        wire          cmd_xbar_mux_008_src_valid;                                                                          // cmd_xbar_mux_008:src_valid -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:cp_valid
695 
        wire          cmd_xbar_mux_008_src_startofpacket;                                                                  // cmd_xbar_mux_008:src_startofpacket -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:cp_startofpacket
696 
        wire  [100:0] cmd_xbar_mux_008_src_data;                                                                           // cmd_xbar_mux_008:src_data -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:cp_data
697 
        wire    [1:0] cmd_xbar_mux_008_src_channel;                                                                        // cmd_xbar_mux_008:src_channel -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:cp_channel
698 
        wire          cmd_xbar_mux_008_src_ready;                                                                          // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_008:src_ready
699 
        wire          id_router_008_src_endofpacket;                                                                       // id_router_008:src_endofpacket -> rsp_xbar_demux_008:sink_endofpacket
700 
        wire          id_router_008_src_valid;                                                                             // id_router_008:src_valid -> rsp_xbar_demux_008:sink_valid
701 
        wire          id_router_008_src_startofpacket;                                                                     // id_router_008:src_startofpacket -> rsp_xbar_demux_008:sink_startofpacket
702 
        wire  [100:0] id_router_008_src_data;                                                                              // id_router_008:src_data -> rsp_xbar_demux_008:sink_data
703 
        wire    [1:0] id_router_008_src_channel;                                                                           // id_router_008:src_channel -> rsp_xbar_demux_008:sink_channel
704 
        wire          id_router_008_src_ready;                                                                             // rsp_xbar_demux_008:sink_ready -> id_router_008:src_ready
705 
        wire          cmd_xbar_mux_001_src_endofpacket;                                                                    // cmd_xbar_mux_001:src_endofpacket -> width_adapter:in_endofpacket
706 
        wire          cmd_xbar_mux_001_src_valid;                                                                          // cmd_xbar_mux_001:src_valid -> width_adapter:in_valid
707 
        wire          cmd_xbar_mux_001_src_startofpacket;                                                                  // cmd_xbar_mux_001:src_startofpacket -> width_adapter:in_startofpacket
708 
        wire   [98:0] cmd_xbar_mux_001_src_data;                                                                           // cmd_xbar_mux_001:src_data -> width_adapter:in_data
709 
        wire    [7:0] cmd_xbar_mux_001_src_channel;                                                                        // cmd_xbar_mux_001:src_channel -> width_adapter:in_channel
710 
        wire          cmd_xbar_mux_001_src_ready;                                                                          // width_adapter:in_ready -> cmd_xbar_mux_001:src_ready
711 
        wire          width_adapter_src_endofpacket;                                                                       // width_adapter:out_endofpacket -> burst_adapter:sink0_endofpacket
712 
        wire          width_adapter_src_valid;                                                                             // width_adapter:out_valid -> burst_adapter:sink0_valid
713 
        wire          width_adapter_src_startofpacket;                                                                     // width_adapter:out_startofpacket -> burst_adapter:sink0_startofpacket
714 
        wire   [80:0] width_adapter_src_data;                                                                              // width_adapter:out_data -> burst_adapter:sink0_data
715 
        wire          width_adapter_src_ready;                                                                             // burst_adapter:sink0_ready -> width_adapter:out_ready
716 
        wire    [7:0] width_adapter_src_channel;                                                                           // width_adapter:out_channel -> burst_adapter:sink0_channel
717 
        wire          id_router_001_src_endofpacket;                                                                       // id_router_001:src_endofpacket -> width_adapter_001:in_endofpacket
718 
        wire          id_router_001_src_valid;                                                                             // id_router_001:src_valid -> width_adapter_001:in_valid
719 
        wire          id_router_001_src_startofpacket;                                                                     // id_router_001:src_startofpacket -> width_adapter_001:in_startofpacket
720 
        wire   [80:0] id_router_001_src_data;                                                                              // id_router_001:src_data -> width_adapter_001:in_data
721 
        wire    [7:0] id_router_001_src_channel;                                                                           // id_router_001:src_channel -> width_adapter_001:in_channel
722 
        wire          id_router_001_src_ready;                                                                             // width_adapter_001:in_ready -> id_router_001:src_ready
723 
        wire          width_adapter_001_src_endofpacket;                                                                   // width_adapter_001:out_endofpacket -> rsp_xbar_demux_001:sink_endofpacket
724 
        wire          width_adapter_001_src_valid;                                                                         // width_adapter_001:out_valid -> rsp_xbar_demux_001:sink_valid
725 
        wire          width_adapter_001_src_startofpacket;                                                                 // width_adapter_001:out_startofpacket -> rsp_xbar_demux_001:sink_startofpacket
726 
        wire   [98:0] width_adapter_001_src_data;                                                                          // width_adapter_001:out_data -> rsp_xbar_demux_001:sink_data
727 
        wire          width_adapter_001_src_ready;                                                                         // rsp_xbar_demux_001:sink_ready -> width_adapter_001:out_ready
728 
        wire    [7:0] width_adapter_001_src_channel;                                                                       // width_adapter_001:out_channel -> rsp_xbar_demux_001:sink_channel
729 
        wire    [7:0] limiter_cmd_valid_data;                                                                              // limiter:cmd_src_valid -> cmd_xbar_demux:sink_valid
730 
        wire    [7:0] limiter_001_cmd_valid_data;                                                                          // limiter_001:cmd_src_valid -> cmd_xbar_demux_001:sink_valid
731 
        wire          irq_mapper_receiver0_irq;                                                                            // jtag_uart_1:av_irq -> irq_mapper:receiver0_irq
732 
        wire          irq_mapper_receiver1_irq;                                                                            // timer_1:irq -> irq_mapper:receiver1_irq
733 
        wire          irq_mapper_receiver2_irq;                                                                            // timer_0:irq -> irq_mapper:receiver2_irq
734 
        wire          irq_mapper_receiver3_irq;                                                                            // hibi_pe_dma_0:rx_irq_out -> irq_mapper:receiver3_irq
735 
        wire   [31:0] nios2_qsys_1_d_irq_irq;                                                                              // irq_mapper:sender_irq -> nios2_qsys_1:d_irq
736 
 
737 
        nios2_sdram_nios2_qsys_1 nios2_qsys_1 (
738 
                .clk                                   (clk_clk),                                                                     //                       clk.clk
739 
                .reset_n                               (~rst_controller_reset_out_reset),                                             //                   reset_n.reset_n
740 
                .d_address                             (nios2_qsys_1_data_master_address),                                            //               data_master.address
741 
                .d_byteenable                          (nios2_qsys_1_data_master_byteenable),                                         //                          .byteenable
742 
                .d_read                                (nios2_qsys_1_data_master_read),                                               //                          .read
743 
                .d_readdata                            (nios2_qsys_1_data_master_readdata),                                           //                          .readdata
744 
                .d_waitrequest                         (nios2_qsys_1_data_master_waitrequest),                                        //                          .waitrequest
745 
                .d_write                               (nios2_qsys_1_data_master_write),                                              //                          .write
746 
                .d_writedata                           (nios2_qsys_1_data_master_writedata),                                          //                          .writedata
747 
                .d_readdatavalid                       (nios2_qsys_1_data_master_readdatavalid),                                      //                          .readdatavalid
748 
                .jtag_debug_module_debugaccess_to_roms (nios2_qsys_1_data_master_debugaccess),                                        //                          .debugaccess
749 
                .i_address                             (nios2_qsys_1_instruction_master_address),                                     //        instruction_master.address
750 
                .i_read                                (nios2_qsys_1_instruction_master_read),                                        //                          .read
751 
                .i_readdata                            (nios2_qsys_1_instruction_master_readdata),                                    //                          .readdata
752 
                .i_waitrequest                         (nios2_qsys_1_instruction_master_waitrequest),                                 //                          .waitrequest
753 
                .i_readdatavalid                       (nios2_qsys_1_instruction_master_readdatavalid),                               //                          .readdatavalid
754 
                .d_irq                                 (nios2_qsys_1_d_irq_irq),                                                      //                     d_irq.irq
755 
                .jtag_debug_module_resetrequest        (),                                                                            //   jtag_debug_module_reset.reset
756 
                .jtag_debug_module_address             (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_address),       //         jtag_debug_module.address
757 
                .jtag_debug_module_begintransfer       (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer), //                          .begintransfer
758 
                .jtag_debug_module_byteenable          (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_byteenable),    //                          .byteenable
759 
                .jtag_debug_module_debugaccess         (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess),   //                          .debugaccess
760 
                .jtag_debug_module_readdata            (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_readdata),      //                          .readdata
761 
                .jtag_debug_module_select              (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_chipselect),    //                          .chipselect
762 
                .jtag_debug_module_write               (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_write),         //                          .write
763 
                .jtag_debug_module_writedata           (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_writedata),     //                          .writedata
764 
                .no_ci_readra                          ()                                                                             // custom_instruction_master.readra
765 
        );
766 
 
767 
        nios2_sdram_onchip_memory2_1 onchip_memory2_1 (
768 
                .clk         (clk_clk),                                                       //   clk1.clk
769 
                .address     (onchip_memory2_1_s1_translator_avalon_anti_slave_0_address),    //     s1.address
770 
                .chipselect  (onchip_memory2_1_s1_translator_avalon_anti_slave_0_chipselect), //       .chipselect
771 
                .clken       (onchip_memory2_1_s1_translator_avalon_anti_slave_0_clken),      //       .clken
772 
                .readdata    (onchip_memory2_1_s1_translator_avalon_anti_slave_0_readdata),   //       .readdata
773 
                .write       (onchip_memory2_1_s1_translator_avalon_anti_slave_0_write),      //       .write
774 
                .writedata   (onchip_memory2_1_s1_translator_avalon_anti_slave_0_writedata),  //       .writedata
775 
                .byteenable  (onchip_memory2_1_s1_translator_avalon_anti_slave_0_byteenable), //       .byteenable
776 
                .reset       (rst_controller_reset_out_reset),                                // reset1.reset
777 
                .address2    (onchip_memory2_1_s2_translator_avalon_anti_slave_0_address),    //     s2.address
778 
                .chipselect2 (onchip_memory2_1_s2_translator_avalon_anti_slave_0_chipselect), //       .chipselect
779 
                .clken2      (onchip_memory2_1_s2_translator_avalon_anti_slave_0_clken),      //       .clken
780 
                .readdata2   (onchip_memory2_1_s2_translator_avalon_anti_slave_0_readdata),   //       .readdata
781 
                .write2      (onchip_memory2_1_s2_translator_avalon_anti_slave_0_write),      //       .write
782 
                .writedata2  (onchip_memory2_1_s2_translator_avalon_anti_slave_0_writedata),  //       .writedata
783 
                .byteenable2 (onchip_memory2_1_s2_translator_avalon_anti_slave_0_byteenable), //       .byteenable
784 
                .clk2        (clk_clk),                                                       //   clk2.clk
785 
                .reset2      (rst_controller_reset_out_reset)                                 // reset2.reset
786 
        );
787 
 
788 
        nios2_sdram_jtag_uart_1 jtag_uart_1 (
789 
                .clk            (clk_clk),                                                                  //               clk.clk
790 
                .rst_n          (~rst_controller_reset_out_reset),                                          //             reset.reset_n
791 
                .av_chipselect  (jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect),  // avalon_jtag_slave.chipselect
792 
                .av_address     (jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_address),     //                  .address
793 
                .av_read_n      (~jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_read),       //                  .read_n
794 
                .av_readdata    (jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata),    //                  .readdata
795 
                .av_write_n     (~jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_write),      //                  .write_n
796 
                .av_writedata   (jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata),   //                  .writedata
797 
                .av_waitrequest (jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest), //                  .waitrequest
798 
                .av_irq         (irq_mapper_receiver0_irq)                                                  //               irq.irq
799 
        );
800 
 
801 
        nios2_sdram_sysid_qsys_1 sysid_qsys_1 (
802 
                .clock    (clk_clk),                                                            //           clk.clk
803 
                .reset_n  (~rst_controller_reset_out_reset),                                    //         reset.reset_n
804 
                .readdata (sysid_qsys_1_control_slave_translator_avalon_anti_slave_0_readdata), // control_slave.readdata
805 
                .address  (sysid_qsys_1_control_slave_translator_avalon_anti_slave_0_address)   //              .address
806 
        );
807 
 
808 
        nios2_sdram_timer_0 timer_0 (
809 
                .clk        (clk_clk),                                              //   clk.clk
810 
                .reset_n    (~rst_controller_reset_out_reset),                      // reset.reset_n
811 
                .address    (timer_0_s1_translator_avalon_anti_slave_0_address),    //    s1.address
812 
                .writedata  (timer_0_s1_translator_avalon_anti_slave_0_writedata),  //      .writedata
813 
                .readdata   (timer_0_s1_translator_avalon_anti_slave_0_readdata),   //      .readdata
814 
                .chipselect (timer_0_s1_translator_avalon_anti_slave_0_chipselect), //      .chipselect
815 
                .write_n    (~timer_0_s1_translator_avalon_anti_slave_0_write),     //      .write_n
816 
                .irq        (irq_mapper_receiver2_irq)                              //   irq.irq
817 
        );
818 
 
819 
        nios2_sdram_timer_0 timer_1 (
820 
                .clk        (clk_clk),                                              //   clk.clk
821 
                .reset_n    (~rst_controller_reset_out_reset),                      // reset.reset_n
822 
                .address    (timer_1_s1_translator_avalon_anti_slave_0_address),    //    s1.address
823 
                .writedata  (timer_1_s1_translator_avalon_anti_slave_0_writedata),  //      .writedata
824 
                .readdata   (timer_1_s1_translator_avalon_anti_slave_0_readdata),   //      .readdata
825 
                .chipselect (timer_1_s1_translator_avalon_anti_slave_0_chipselect), //      .chipselect
826 
                .write_n    (~timer_1_s1_translator_avalon_anti_slave_0_write),     //      .write_n
827 
                .irq        (irq_mapper_receiver1_irq)                              //   irq.irq
828 
        );
829 
 
830 
        nios2_sdram_sdram_0 sdram_0 (
831 
                .clk            (clk_clk),                                                 //   clk.clk
832 
                .reset_n        (~rst_controller_reset_out_reset),                         // reset.reset_n
833 
                .az_addr        (sdram_0_s1_translator_avalon_anti_slave_0_address),       //    s1.address
834 
                .az_be_n        (~sdram_0_s1_translator_avalon_anti_slave_0_byteenable),   //      .byteenable_n
835 
                .az_cs          (sdram_0_s1_translator_avalon_anti_slave_0_chipselect),    //      .chipselect
836 
                .az_data        (sdram_0_s1_translator_avalon_anti_slave_0_writedata),     //      .writedata
837 
                .az_rd_n        (~sdram_0_s1_translator_avalon_anti_slave_0_read),         //      .read_n
838 
                .az_wr_n        (~sdram_0_s1_translator_avalon_anti_slave_0_write),        //      .write_n
839 
                .za_data        (sdram_0_s1_translator_avalon_anti_slave_0_readdata),      //      .readdata
840 
                .za_valid       (sdram_0_s1_translator_avalon_anti_slave_0_readdatavalid), //      .readdatavalid
841 
                .za_waitrequest (sdram_0_s1_translator_avalon_anti_slave_0_waitrequest),   //      .waitrequest
842 
                .zs_addr        (sdram_0_addr),                                            //  wire.export
843 
                .zs_ba          (sdram_0_ba),                                              //      .export
844 
                .zs_cas_n       (sdram_0_cas_n),                                           //      .export
845 
                .zs_cke         (sdram_0_cke),                                             //      .export
846 
                .zs_cs_n        (sdram_0_cs_n),                                            //      .export
847 
                .zs_dq          (sdram_0_dq),                                              //      .export
848 
                .zs_dqm         (sdram_0_dqm),                                             //      .export
849 
                .zs_ras_n       (sdram_0_ras_n),                                           //      .export
850 
                .zs_we_n        (sdram_0_we_n)                                             //      .export
851 
        );
852 
 
853 
        hibi_pe_dma #(
854 
                .data_width_g       (32),
855 
                .addr_width_g       (32),
856 
                .words_width_g      (16),
857 
                .n_stream_chans_g   (2),
858 
                .n_packet_chans_g   (2),
859 
                .n_chans_bits_g     (3),
860 
                .hibi_addr_cmp_lo_g (0),
861 
                .hibi_addr_cmp_hi_g (31)
862 
        ) hibi_pe_dma_0 (
863 
                .avalon_cfg_addr_in         (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_address),     //   avalon_slave_0.address
864 
                .avalon_cfg_we_in           (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_write),       //                 .write
865 
                .avalon_cfg_re_in           (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_read),        //                 .read
866 
                .avalon_cfg_cs_in           (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_chipselect),  //                 .chipselect
867 
                .avalon_cfg_waitrequest_out (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest), //                 .waitrequest
868 
                .avalon_cfg_writedata_in    (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata),   //                 .writedata
869 
                .avalon_cfg_readdata_out    (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata),    //                 .readdata
870 
                .hibi_data_in               (hibi_pe_dma_data_in),                                                     //      conduit_end.export
871 
                .hibi_av_in                 (hibi_pe_dma_av_in),                                                       //                 .export
872 
                .hibi_empty_in              (hibi_pe_dma_empty_in),                                                    //                 .export
873 
                .hibi_comm_in               (hibi_pe_dma_comm_in),                                                     //                 .export
874 
                .hibi_re_out                (hibi_pe_dma_re_out),                                                      //                 .export
875 
                .hibi_data_out              (hibi_pe_dma_data_out),                                                    //                 .export
876 
                .hibi_av_out                (hibi_pe_dma_av_out),                                                      //                 .export
877 
                .hibi_full_in               (hibi_pe_dma_full_in),                                                     //                 .export
878 
                .hibi_comm_out              (hibi_pe_dma_comm_out),                                                    //                 .export
879 
                .hibi_we_out                (hibi_pe_dma_we_out),                                                      //                 .export
880 
                .rst_n                      (~rst_controller_reset_out_reset),                                         // clock_sink_reset.reset_n
881 
                .rx_irq_out                 (irq_mapper_receiver3_irq),                                                // interrupt_sender.irq
882 
                .avalon_addr_out_rx         (hibi_pe_dma_0_avalon_master_address),                                     //    avalon_master.address
883 
                .avalon_we_out_rx           (hibi_pe_dma_0_avalon_master_write),                                       //                 .write
884 
                .avalon_be_out_rx           (hibi_pe_dma_0_avalon_master_byteenable),                                  //                 .byteenable
885 
                .avalon_writedata_out_rx    (hibi_pe_dma_0_avalon_master_writedata),                                   //                 .writedata
886 
                .avalon_waitrequest_in_rx   (hibi_pe_dma_0_avalon_master_waitrequest),                                 //                 .waitrequest
887 
                .avalon_readdatavalid_in_tx (hibi_pe_dma_0_avalon_master_1_readdatavalid),                             //  avalon_master_1.readdatavalid
888 
                .avalon_waitrequest_in_tx   (hibi_pe_dma_0_avalon_master_1_waitrequest),                               //                 .waitrequest
889 
                .avalon_readdata_in_tx      (hibi_pe_dma_0_avalon_master_1_readdata),                                  //                 .readdata
890 
                .avalon_re_out_tx           (hibi_pe_dma_0_avalon_master_1_read),                                      //                 .read
891 
                .avalon_addr_out_tx         (hibi_pe_dma_0_avalon_master_1_address),                                   //                 .address
892 
                .clk                        (clk_clk)                                                                  //            clock.clk
893 
        );
894 
 
895 
        altera_merlin_master_translator #(
896 
                .AV_ADDRESS_W                (26),
897 
                .AV_DATA_W                   (32),
898 
                .AV_BURSTCOUNT_W             (1),
899 
                .AV_BYTEENABLE_W             (4),
900 
                .UAV_ADDRESS_W               (26),
901 
                .UAV_BURSTCOUNT_W            (3),
902 
                .USE_READ                    (1),
903 
                .USE_WRITE                   (0),
904 
                .USE_BEGINBURSTTRANSFER      (0),
905 
                .USE_BEGINTRANSFER           (0),
906 
                .USE_CHIPSELECT              (0),
907 
                .USE_BURSTCOUNT              (0),
908 
                .USE_READDATAVALID           (1),
909 
                .USE_WAITREQUEST             (1),
910 
                .AV_SYMBOLS_PER_WORD         (4),
911 
                .AV_ADDRESS_SYMBOLS          (1),
912 
                .AV_BURSTCOUNT_SYMBOLS       (0),
913 
                .AV_CONSTANT_BURST_BEHAVIOR  (0),
914 
                .UAV_CONSTANT_BURST_BEHAVIOR (0),
915 
                .AV_LINEWRAPBURSTS           (1),
916 
                .AV_REGISTERINCOMINGSIGNALS  (0)
917 
        ) nios2_qsys_1_instruction_master_translator (
918 
                .clk                   (clk_clk),                                                                            //                       clk.clk
919 
                .reset                 (rst_controller_reset_out_reset),                                                     //                     reset.reset
920 
                .uav_address           (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
921 
                .uav_burstcount        (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
922 
                .uav_read              (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_read),          //                          .read
923 
                .uav_write             (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_write),         //                          .write
924 
                .uav_waitrequest       (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
925 
                .uav_readdatavalid     (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
926 
                .uav_byteenable        (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
927 
                .uav_readdata          (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
928 
                .uav_writedata         (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
929 
                .uav_lock              (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_lock),          //                          .lock
930 
                .uav_debugaccess       (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
931 
                .av_address            (nios2_qsys_1_instruction_master_address),                                            //      avalon_anti_master_0.address
932 
                .av_waitrequest        (nios2_qsys_1_instruction_master_waitrequest),                                        //                          .waitrequest
933 
                .av_read               (nios2_qsys_1_instruction_master_read),                                               //                          .read
934 
                .av_readdata           (nios2_qsys_1_instruction_master_readdata),                                           //                          .readdata
935 
                .av_readdatavalid      (nios2_qsys_1_instruction_master_readdatavalid),                                      //                          .readdatavalid
936 
                .av_burstcount         (1'b1),                                                                               //               (terminated)
937 
                .av_byteenable         (4'b1111),                                                                            //               (terminated)
938 
                .av_beginbursttransfer (1'b0),                                                                               //               (terminated)
939 
                .av_begintransfer      (1'b0),                                                                               //               (terminated)
940 
                .av_chipselect         (1'b0),                                                                               //               (terminated)
941 
                .av_write              (1'b0),                                                                               //               (terminated)
942 
                .av_writedata          (32'b00000000000000000000000000000000),                                               //               (terminated)
943 
                .av_lock               (1'b0),                                                                               //               (terminated)
944 
                .av_debugaccess        (1'b0),                                                                               //               (terminated)
945 
                .uav_clken             (),                                                                                   //               (terminated)
946 
                .av_clken              (1'b1)                                                                                //               (terminated)
947 
        );
948 
 
949 
        altera_merlin_master_translator #(
950 
                .AV_ADDRESS_W                (26),
951 
                .AV_DATA_W                   (32),
952 
                .AV_BURSTCOUNT_W             (1),
953 
                .AV_BYTEENABLE_W             (4),
954 
                .UAV_ADDRESS_W               (26),
955 
                .UAV_BURSTCOUNT_W            (3),
956 
                .USE_READ                    (1),
957 
                .USE_WRITE                   (1),
958 
                .USE_BEGINBURSTTRANSFER      (0),
959 
                .USE_BEGINTRANSFER           (0),
960 
                .USE_CHIPSELECT              (0),
961 
                .USE_BURSTCOUNT              (0),
962 
                .USE_READDATAVALID           (1),
963 
                .USE_WAITREQUEST             (1),
964 
                .AV_SYMBOLS_PER_WORD         (4),
965 
                .AV_ADDRESS_SYMBOLS          (1),
966 
                .AV_BURSTCOUNT_SYMBOLS       (0),
967 
                .AV_CONSTANT_BURST_BEHAVIOR  (0),
968 
                .UAV_CONSTANT_BURST_BEHAVIOR (0),
969 
                .AV_LINEWRAPBURSTS           (0),
970 
                .AV_REGISTERINCOMINGSIGNALS  (0)
971 
        ) nios2_qsys_1_data_master_translator (
972 
                .clk                   (clk_clk),                                                                     //                       clk.clk
973 
                .reset                 (rst_controller_reset_out_reset),                                              //                     reset.reset
974 
                .uav_address           (nios2_qsys_1_data_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
975 
                .uav_burstcount        (nios2_qsys_1_data_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
976 
                .uav_read              (nios2_qsys_1_data_master_translator_avalon_universal_master_0_read),          //                          .read
977 
                .uav_write             (nios2_qsys_1_data_master_translator_avalon_universal_master_0_write),         //                          .write
978 
                .uav_waitrequest       (nios2_qsys_1_data_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
979 
                .uav_readdatavalid     (nios2_qsys_1_data_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
980 
                .uav_byteenable        (nios2_qsys_1_data_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
981 
                .uav_readdata          (nios2_qsys_1_data_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
982 
                .uav_writedata         (nios2_qsys_1_data_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
983 
                .uav_lock              (nios2_qsys_1_data_master_translator_avalon_universal_master_0_lock),          //                          .lock
984 
                .uav_debugaccess       (nios2_qsys_1_data_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
985 
                .av_address            (nios2_qsys_1_data_master_address),                                            //      avalon_anti_master_0.address
986 
                .av_waitrequest        (nios2_qsys_1_data_master_waitrequest),                                        //                          .waitrequest
987 
                .av_byteenable         (nios2_qsys_1_data_master_byteenable),                                         //                          .byteenable
988 
                .av_read               (nios2_qsys_1_data_master_read),                                               //                          .read
989 
                .av_readdata           (nios2_qsys_1_data_master_readdata),                                           //                          .readdata
990 
                .av_readdatavalid      (nios2_qsys_1_data_master_readdatavalid),                                      //                          .readdatavalid
991 
                .av_write              (nios2_qsys_1_data_master_write),                                              //                          .write
992 
                .av_writedata          (nios2_qsys_1_data_master_writedata),                                          //                          .writedata
993 
                .av_debugaccess        (nios2_qsys_1_data_master_debugaccess),                                        //                          .debugaccess
994 
                .av_burstcount         (1'b1),                                                                        //               (terminated)
995 
                .av_beginbursttransfer (1'b0),                                                                        //               (terminated)
996 
                .av_begintransfer      (1'b0),                                                                        //               (terminated)
997 
                .av_chipselect         (1'b0),                                                                        //               (terminated)
998 
                .av_lock               (1'b0),                                                                        //               (terminated)
999 
                .uav_clken             (),                                                                            //               (terminated)
1000 
                .av_clken              (1'b1)                                                                         //               (terminated)
1001 
        );
1002 
 
1003 
        altera_merlin_slave_translator #(
1004 
                .AV_ADDRESS_W                   (9),
1005 
                .AV_DATA_W                      (32),
1006 
                .UAV_DATA_W                     (32),
1007 
                .AV_BURSTCOUNT_W                (1),
1008 
                .AV_BYTEENABLE_W                (4),
1009 
                .UAV_BYTEENABLE_W               (4),
1010 
                .UAV_ADDRESS_W                  (26),
1011 
                .UAV_BURSTCOUNT_W               (3),
1012 
                .AV_READLATENCY                 (0),
1013 
                .USE_READDATAVALID              (0),
1014 
                .USE_WAITREQUEST                (0),
1015 
                .USE_UAV_CLKEN                  (0),
1016 
                .AV_SYMBOLS_PER_WORD            (4),
1017 
                .AV_ADDRESS_SYMBOLS             (0),
1018 
                .AV_BURSTCOUNT_SYMBOLS          (0),
1019 
                .AV_CONSTANT_BURST_BEHAVIOR     (0),
1020 
                .UAV_CONSTANT_BURST_BEHAVIOR    (0),
1021 
                .AV_REQUIRE_UNALIGNED_ADDRESSES (0),
1022 
                .CHIPSELECT_THROUGH_READLATENCY (0),
1023 
                .AV_READ_WAIT_CYCLES            (1),
1024 
                .AV_WRITE_WAIT_CYCLES           (0),
1025 
                .AV_SETUP_WAIT_CYCLES           (0),
1026 
                .AV_DATA_HOLD_CYCLES            (0)
1027 
        ) nios2_qsys_1_jtag_debug_module_translator (
1028 
                .clk                   (clk_clk),                                                                                   //                      clk.clk
1029 
                .reset                 (rst_controller_reset_out_reset),                                                            //                    reset.reset
1030 
                .uav_address           (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
1031 
                .uav_burstcount        (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
1032 
                .uav_read              (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
1033 
                .uav_write             (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
1034 
                .uav_waitrequest       (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
1035 
                .uav_readdatavalid     (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
1036 
                .uav_byteenable        (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
1037 
                .uav_readdata          (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
1038 
                .uav_writedata         (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
1039 
                .uav_lock              (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
1040 
                .uav_debugaccess       (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
1041 
                .av_address            (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
1042 
                .av_write              (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_write),                       //                         .write
1043 
                .av_readdata           (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
1044 
                .av_writedata          (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
1045 
                .av_begintransfer      (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer),               //                         .begintransfer
1046 
                .av_byteenable         (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_byteenable),                  //                         .byteenable
1047 
                .av_chipselect         (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_chipselect),                  //                         .chipselect
1048 
                .av_debugaccess        (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess),                 //                         .debugaccess
1049 
                .av_read               (),                                                                                          //              (terminated)
1050 
                .av_beginbursttransfer (),                                                                                          //              (terminated)
1051 
                .av_burstcount         (),                                                                                          //              (terminated)
1052 
                .av_readdatavalid      (1'b0),                                                                                      //              (terminated)
1053 
                .av_waitrequest        (1'b0),                                                                                      //              (terminated)
1054 
                .av_writebyteenable    (),                                                                                          //              (terminated)
1055 
                .av_lock               (),                                                                                          //              (terminated)
1056 
                .av_clken              (),                                                                                          //              (terminated)
1057 
                .uav_clken             (1'b0),                                                                                      //              (terminated)
1058 
                .av_outputenable       ()                                                                                           //              (terminated)
1059 
        );
1060 
 
1061 
        altera_merlin_slave_translator #(
1062 
                .AV_ADDRESS_W                   (22),
1063 
                .AV_DATA_W                      (16),
1064 
                .UAV_DATA_W                     (16),
1065 
                .AV_BURSTCOUNT_W                (1),
1066 
                .AV_BYTEENABLE_W                (2),
1067 
                .UAV_BYTEENABLE_W               (2),
1068 
                .UAV_ADDRESS_W                  (26),
1069 
                .UAV_BURSTCOUNT_W               (2),
1070 
                .AV_READLATENCY                 (0),
1071 
                .USE_READDATAVALID              (1),
1072 
                .USE_WAITREQUEST                (1),
1073 
                .USE_UAV_CLKEN                  (0),
1074 
                .AV_SYMBOLS_PER_WORD            (2),
1075 
                .AV_ADDRESS_SYMBOLS             (0),
1076 
                .AV_BURSTCOUNT_SYMBOLS          (0),
1077 
                .AV_CONSTANT_BURST_BEHAVIOR     (0),
1078 
                .UAV_CONSTANT_BURST_BEHAVIOR    (0),
1079 
                .AV_REQUIRE_UNALIGNED_ADDRESSES (0),
1080 
                .CHIPSELECT_THROUGH_READLATENCY (0),
1081 
                .AV_READ_WAIT_CYCLES            (1),
1082 
                .AV_WRITE_WAIT_CYCLES           (0),
1083 
                .AV_SETUP_WAIT_CYCLES           (0),
1084 
                .AV_DATA_HOLD_CYCLES            (0)
1085 
        ) sdram_0_s1_translator (
1086 
                .clk                   (clk_clk),                                                               //                      clk.clk
1087 
                .reset                 (rst_controller_reset_out_reset),                                        //                    reset.reset
1088 
                .uav_address           (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
1089 
                .uav_burstcount        (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
1090 
                .uav_read              (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
1091 
                .uav_write             (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
1092 
                .uav_waitrequest       (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
1093 
                .uav_readdatavalid     (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
1094 
                .uav_byteenable        (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
1095 
                .uav_readdata          (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
1096 
                .uav_writedata         (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
1097 
                .uav_lock              (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
1098 
                .uav_debugaccess       (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
1099 
                .av_address            (sdram_0_s1_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
1100 
                .av_write              (sdram_0_s1_translator_avalon_anti_slave_0_write),                       //                         .write
1101 
                .av_read               (sdram_0_s1_translator_avalon_anti_slave_0_read),                        //                         .read
1102 
                .av_readdata           (sdram_0_s1_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
1103 
                .av_writedata          (sdram_0_s1_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
1104 
                .av_byteenable         (sdram_0_s1_translator_avalon_anti_slave_0_byteenable),                  //                         .byteenable
1105 
                .av_readdatavalid      (sdram_0_s1_translator_avalon_anti_slave_0_readdatavalid),               //                         .readdatavalid
1106 
                .av_waitrequest        (sdram_0_s1_translator_avalon_anti_slave_0_waitrequest),                 //                         .waitrequest
1107 
                .av_chipselect         (sdram_0_s1_translator_avalon_anti_slave_0_chipselect),                  //                         .chipselect
1108 
                .av_begintransfer      (),                                                                      //              (terminated)
1109 
                .av_beginbursttransfer (),                                                                      //              (terminated)
1110 
                .av_burstcount         (),                                                                      //              (terminated)
1111 
                .av_writebyteenable    (),                                                                      //              (terminated)
1112 
                .av_lock               (),                                                                      //              (terminated)
1113 
                .av_clken              (),                                                                      //              (terminated)
1114 
                .uav_clken             (1'b0),                                                                  //              (terminated)
1115 
                .av_debugaccess        (),                                                                      //              (terminated)
1116 
                .av_outputenable       ()                                                                       //              (terminated)
1117 
        );
1118 
 
1119 
        altera_merlin_slave_translator #(
1120 
                .AV_ADDRESS_W                   (1),
1121 
                .AV_DATA_W                      (32),
1122 
                .UAV_DATA_W                     (32),
1123 
                .AV_BURSTCOUNT_W                (1),
1124 
                .AV_BYTEENABLE_W                (1),
1125 
                .UAV_BYTEENABLE_W               (4),
1126 
                .UAV_ADDRESS_W                  (26),
1127 
                .UAV_BURSTCOUNT_W               (3),
1128 
                .AV_READLATENCY                 (0),
1129 
                .USE_READDATAVALID              (0),
1130 
                .USE_WAITREQUEST                (1),
1131 
                .USE_UAV_CLKEN                  (0),
1132 
                .AV_SYMBOLS_PER_WORD            (4),
1133 
                .AV_ADDRESS_SYMBOLS             (0),
1134 
                .AV_BURSTCOUNT_SYMBOLS          (0),
1135 
                .AV_CONSTANT_BURST_BEHAVIOR     (0),
1136 
                .UAV_CONSTANT_BURST_BEHAVIOR    (0),
1137 
                .AV_REQUIRE_UNALIGNED_ADDRESSES (0),
1138 
                .CHIPSELECT_THROUGH_READLATENCY (0),
1139 
                .AV_READ_WAIT_CYCLES            (1),
1140 
                .AV_WRITE_WAIT_CYCLES           (0),
1141 
                .AV_SETUP_WAIT_CYCLES           (0),
1142 
                .AV_DATA_HOLD_CYCLES            (0)
1143 
        ) jtag_uart_1_avalon_jtag_slave_translator (
1144 
                .clk                   (clk_clk),                                                                                  //                      clk.clk
1145 
                .reset                 (rst_controller_reset_out_reset),                                                           //                    reset.reset
1146 
                .uav_address           (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
1147 
                .uav_burstcount        (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
1148 
                .uav_read              (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
1149 
                .uav_write             (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
1150 
                .uav_waitrequest       (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
1151 
                .uav_readdatavalid     (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
1152 
                .uav_byteenable        (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
1153 
                .uav_readdata          (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
1154 
                .uav_writedata         (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
1155 
                .uav_lock              (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
1156 
                .uav_debugaccess       (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
1157 
                .av_address            (jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
1158 
                .av_write              (jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_write),                       //                         .write
1159 
                .av_read               (jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_read),                        //                         .read
1160 
                .av_readdata           (jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
1161 
                .av_writedata          (jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
1162 
                .av_waitrequest        (jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest),                 //                         .waitrequest
1163 
                .av_chipselect         (jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect),                  //                         .chipselect
1164 
                .av_begintransfer      (),                                                                                         //              (terminated)
1165 
                .av_beginbursttransfer (),                                                                                         //              (terminated)
1166 
                .av_burstcount         (),                                                                                         //              (terminated)
1167 
                .av_byteenable         (),                                                                                         //              (terminated)
1168 
                .av_readdatavalid      (1'b0),                                                                                     //              (terminated)
1169 
                .av_writebyteenable    (),                                                                                         //              (terminated)
1170 
                .av_lock               (),                                                                                         //              (terminated)
1171 
                .av_clken              (),                                                                                         //              (terminated)
1172 
                .uav_clken             (1'b0),                                                                                     //              (terminated)
1173 
                .av_debugaccess        (),                                                                                         //              (terminated)
1174 
                .av_outputenable       ()                                                                                          //              (terminated)
1175 
        );
1176 
 
1177 
        altera_merlin_slave_translator #(
1178 
                .AV_ADDRESS_W                   (3),
1179 
                .AV_DATA_W                      (16),
1180 
                .UAV_DATA_W                     (32),
1181 
                .AV_BURSTCOUNT_W                (1),
1182 
                .AV_BYTEENABLE_W                (1),
1183 
                .UAV_BYTEENABLE_W               (4),
1184 
                .UAV_ADDRESS_W                  (26),
1185 
                .UAV_BURSTCOUNT_W               (3),
1186 
                .AV_READLATENCY                 (0),
1187 
                .USE_READDATAVALID              (0),
1188 
                .USE_WAITREQUEST                (0),
1189 
                .USE_UAV_CLKEN                  (0),
1190 
                .AV_SYMBOLS_PER_WORD            (4),
1191 
                .AV_ADDRESS_SYMBOLS             (0),
1192 
                .AV_BURSTCOUNT_SYMBOLS          (0),
1193 
                .AV_CONSTANT_BURST_BEHAVIOR     (0),
1194 
                .UAV_CONSTANT_BURST_BEHAVIOR    (0),
1195 
                .AV_REQUIRE_UNALIGNED_ADDRESSES (0),
1196 
                .CHIPSELECT_THROUGH_READLATENCY (0),
1197 
                .AV_READ_WAIT_CYCLES            (1),
1198 
                .AV_WRITE_WAIT_CYCLES           (0),
1199 
                .AV_SETUP_WAIT_CYCLES           (0),
1200 
                .AV_DATA_HOLD_CYCLES            (0)
1201 
        ) timer_1_s1_translator (
1202 
                .clk                   (clk_clk),                                                               //                      clk.clk
1203 
                .reset                 (rst_controller_reset_out_reset),                                        //                    reset.reset
1204 
                .uav_address           (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
1205 
                .uav_burstcount        (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
1206 
                .uav_read              (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
1207 
                .uav_write             (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
1208 
                .uav_waitrequest       (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
1209 
                .uav_readdatavalid     (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
1210 
                .uav_byteenable        (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
1211 
                .uav_readdata          (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
1212 
                .uav_writedata         (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
1213 
                .uav_lock              (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
1214 
                .uav_debugaccess       (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
1215 
                .av_address            (timer_1_s1_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
1216 
                .av_write              (timer_1_s1_translator_avalon_anti_slave_0_write),                       //                         .write
1217 
                .av_readdata           (timer_1_s1_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
1218 
                .av_writedata          (timer_1_s1_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
1219 
                .av_chipselect         (timer_1_s1_translator_avalon_anti_slave_0_chipselect),                  //                         .chipselect
1220 
                .av_read               (),                                                                      //              (terminated)
1221 
                .av_begintransfer      (),                                                                      //              (terminated)
1222 
                .av_beginbursttransfer (),                                                                      //              (terminated)
1223 
                .av_burstcount         (),                                                                      //              (terminated)
1224 
                .av_byteenable         (),                                                                      //              (terminated)
1225 
                .av_readdatavalid      (1'b0),                                                                  //              (terminated)
1226 
                .av_waitrequest        (1'b0),                                                                  //              (terminated)
1227 
                .av_writebyteenable    (),                                                                      //              (terminated)
1228 
                .av_lock               (),                                                                      //              (terminated)
1229 
                .av_clken              (),                                                                      //              (terminated)
1230 
                .uav_clken             (1'b0),                                                                  //              (terminated)
1231 
                .av_debugaccess        (),                                                                      //              (terminated)
1232 
                .av_outputenable       ()                                                                       //              (terminated)
1233 
        );
1234 
 
1235 
        altera_merlin_slave_translator #(
1236 
                .AV_ADDRESS_W                   (3),
1237 
                .AV_DATA_W                      (16),
1238 
                .UAV_DATA_W                     (32),
1239 
                .AV_BURSTCOUNT_W                (1),
1240 
                .AV_BYTEENABLE_W                (1),
1241 
                .UAV_BYTEENABLE_W               (4),
1242 
                .UAV_ADDRESS_W                  (26),
1243 
                .UAV_BURSTCOUNT_W               (3),
1244 
                .AV_READLATENCY                 (0),
1245 
                .USE_READDATAVALID              (0),
1246 
                .USE_WAITREQUEST                (0),
1247 
                .USE_UAV_CLKEN                  (0),
1248 
                .AV_SYMBOLS_PER_WORD            (4),
1249 
                .AV_ADDRESS_SYMBOLS             (0),
1250 
                .AV_BURSTCOUNT_SYMBOLS          (0),
1251 
                .AV_CONSTANT_BURST_BEHAVIOR     (0),
1252 
                .UAV_CONSTANT_BURST_BEHAVIOR    (0),
1253 
                .AV_REQUIRE_UNALIGNED_ADDRESSES (0),
1254 
                .CHIPSELECT_THROUGH_READLATENCY (0),
1255 
                .AV_READ_WAIT_CYCLES            (1),
1256 
                .AV_WRITE_WAIT_CYCLES           (0),
1257 
                .AV_SETUP_WAIT_CYCLES           (0),
1258 
                .AV_DATA_HOLD_CYCLES            (0)
1259 
        ) timer_0_s1_translator (
1260 
                .clk                   (clk_clk),                                                               //                      clk.clk
1261 
                .reset                 (rst_controller_reset_out_reset),                                        //                    reset.reset
1262 
                .uav_address           (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
1263 
                .uav_burstcount        (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
1264 
                .uav_read              (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
1265 
                .uav_write             (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
1266 
                .uav_waitrequest       (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
1267 
                .uav_readdatavalid     (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
1268 
                .uav_byteenable        (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
1269 
                .uav_readdata          (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
1270 
                .uav_writedata         (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
1271 
                .uav_lock              (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
1272 
                .uav_debugaccess       (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
1273 
                .av_address            (timer_0_s1_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
1274 
                .av_write              (timer_0_s1_translator_avalon_anti_slave_0_write),                       //                         .write
1275 
                .av_readdata           (timer_0_s1_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
1276 
                .av_writedata          (timer_0_s1_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
1277 
                .av_chipselect         (timer_0_s1_translator_avalon_anti_slave_0_chipselect),                  //                         .chipselect
1278 
                .av_read               (),                                                                      //              (terminated)
1279 
                .av_begintransfer      (),                                                                      //              (terminated)
1280 
                .av_beginbursttransfer (),                                                                      //              (terminated)
1281 
                .av_burstcount         (),                                                                      //              (terminated)
1282 
                .av_byteenable         (),                                                                      //              (terminated)
1283 
                .av_readdatavalid      (1'b0),                                                                  //              (terminated)
1284 
                .av_waitrequest        (1'b0),                                                                  //              (terminated)
1285 
                .av_writebyteenable    (),                                                                      //              (terminated)
1286 
                .av_lock               (),                                                                      //              (terminated)
1287 
                .av_clken              (),                                                                      //              (terminated)
1288 
                .uav_clken             (1'b0),                                                                  //              (terminated)
1289 
                .av_debugaccess        (),                                                                      //              (terminated)
1290 
                .av_outputenable       ()                                                                       //              (terminated)
1291 
        );
1292 
 
1293 
        altera_merlin_slave_translator #(
1294 
                .AV_ADDRESS_W                   (1),
1295 
                .AV_DATA_W                      (32),
1296 
                .UAV_DATA_W                     (32),
1297 
                .AV_BURSTCOUNT_W                (1),
1298 
                .AV_BYTEENABLE_W                (4),
1299 
                .UAV_BYTEENABLE_W               (4),
1300 
                .UAV_ADDRESS_W                  (26),
1301 
                .UAV_BURSTCOUNT_W               (3),
1302 
                .AV_READLATENCY                 (0),
1303 
                .USE_READDATAVALID              (0),
1304 
                .USE_WAITREQUEST                (0),
1305 
                .USE_UAV_CLKEN                  (0),
1306 
                .AV_SYMBOLS_PER_WORD            (4),
1307 
                .AV_ADDRESS_SYMBOLS             (0),
1308 
                .AV_BURSTCOUNT_SYMBOLS          (0),
1309 
                .AV_CONSTANT_BURST_BEHAVIOR     (0),
1310 
                .UAV_CONSTANT_BURST_BEHAVIOR    (0),
1311 
                .AV_REQUIRE_UNALIGNED_ADDRESSES (0),
1312 
                .CHIPSELECT_THROUGH_READLATENCY (0),
1313 
                .AV_READ_WAIT_CYCLES            (1),
1314 
                .AV_WRITE_WAIT_CYCLES           (0),
1315 
                .AV_SETUP_WAIT_CYCLES           (0),
1316 
                .AV_DATA_HOLD_CYCLES            (0)
1317 
        ) sysid_qsys_1_control_slave_translator (
1318 
                .clk                   (clk_clk),                                                                               //                      clk.clk
1319 
                .reset                 (rst_controller_reset_out_reset),                                                        //                    reset.reset
1320 
                .uav_address           (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
1321 
                .uav_burstcount        (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
1322 
                .uav_read              (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
1323 
                .uav_write             (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
1324 
                .uav_waitrequest       (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
1325 
                .uav_readdatavalid     (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
1326 
                .uav_byteenable        (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
1327 
                .uav_readdata          (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
1328 
                .uav_writedata         (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
1329 
                .uav_lock              (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
1330 
                .uav_debugaccess       (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
1331 
                .av_address            (sysid_qsys_1_control_slave_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
1332 
                .av_readdata           (sysid_qsys_1_control_slave_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
1333 
                .av_write              (),                                                                                      //              (terminated)
1334 
                .av_read               (),                                                                                      //              (terminated)
1335 
                .av_writedata          (),                                                                                      //              (terminated)
1336 
                .av_begintransfer      (),                                                                                      //              (terminated)
1337 
                .av_beginbursttransfer (),                                                                                      //              (terminated)
1338 
                .av_burstcount         (),                                                                                      //              (terminated)
1339 
                .av_byteenable         (),                                                                                      //              (terminated)
1340 
                .av_readdatavalid      (1'b0),                                                                                  //              (terminated)
1341 
                .av_waitrequest        (1'b0),                                                                                  //              (terminated)
1342 
                .av_writebyteenable    (),                                                                                      //              (terminated)
1343 
                .av_lock               (),                                                                                      //              (terminated)
1344 
                .av_chipselect         (),                                                                                      //              (terminated)
1345 
                .av_clken              (),                                                                                      //              (terminated)
1346 
                .uav_clken             (1'b0),                                                                                  //              (terminated)
1347 
                .av_debugaccess        (),                                                                                      //              (terminated)
1348 
                .av_outputenable       ()                                                                                       //              (terminated)
1349 
        );
1350 
 
1351 
        altera_merlin_slave_translator #(
1352 
                .AV_ADDRESS_W                   (11),
1353 
                .AV_DATA_W                      (32),
1354 
                .UAV_DATA_W                     (32),
1355 
                .AV_BURSTCOUNT_W                (1),
1356 
                .AV_BYTEENABLE_W                (4),
1357 
                .UAV_BYTEENABLE_W               (4),
1358 
                .UAV_ADDRESS_W                  (26),
1359 
                .UAV_BURSTCOUNT_W               (3),
1360 
                .AV_READLATENCY                 (1),
1361 
                .USE_READDATAVALID              (0),
1362 
                .USE_WAITREQUEST                (0),
1363 
                .USE_UAV_CLKEN                  (0),
1364 
                .AV_SYMBOLS_PER_WORD            (4),
1365 
                .AV_ADDRESS_SYMBOLS             (0),
1366 
                .AV_BURSTCOUNT_SYMBOLS          (0),
1367 
                .AV_CONSTANT_BURST_BEHAVIOR     (0),
1368 
                .UAV_CONSTANT_BURST_BEHAVIOR    (0),
1369 
                .AV_REQUIRE_UNALIGNED_ADDRESSES (0),
1370 
                .CHIPSELECT_THROUGH_READLATENCY (0),
1371 
                .AV_READ_WAIT_CYCLES            (0),
1372 
                .AV_WRITE_WAIT_CYCLES           (0),
1373 
                .AV_SETUP_WAIT_CYCLES           (0),
1374 
                .AV_DATA_HOLD_CYCLES            (0)
1375 
        ) onchip_memory2_1_s1_translator (
1376 
                .clk                   (clk_clk),                                                                        //                      clk.clk
1377 
                .reset                 (rst_controller_reset_out_reset),                                                 //                    reset.reset
1378 
                .uav_address           (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
1379 
                .uav_burstcount        (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
1380 
                .uav_read              (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
1381 
                .uav_write             (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
1382 
                .uav_waitrequest       (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
1383 
                .uav_readdatavalid     (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
1384 
                .uav_byteenable        (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
1385 
                .uav_readdata          (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
1386 
                .uav_writedata         (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
1387 
                .uav_lock              (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
1388 
                .uav_debugaccess       (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
1389 
                .av_address            (onchip_memory2_1_s1_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
1390 
                .av_write              (onchip_memory2_1_s1_translator_avalon_anti_slave_0_write),                       //                         .write
1391 
                .av_readdata           (onchip_memory2_1_s1_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
1392 
                .av_writedata          (onchip_memory2_1_s1_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
1393 
                .av_byteenable         (onchip_memory2_1_s1_translator_avalon_anti_slave_0_byteenable),                  //                         .byteenable
1394 
                .av_chipselect         (onchip_memory2_1_s1_translator_avalon_anti_slave_0_chipselect),                  //                         .chipselect
1395 
                .av_clken              (onchip_memory2_1_s1_translator_avalon_anti_slave_0_clken),                       //                         .clken
1396 
                .av_read               (),                                                                               //              (terminated)
1397 
                .av_begintransfer      (),                                                                               //              (terminated)
1398 
                .av_beginbursttransfer (),                                                                               //              (terminated)
1399 
                .av_burstcount         (),                                                                               //              (terminated)
1400 
                .av_readdatavalid      (1'b0),                                                                           //              (terminated)
1401 
                .av_waitrequest        (1'b0),                                                                           //              (terminated)
1402 
                .av_writebyteenable    (),                                                                               //              (terminated)
1403 
                .av_lock               (),                                                                               //              (terminated)
1404 
                .uav_clken             (1'b0),                                                                           //              (terminated)
1405 
                .av_debugaccess        (),                                                                               //              (terminated)
1406 
                .av_outputenable       ()                                                                                //              (terminated)
1407 
        );
1408 
 
1409 
        altera_merlin_slave_translator #(
1410 
                .AV_ADDRESS_W                   (7),
1411 
                .AV_DATA_W                      (32),
1412 
                .UAV_DATA_W                     (32),
1413 
                .AV_BURSTCOUNT_W                (1),
1414 
                .AV_BYTEENABLE_W                (4),
1415 
                .UAV_BYTEENABLE_W               (4),
1416 
                .UAV_ADDRESS_W                  (26),
1417 
                .UAV_BURSTCOUNT_W               (3),
1418 
                .AV_READLATENCY                 (0),
1419 
                .USE_READDATAVALID              (0),
1420 
                .USE_WAITREQUEST                (1),
1421 
                .USE_UAV_CLKEN                  (0),
1422 
                .AV_SYMBOLS_PER_WORD            (4),
1423 
                .AV_ADDRESS_SYMBOLS             (0),
1424 
                .AV_BURSTCOUNT_SYMBOLS          (0),
1425 
                .AV_CONSTANT_BURST_BEHAVIOR     (0),
1426 
                .UAV_CONSTANT_BURST_BEHAVIOR    (0),
1427 
                .AV_REQUIRE_UNALIGNED_ADDRESSES (0),
1428 
                .CHIPSELECT_THROUGH_READLATENCY (0),
1429 
                .AV_READ_WAIT_CYCLES            (1),
1430 
                .AV_WRITE_WAIT_CYCLES           (0),
1431 
                .AV_SETUP_WAIT_CYCLES           (0),
1432 
                .AV_DATA_HOLD_CYCLES            (0)
1433 
        ) hibi_pe_dma_0_avalon_slave_0_translator (
1434 
                .clk                   (clk_clk),                                                                                 //                      clk.clk
1435 
                .reset                 (rst_controller_reset_out_reset),                                                          //                    reset.reset
1436 
                .uav_address           (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
1437 
                .uav_burstcount        (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
1438 
                .uav_read              (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
1439 
                .uav_write             (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
1440 
                .uav_waitrequest       (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
1441 
                .uav_readdatavalid     (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
1442 
                .uav_byteenable        (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
1443 
                .uav_readdata          (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
1444 
                .uav_writedata         (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
1445 
                .uav_lock              (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
1446 
                .uav_debugaccess       (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
1447 
                .av_address            (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
1448 
                .av_write              (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_write),                       //                         .write
1449 
                .av_read               (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_read),                        //                         .read
1450 
                .av_readdata           (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
1451 
                .av_writedata          (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
1452 
                .av_waitrequest        (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest),                 //                         .waitrequest
1453 
                .av_chipselect         (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_chipselect),                  //                         .chipselect
1454 
                .av_begintransfer      (),                                                                                        //              (terminated)
1455 
                .av_beginbursttransfer (),                                                                                        //              (terminated)
1456 
                .av_burstcount         (),                                                                                        //              (terminated)
1457 
                .av_byteenable         (),                                                                                        //              (terminated)
1458 
                .av_readdatavalid      (1'b0),                                                                                    //              (terminated)
1459 
                .av_writebyteenable    (),                                                                                        //              (terminated)
1460 
                .av_lock               (),                                                                                        //              (terminated)
1461 
                .av_clken              (),                                                                                        //              (terminated)
1462 
                .uav_clken             (1'b0),                                                                                    //              (terminated)
1463 
                .av_debugaccess        (),                                                                                        //              (terminated)
1464 
                .av_outputenable       ()                                                                                         //              (terminated)
1465 
        );
1466 
 
1467 
        altera_merlin_master_translator #(
1468 
                .AV_ADDRESS_W                (32),
1469 
                .AV_DATA_W                   (32),
1470 
                .AV_BURSTCOUNT_W             (1),
1471 
                .AV_BYTEENABLE_W             (4),
1472 
                .UAV_ADDRESS_W               (32),
1473 
                .UAV_BURSTCOUNT_W            (3),
1474 
                .USE_READ                    (0),
1475 
                .USE_WRITE                   (1),
1476 
                .USE_BEGINBURSTTRANSFER      (0),
1477 
                .USE_BEGINTRANSFER           (0),
1478 
                .USE_CHIPSELECT              (0),
1479 
                .USE_BURSTCOUNT              (0),
1480 
                .USE_READDATAVALID           (0),
1481 
                .USE_WAITREQUEST             (1),
1482 
                .AV_SYMBOLS_PER_WORD         (4),
1483 
                .AV_ADDRESS_SYMBOLS          (1),
1484 
                .AV_BURSTCOUNT_SYMBOLS       (0),
1485 
                .AV_CONSTANT_BURST_BEHAVIOR  (0),
1486 
                .UAV_CONSTANT_BURST_BEHAVIOR (0),
1487 
                .AV_LINEWRAPBURSTS           (0),
1488 
                .AV_REGISTERINCOMINGSIGNALS  (0)
1489 
        ) hibi_pe_dma_0_avalon_master_translator (
1490 
                .clk                   (clk_clk),                                                                        //                       clk.clk
1491 
                .reset                 (rst_controller_reset_out_reset),                                                 //                     reset.reset
1492 
                .uav_address           (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
1493 
                .uav_burstcount        (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
1494 
                .uav_read              (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_read),          //                          .read
1495 
                .uav_write             (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_write),         //                          .write
1496 
                .uav_waitrequest       (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
1497 
                .uav_readdatavalid     (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
1498 
                .uav_byteenable        (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
1499 
                .uav_readdata          (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
1500 
                .uav_writedata         (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
1501 
                .uav_lock              (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_lock),          //                          .lock
1502 
                .uav_debugaccess       (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
1503 
                .av_address            (hibi_pe_dma_0_avalon_master_address),                                            //      avalon_anti_master_0.address
1504 
                .av_waitrequest        (hibi_pe_dma_0_avalon_master_waitrequest),                                        //                          .waitrequest
1505 
                .av_byteenable         (hibi_pe_dma_0_avalon_master_byteenable),                                         //                          .byteenable
1506 
                .av_write              (hibi_pe_dma_0_avalon_master_write),                                              //                          .write
1507 
                .av_writedata          (hibi_pe_dma_0_avalon_master_writedata),                                          //                          .writedata
1508 
                .av_burstcount         (1'b1),                                                                           //               (terminated)
1509 
                .av_beginbursttransfer (1'b0),                                                                           //               (terminated)
1510 
                .av_begintransfer      (1'b0),                                                                           //               (terminated)
1511 
                .av_chipselect         (1'b0),                                                                           //               (terminated)
1512 
                .av_read               (1'b0),                                                                           //               (terminated)
1513 
                .av_readdata           (),                                                                               //               (terminated)
1514 
                .av_readdatavalid      (),                                                                               //               (terminated)
1515 
                .av_lock               (1'b0),                                                                           //               (terminated)
1516 
                .av_debugaccess        (1'b0),                                                                           //               (terminated)
1517 
                .uav_clken             (),                                                                               //               (terminated)
1518 
                .av_clken              (1'b1)                                                                            //               (terminated)
1519 
        );
1520 
 
1521 
        altera_merlin_master_translator #(
1522 
                .AV_ADDRESS_W                (32),
1523 
                .AV_DATA_W                   (32),
1524 
                .AV_BURSTCOUNT_W             (1),
1525 
                .AV_BYTEENABLE_W             (4),
1526 
                .UAV_ADDRESS_W               (32),
1527 
                .UAV_BURSTCOUNT_W            (3),
1528 
                .USE_READ                    (1),
1529 
                .USE_WRITE                   (0),
1530 
                .USE_BEGINBURSTTRANSFER      (0),
1531 
                .USE_BEGINTRANSFER           (0),
1532 
                .USE_CHIPSELECT              (0),
1533 
                .USE_BURSTCOUNT              (0),
1534 
                .USE_READDATAVALID           (1),
1535 
                .USE_WAITREQUEST             (1),
1536 
                .AV_SYMBOLS_PER_WORD         (4),
1537 
                .AV_ADDRESS_SYMBOLS          (1),
1538 
                .AV_BURSTCOUNT_SYMBOLS       (0),
1539 
                .AV_CONSTANT_BURST_BEHAVIOR  (0),
1540 
                .UAV_CONSTANT_BURST_BEHAVIOR (0),
1541 
                .AV_LINEWRAPBURSTS           (0),
1542 
                .AV_REGISTERINCOMINGSIGNALS  (0)
1543 
        ) hibi_pe_dma_0_avalon_master_1_translator (
1544 
                .clk                   (clk_clk),                                                                          //                       clk.clk
1545 
                .reset                 (rst_controller_reset_out_reset),                                                   //                     reset.reset
1546 
                .uav_address           (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
1547 
                .uav_burstcount        (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
1548 
                .uav_read              (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_read),          //                          .read
1549 
                .uav_write             (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_write),         //                          .write
1550 
                .uav_waitrequest       (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
1551 
                .uav_readdatavalid     (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
1552 
                .uav_byteenable        (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
1553 
                .uav_readdata          (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_readdata),      //                          .readdata
1554 
                .uav_writedata         (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_writedata),     //                          .writedata
1555 
                .uav_lock              (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_lock),          //                          .lock
1556 
                .uav_debugaccess       (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
1557 
                .av_address            (hibi_pe_dma_0_avalon_master_1_address),                                            //      avalon_anti_master_0.address
1558 
                .av_waitrequest        (hibi_pe_dma_0_avalon_master_1_waitrequest),                                        //                          .waitrequest
1559 
                .av_read               (hibi_pe_dma_0_avalon_master_1_read),                                               //                          .read
1560 
                .av_readdata           (hibi_pe_dma_0_avalon_master_1_readdata),                                           //                          .readdata
1561 
                .av_readdatavalid      (hibi_pe_dma_0_avalon_master_1_readdatavalid),                                      //                          .readdatavalid
1562 
                .av_burstcount         (1'b1),                                                                             //               (terminated)
1563 
                .av_byteenable         (4'b1111),                                                                          //               (terminated)
1564 
                .av_beginbursttransfer (1'b0),                                                                             //               (terminated)
1565 
                .av_begintransfer      (1'b0),                                                                             //               (terminated)
1566 
                .av_chipselect         (1'b0),                                                                             //               (terminated)
1567 
                .av_write              (1'b0),                                                                             //               (terminated)
1568 
                .av_writedata          (32'b00000000000000000000000000000000),                                             //               (terminated)
1569 
                .av_lock               (1'b0),                                                                             //               (terminated)
1570 
                .av_debugaccess        (1'b0),                                                                             //               (terminated)
1571 
                .uav_clken             (),                                                                                 //               (terminated)
1572 
                .av_clken              (1'b1)                                                                              //               (terminated)
1573 
        );
1574 
 
1575 
        altera_merlin_slave_translator #(
1576 
                .AV_ADDRESS_W                   (11),
1577 
                .AV_DATA_W                      (32),
1578 
                .UAV_DATA_W                     (32),
1579 
                .AV_BURSTCOUNT_W                (1),
1580 
                .AV_BYTEENABLE_W                (4),
1581 
                .UAV_BYTEENABLE_W               (4),
1582 
                .UAV_ADDRESS_W                  (32),
1583 
                .UAV_BURSTCOUNT_W               (3),
1584 
                .AV_READLATENCY                 (1),
1585 
                .USE_READDATAVALID              (0),
1586 
                .USE_WAITREQUEST                (0),
1587 
                .USE_UAV_CLKEN                  (0),
1588 
                .AV_SYMBOLS_PER_WORD            (4),
1589 
                .AV_ADDRESS_SYMBOLS             (0),
1590 
                .AV_BURSTCOUNT_SYMBOLS          (0),
1591 
                .AV_CONSTANT_BURST_BEHAVIOR     (0),
1592 
                .UAV_CONSTANT_BURST_BEHAVIOR    (0),
1593 
                .AV_REQUIRE_UNALIGNED_ADDRESSES (0),
1594 
                .CHIPSELECT_THROUGH_READLATENCY (0),
1595 
                .AV_READ_WAIT_CYCLES            (0),
1596 
                .AV_WRITE_WAIT_CYCLES           (0),
1597 
                .AV_SETUP_WAIT_CYCLES           (0),
1598 
                .AV_DATA_HOLD_CYCLES            (0)
1599 
        ) onchip_memory2_1_s2_translator (
1600 
                .clk                   (clk_clk),                                                                        //                      clk.clk
1601 
                .reset                 (rst_controller_reset_out_reset),                                                 //                    reset.reset
1602 
                .uav_address           (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
1603 
                .uav_burstcount        (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
1604 
                .uav_read              (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
1605 
                .uav_write             (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
1606 
                .uav_waitrequest       (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
1607 
                .uav_readdatavalid     (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
1608 
                .uav_byteenable        (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
1609 
                .uav_readdata          (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
1610 
                .uav_writedata         (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
1611 
                .uav_lock              (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
1612 
                .uav_debugaccess       (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
1613 
                .av_address            (onchip_memory2_1_s2_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
1614 
                .av_write              (onchip_memory2_1_s2_translator_avalon_anti_slave_0_write),                       //                         .write
1615 
                .av_readdata           (onchip_memory2_1_s2_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
1616 
                .av_writedata          (onchip_memory2_1_s2_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
1617 
                .av_byteenable         (onchip_memory2_1_s2_translator_avalon_anti_slave_0_byteenable),                  //                         .byteenable
1618 
                .av_chipselect         (onchip_memory2_1_s2_translator_avalon_anti_slave_0_chipselect),                  //                         .chipselect
1619 
                .av_clken              (onchip_memory2_1_s2_translator_avalon_anti_slave_0_clken),                       //                         .clken
1620 
                .av_read               (),                                                                               //              (terminated)
1621 
                .av_begintransfer      (),                                                                               //              (terminated)
1622 
                .av_beginbursttransfer (),                                                                               //              (terminated)
1623 
                .av_burstcount         (),                                                                               //              (terminated)
1624 
                .av_readdatavalid      (1'b0),                                                                           //              (terminated)
1625 
                .av_waitrequest        (1'b0),                                                                           //              (terminated)
1626 
                .av_writebyteenable    (),                                                                               //              (terminated)
1627 
                .av_lock               (),                                                                               //              (terminated)
1628 
                .uav_clken             (1'b0),                                                                           //              (terminated)
1629 
                .av_debugaccess        (),                                                                               //              (terminated)
1630 
                .av_outputenable       ()                                                                                //              (terminated)
1631 
        );
1632 
 
1633 
        altera_merlin_master_agent #(
1634 
                .PKT_PROTECTION_H          (92),
1635 
                .PKT_PROTECTION_L          (90),
1636 
                .PKT_BEGIN_BURST           (81),
1637 
                .PKT_BURSTWRAP_H           (73),
1638 
                .PKT_BURSTWRAP_L           (71),
1639 
                .PKT_BURST_SIZE_H          (76),
1640 
                .PKT_BURST_SIZE_L          (74),
1641 
                .PKT_BURST_TYPE_H          (78),
1642 
                .PKT_BURST_TYPE_L          (77),
1643 
                .PKT_BYTE_CNT_H            (70),
1644 
                .PKT_BYTE_CNT_L            (68),
1645 
                .PKT_ADDR_H                (61),
1646 
                .PKT_ADDR_L                (36),
1647 
                .PKT_TRANS_COMPRESSED_READ (62),
1648 
                .PKT_TRANS_POSTED          (63),
1649 
                .PKT_TRANS_WRITE           (64),
1650 
                .PKT_TRANS_READ            (65),
1651 
                .PKT_TRANS_LOCK            (66),
1652 
                .PKT_TRANS_EXCLUSIVE       (67),
1653 
                .PKT_DATA_H                (31),
1654 
                .PKT_DATA_L                (0),
1655 
                .PKT_BYTEEN_H              (35),
1656 
                .PKT_BYTEEN_L              (32),
1657 
                .PKT_SRC_ID_H              (85),
1658 
                .PKT_SRC_ID_L              (83),
1659 
                .PKT_DEST_ID_H             (88),
1660 
                .PKT_DEST_ID_L             (86),
1661 
                .PKT_THREAD_ID_H           (89),
1662 
                .PKT_THREAD_ID_L           (89),
1663 
                .PKT_CACHE_H               (96),
1664 
                .PKT_CACHE_L               (93),
1665 
                .PKT_DATA_SIDEBAND_H       (80),
1666 
                .PKT_DATA_SIDEBAND_L       (80),
1667 
                .PKT_QOS_H                 (82),
1668 
                .PKT_QOS_L                 (82),
1669 
                .PKT_ADDR_SIDEBAND_H       (79),
1670 
                .PKT_ADDR_SIDEBAND_L       (79),
1671 
                .ST_DATA_W                 (99),
1672 
                .ST_CHANNEL_W              (8),
1673 
                .AV_BURSTCOUNT_W           (3),
1674 
                .SUPPRESS_0_BYTEEN_RSP     (0),
1675 
                .ID                        (0),
1676 
                .BURSTWRAP_VALUE           (3),
1677 
                .CACHE_VALUE               (4'b0000)
1678 
        ) nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent (
1679 
                .clk              (clk_clk),                                                                                     //       clk.clk
1680 
                .reset            (rst_controller_reset_out_reset),                                                              // clk_reset.reset
1681 
                .av_address       (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_address),                //        av.address
1682 
                .av_write         (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_write),                  //          .write
1683 
                .av_read          (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_read),                   //          .read
1684 
                .av_writedata     (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_writedata),              //          .writedata
1685 
                .av_readdata      (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_readdata),               //          .readdata
1686 
                .av_waitrequest   (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_waitrequest),            //          .waitrequest
1687 
                .av_readdatavalid (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_readdatavalid),          //          .readdatavalid
1688 
                .av_byteenable    (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_byteenable),             //          .byteenable
1689 
                .av_burstcount    (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_burstcount),             //          .burstcount
1690 
                .av_debugaccess   (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_debugaccess),            //          .debugaccess
1691 
                .av_lock          (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_lock),                   //          .lock
1692 
                .cp_valid         (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_valid),         //        cp.valid
1693 
                .cp_data          (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_data),          //          .data
1694 
                .cp_startofpacket (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
1695 
                .cp_endofpacket   (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
1696 
                .cp_ready         (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_ready),         //          .ready
1697 
                .rp_valid         (limiter_rsp_src_valid),                                                                       //        rp.valid
1698 
                .rp_data          (limiter_rsp_src_data),                                                                        //          .data
1699 
                .rp_channel       (limiter_rsp_src_channel),                                                                     //          .channel
1700 
                .rp_startofpacket (limiter_rsp_src_startofpacket),                                                               //          .startofpacket
1701 
                .rp_endofpacket   (limiter_rsp_src_endofpacket),                                                                 //          .endofpacket
1702 
                .rp_ready         (limiter_rsp_src_ready)                                                                        //          .ready
1703 
        );
1704 
 
1705 
        altera_merlin_master_agent #(
1706 
                .PKT_PROTECTION_H          (92),
1707 
                .PKT_PROTECTION_L          (90),
1708 
                .PKT_BEGIN_BURST           (81),
1709 
                .PKT_BURSTWRAP_H           (73),
1710 
                .PKT_BURSTWRAP_L           (71),
1711 
                .PKT_BURST_SIZE_H          (76),
1712 
                .PKT_BURST_SIZE_L          (74),
1713 
                .PKT_BURST_TYPE_H          (78),
1714 
                .PKT_BURST_TYPE_L          (77),
1715 
                .PKT_BYTE_CNT_H            (70),
1716 
                .PKT_BYTE_CNT_L            (68),
1717 
                .PKT_ADDR_H                (61),
1718 
                .PKT_ADDR_L                (36),
1719 
                .PKT_TRANS_COMPRESSED_READ (62),
1720 
                .PKT_TRANS_POSTED          (63),
1721 
                .PKT_TRANS_WRITE           (64),
1722 
                .PKT_TRANS_READ            (65),
1723 
                .PKT_TRANS_LOCK            (66),
1724 
                .PKT_TRANS_EXCLUSIVE       (67),
1725 
                .PKT_DATA_H                (31),
1726 
                .PKT_DATA_L                (0),
1727 
                .PKT_BYTEEN_H              (35),
1728 
                .PKT_BYTEEN_L              (32),
1729 
                .PKT_SRC_ID_H              (85),
1730 
                .PKT_SRC_ID_L              (83),
1731 
                .PKT_DEST_ID_H             (88),
1732 
                .PKT_DEST_ID_L             (86),
1733 
                .PKT_THREAD_ID_H           (89),
1734 
                .PKT_THREAD_ID_L           (89),
1735 
                .PKT_CACHE_H               (96),
1736 
                .PKT_CACHE_L               (93),
1737 
                .PKT_DATA_SIDEBAND_H       (80),
1738 
                .PKT_DATA_SIDEBAND_L       (80),
1739 
                .PKT_QOS_H                 (82),
1740 
                .PKT_QOS_L                 (82),
1741 
                .PKT_ADDR_SIDEBAND_H       (79),
1742 
                .PKT_ADDR_SIDEBAND_L       (79),
1743 
                .ST_DATA_W                 (99),
1744 
                .ST_CHANNEL_W              (8),
1745 
                .AV_BURSTCOUNT_W           (3),
1746 
                .SUPPRESS_0_BYTEEN_RSP     (0),
1747 
                .ID                        (1),
1748 
                .BURSTWRAP_VALUE           (7),
1749 
                .CACHE_VALUE               (4'b0000)
1750 
        ) nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent (
1751 
                .clk              (clk_clk),                                                                              //       clk.clk
1752 
                .reset            (rst_controller_reset_out_reset),                                                       // clk_reset.reset
1753 
                .av_address       (nios2_qsys_1_data_master_translator_avalon_universal_master_0_address),                //        av.address
1754 
                .av_write         (nios2_qsys_1_data_master_translator_avalon_universal_master_0_write),                  //          .write
1755 
                .av_read          (nios2_qsys_1_data_master_translator_avalon_universal_master_0_read),                   //          .read
1756 
                .av_writedata     (nios2_qsys_1_data_master_translator_avalon_universal_master_0_writedata),              //          .writedata
1757 
                .av_readdata      (nios2_qsys_1_data_master_translator_avalon_universal_master_0_readdata),               //          .readdata
1758 
                .av_waitrequest   (nios2_qsys_1_data_master_translator_avalon_universal_master_0_waitrequest),            //          .waitrequest
1759 
                .av_readdatavalid (nios2_qsys_1_data_master_translator_avalon_universal_master_0_readdatavalid),          //          .readdatavalid
1760 
                .av_byteenable    (nios2_qsys_1_data_master_translator_avalon_universal_master_0_byteenable),             //          .byteenable
1761 
                .av_burstcount    (nios2_qsys_1_data_master_translator_avalon_universal_master_0_burstcount),             //          .burstcount
1762 
                .av_debugaccess   (nios2_qsys_1_data_master_translator_avalon_universal_master_0_debugaccess),            //          .debugaccess
1763 
                .av_lock          (nios2_qsys_1_data_master_translator_avalon_universal_master_0_lock),                   //          .lock
1764 
                .cp_valid         (nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_valid),         //        cp.valid
1765 
                .cp_data          (nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_data),          //          .data
1766 
                .cp_startofpacket (nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
1767 
                .cp_endofpacket   (nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
1768 
                .cp_ready         (nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_ready),         //          .ready
1769 
                .rp_valid         (limiter_001_rsp_src_valid),                                                            //        rp.valid
1770 
                .rp_data          (limiter_001_rsp_src_data),                                                             //          .data
1771 
                .rp_channel       (limiter_001_rsp_src_channel),                                                          //          .channel
1772 
                .rp_startofpacket (limiter_001_rsp_src_startofpacket),                                                    //          .startofpacket
1773 
                .rp_endofpacket   (limiter_001_rsp_src_endofpacket),                                                      //          .endofpacket
1774 
                .rp_ready         (limiter_001_rsp_src_ready)                                                             //          .ready
1775 
        );
1776 
 
1777 
        altera_merlin_slave_agent #(
1778 
                .PKT_DATA_H                (31),
1779 
                .PKT_DATA_L                (0),
1780 
                .PKT_BEGIN_BURST           (81),
1781 
                .PKT_SYMBOL_W              (8),
1782 
                .PKT_BYTEEN_H              (35),
1783 
                .PKT_BYTEEN_L              (32),
1784 
                .PKT_ADDR_H                (61),
1785 
                .PKT_ADDR_L                (36),
1786 
                .PKT_TRANS_COMPRESSED_READ (62),
1787 
                .PKT_TRANS_POSTED          (63),
1788 
                .PKT_TRANS_WRITE           (64),
1789 
                .PKT_TRANS_READ            (65),
1790 
                .PKT_TRANS_LOCK            (66),
1791 
                .PKT_SRC_ID_H              (85),
1792 
                .PKT_SRC_ID_L              (83),
1793 
                .PKT_DEST_ID_H             (88),
1794 
                .PKT_DEST_ID_L             (86),
1795 
                .PKT_BURSTWRAP_H           (73),
1796 
                .PKT_BURSTWRAP_L           (71),
1797 
                .PKT_BYTE_CNT_H            (70),
1798 
                .PKT_BYTE_CNT_L            (68),
1799 
                .PKT_PROTECTION_H          (92),
1800 
                .PKT_PROTECTION_L          (90),
1801 
                .PKT_RESPONSE_STATUS_H     (98),
1802 
                .PKT_RESPONSE_STATUS_L     (97),
1803 
                .PKT_BURST_SIZE_H          (76),
1804 
                .PKT_BURST_SIZE_L          (74),
1805 
                .ST_CHANNEL_W              (8),
1806 
                .ST_DATA_W                 (99),
1807 
                .AVS_BURSTCOUNT_W          (3),
1808 
                .SUPPRESS_0_BYTEEN_CMD     (0),
1809 
                .PREVENT_FIFO_OVERFLOW     (1)
1810 
        ) nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent (
1811 
                .clk                     (clk_clk),                                                                                             //             clk.clk
1812 
                .reset                   (rst_controller_reset_out_reset),                                                                      //       clk_reset.reset
1813 
                .m0_address              (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
1814 
                .m0_burstcount           (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
1815 
                .m0_byteenable           (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
1816 
                .m0_debugaccess          (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
1817 
                .m0_lock                 (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
1818 
                .m0_readdata             (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
1819 
                .m0_readdatavalid        (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
1820 
                .m0_read                 (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
1821 
                .m0_waitrequest          (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
1822 
                .m0_writedata            (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
1823 
                .m0_write                (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
1824 
                .rp_endofpacket          (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
1825 
                .rp_ready                (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
1826 
                .rp_valid                (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
1827 
                .rp_data                 (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
1828 
                .rp_startofpacket        (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
1829 
                .cp_ready                (cmd_xbar_mux_src_ready),                                                                              //              cp.ready
1830 
                .cp_valid                (cmd_xbar_mux_src_valid),                                                                              //                .valid
1831 
                .cp_data                 (cmd_xbar_mux_src_data),                                                                               //                .data
1832 
                .cp_startofpacket        (cmd_xbar_mux_src_startofpacket),                                                                      //                .startofpacket
1833 
                .cp_endofpacket          (cmd_xbar_mux_src_endofpacket),                                                                        //                .endofpacket
1834 
                .cp_channel              (cmd_xbar_mux_src_channel),                                                                            //                .channel
1835 
                .rf_sink_ready           (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
1836 
                .rf_sink_valid           (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
1837 
                .rf_sink_startofpacket   (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
1838 
                .rf_sink_endofpacket     (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
1839 
                .rf_sink_data            (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
1840 
                .rf_source_ready         (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
1841 
                .rf_source_valid         (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
1842 
                .rf_source_startofpacket (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
1843 
                .rf_source_endofpacket   (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
1844 
                .rf_source_data          (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
1845 
                .rdata_fifo_sink_ready   (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
1846 
                .rdata_fifo_sink_valid   (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
1847 
                .rdata_fifo_sink_data    (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
1848 
                .rdata_fifo_src_ready    (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
1849 
                .rdata_fifo_src_valid    (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
1850 
                .rdata_fifo_src_data     (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
1851 
        );
1852 
 
1853 
        altera_avalon_sc_fifo #(
1854 
                .SYMBOLS_PER_BEAT    (1),
1855 
                .BITS_PER_SYMBOL     (100),
1856 
                .FIFO_DEPTH          (2),
1857 
                .CHANNEL_WIDTH       (0),
1858 
                .ERROR_WIDTH         (0),
1859 
                .USE_PACKETS         (1),
1860 
                .USE_FILL_LEVEL      (0),
1861 
                .EMPTY_LATENCY       (1),
1862 
                .USE_MEMORY_BLOCKS   (0),
1863 
                .USE_STORE_FORWARD   (0),
1864 
                .USE_ALMOST_FULL_IF  (0),
1865 
                .USE_ALMOST_EMPTY_IF (0)
1866 
        ) nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo (
1867 
                .clk               (clk_clk),                                                                                             //       clk.clk
1868 
                .reset             (rst_controller_reset_out_reset),                                                                      // clk_reset.reset
1869 
                .in_data           (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
1870 
                .in_valid          (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
1871 
                .in_ready          (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
1872 
                .in_startofpacket  (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
1873 
                .in_endofpacket    (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
1874 
                .out_data          (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
1875 
                .out_valid         (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
1876 
                .out_ready         (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
1877 
                .out_startofpacket (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
1878 
                .out_endofpacket   (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
1879 
                .csr_address       (2'b00),                                                                                               // (terminated)
1880 
                .csr_read          (1'b0),                                                                                                // (terminated)
1881 
                .csr_write         (1'b0),                                                                                                // (terminated)
1882 
                .csr_readdata      (),                                                                                                    // (terminated)
1883 
                .csr_writedata     (32'b00000000000000000000000000000000),                                                                // (terminated)
1884 
                .almost_full_data  (),                                                                                                    // (terminated)
1885 
                .almost_empty_data (),                                                                                                    // (terminated)
1886 
                .in_empty          (1'b0),                                                                                                // (terminated)
1887 
                .out_empty         (),                                                                                                    // (terminated)
1888 
                .in_error          (1'b0),                                                                                                // (terminated)
1889 
                .out_error         (),                                                                                                    // (terminated)
1890 
                .in_channel        (1'b0),                                                                                                // (terminated)
1891 
                .out_channel       ()                                                                                                     // (terminated)
1892 
        );
1893 
 
1894 
        altera_merlin_slave_agent #(
1895 
                .PKT_DATA_H                (15),
1896 
                .PKT_DATA_L                (0),
1897 
                .PKT_BEGIN_BURST           (63),
1898 
                .PKT_SYMBOL_W              (8),
1899 
                .PKT_BYTEEN_H              (17),
1900 
                .PKT_BYTEEN_L              (16),
1901 
                .PKT_ADDR_H                (43),
1902 
                .PKT_ADDR_L                (18),
1903 
                .PKT_TRANS_COMPRESSED_READ (44),
1904 
                .PKT_TRANS_POSTED          (45),
1905 
                .PKT_TRANS_WRITE           (46),
1906 
                .PKT_TRANS_READ            (47),
1907 
                .PKT_TRANS_LOCK            (48),
1908 
                .PKT_SRC_ID_H              (67),
1909 
                .PKT_SRC_ID_L              (65),
1910 
                .PKT_DEST_ID_H             (70),
1911 
                .PKT_DEST_ID_L             (68),
1912 
                .PKT_BURSTWRAP_H           (55),
1913 
                .PKT_BURSTWRAP_L           (53),
1914 
                .PKT_BYTE_CNT_H            (52),
1915 
                .PKT_BYTE_CNT_L            (50),
1916 
                .PKT_PROTECTION_H          (74),
1917 
                .PKT_PROTECTION_L          (72),
1918 
                .PKT_RESPONSE_STATUS_H     (80),
1919 
                .PKT_RESPONSE_STATUS_L     (79),
1920 
                .PKT_BURST_SIZE_H          (58),
1921 
                .PKT_BURST_SIZE_L          (56),
1922 
                .ST_CHANNEL_W              (8),
1923 
                .ST_DATA_W                 (81),
1924 
                .AVS_BURSTCOUNT_W          (2),
1925 
                .SUPPRESS_0_BYTEEN_CMD     (1),
1926 
                .PREVENT_FIFO_OVERFLOW     (1)
1927 
        ) sdram_0_s1_translator_avalon_universal_slave_0_agent (
1928 
                .clk                     (clk_clk),                                                                         //             clk.clk
1929 
                .reset                   (rst_controller_reset_out_reset),                                                  //       clk_reset.reset
1930 
                .m0_address              (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
1931 
                .m0_burstcount           (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
1932 
                .m0_byteenable           (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
1933 
                .m0_debugaccess          (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
1934 
                .m0_lock                 (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
1935 
                .m0_readdata             (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
1936 
                .m0_readdatavalid        (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
1937 
                .m0_read                 (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
1938 
                .m0_waitrequest          (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
1939 
                .m0_writedata            (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
1940 
                .m0_write                (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
1941 
                .rp_endofpacket          (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
1942 
                .rp_ready                (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
1943 
                .rp_valid                (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
1944 
                .rp_data                 (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
1945 
                .rp_startofpacket        (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
1946 
                .cp_ready                (burst_adapter_source0_ready),                                                     //              cp.ready
1947 
                .cp_valid                (burst_adapter_source0_valid),                                                     //                .valid
1948 
                .cp_data                 (burst_adapter_source0_data),                                                      //                .data
1949 
                .cp_startofpacket        (burst_adapter_source0_startofpacket),                                             //                .startofpacket
1950 
                .cp_endofpacket          (burst_adapter_source0_endofpacket),                                               //                .endofpacket
1951 
                .cp_channel              (burst_adapter_source0_channel),                                                   //                .channel
1952 
                .rf_sink_ready           (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
1953 
                .rf_sink_valid           (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
1954 
                .rf_sink_startofpacket   (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
1955 
                .rf_sink_endofpacket     (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
1956 
                .rf_sink_data            (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
1957 
                .rf_source_ready         (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
1958 
                .rf_source_valid         (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
1959 
                .rf_source_startofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
1960 
                .rf_source_endofpacket   (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
1961 
                .rf_source_data          (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
1962 
                .rdata_fifo_sink_ready   (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
1963 
                .rdata_fifo_sink_valid   (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
1964 
                .rdata_fifo_sink_data    (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
1965 
                .rdata_fifo_src_ready    (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
1966 
                .rdata_fifo_src_valid    (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
1967 
                .rdata_fifo_src_data     (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
1968 
        );
1969 
 
1970 
        altera_avalon_sc_fifo #(
1971 
                .SYMBOLS_PER_BEAT    (1),
1972 
                .BITS_PER_SYMBOL     (82),
1973 
                .FIFO_DEPTH          (8),
1974 
                .CHANNEL_WIDTH       (0),
1975 
                .ERROR_WIDTH         (0),
1976 
                .USE_PACKETS         (1),
1977 
                .USE_FILL_LEVEL      (0),
1978 
                .EMPTY_LATENCY       (1),
1979 
                .USE_MEMORY_BLOCKS   (0),
1980 
                .USE_STORE_FORWARD   (0),
1981 
                .USE_ALMOST_FULL_IF  (0),
1982 
                .USE_ALMOST_EMPTY_IF (0)
1983 
        ) sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
1984 
                .clk               (clk_clk),                                                                         //       clk.clk
1985 
                .reset             (rst_controller_reset_out_reset),                                                  // clk_reset.reset
1986 
                .in_data           (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
1987 
                .in_valid          (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
1988 
                .in_ready          (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
1989 
                .in_startofpacket  (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
1990 
                .in_endofpacket    (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
1991 
                .out_data          (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
1992 
                .out_valid         (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
1993 
                .out_ready         (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
1994 
                .out_startofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
1995 
                .out_endofpacket   (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
1996 
                .csr_address       (2'b00),                                                                           // (terminated)
1997 
                .csr_read          (1'b0),                                                                            // (terminated)
1998 
                .csr_write         (1'b0),                                                                            // (terminated)
1999 
                .csr_readdata      (),                                                                                // (terminated)
2000 
                .csr_writedata     (32'b00000000000000000000000000000000),                                            // (terminated)
2001 
                .almost_full_data  (),                                                                                // (terminated)
2002 
                .almost_empty_data (),                                                                                // (terminated)
2003 
                .in_empty          (1'b0),                                                                            // (terminated)
2004 
                .out_empty         (),                                                                                // (terminated)
2005 
                .in_error          (1'b0),                                                                            // (terminated)
2006 
                .out_error         (),                                                                                // (terminated)
2007 
                .in_channel        (1'b0),                                                                            // (terminated)
2008 
                .out_channel       ()                                                                                 // (terminated)
2009 
        );
2010 
 
2011 
        altera_merlin_slave_agent #(
2012 
                .PKT_DATA_H                (31),
2013 
                .PKT_DATA_L                (0),
2014 
                .PKT_BEGIN_BURST           (81),
2015 
                .PKT_SYMBOL_W              (8),
2016 
                .PKT_BYTEEN_H              (35),
2017 
                .PKT_BYTEEN_L              (32),
2018 
                .PKT_ADDR_H                (61),
2019 
                .PKT_ADDR_L                (36),
2020 
                .PKT_TRANS_COMPRESSED_READ (62),
2021 
                .PKT_TRANS_POSTED          (63),
2022 
                .PKT_TRANS_WRITE           (64),
2023 
                .PKT_TRANS_READ            (65),
2024 
                .PKT_TRANS_LOCK            (66),
2025 
                .PKT_SRC_ID_H              (85),
2026 
                .PKT_SRC_ID_L              (83),
2027 
                .PKT_DEST_ID_H             (88),
2028 
                .PKT_DEST_ID_L             (86),
2029 
                .PKT_BURSTWRAP_H           (73),
2030 
                .PKT_BURSTWRAP_L           (71),
2031 
                .PKT_BYTE_CNT_H            (70),
2032 
                .PKT_BYTE_CNT_L            (68),
2033 
                .PKT_PROTECTION_H          (92),
2034 
                .PKT_PROTECTION_L          (90),
2035 
                .PKT_RESPONSE_STATUS_H     (98),
2036 
                .PKT_RESPONSE_STATUS_L     (97),
2037 
                .PKT_BURST_SIZE_H          (76),
2038 
                .PKT_BURST_SIZE_L          (74),
2039 
                .ST_CHANNEL_W              (8),
2040 
                .ST_DATA_W                 (99),
2041 
                .AVS_BURSTCOUNT_W          (3),
2042 
                .SUPPRESS_0_BYTEEN_CMD     (0),
2043 
                .PREVENT_FIFO_OVERFLOW     (1)
2044 
        ) jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent (
2045 
                .clk                     (clk_clk),                                                                                            //             clk.clk
2046 
                .reset                   (rst_controller_reset_out_reset),                                                                     //       clk_reset.reset
2047 
                .m0_address              (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
2048 
                .m0_burstcount           (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
2049 
                .m0_byteenable           (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
2050 
                .m0_debugaccess          (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
2051 
                .m0_lock                 (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
2052 
                .m0_readdata             (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
2053 
                .m0_readdatavalid        (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
2054 
                .m0_read                 (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
2055 
                .m0_waitrequest          (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
2056 
                .m0_writedata            (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
2057 
                .m0_write                (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
2058 
                .rp_endofpacket          (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
2059 
                .rp_ready                (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
2060 
                .rp_valid                (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
2061 
                .rp_data                 (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
2062 
                .rp_startofpacket        (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
2063 
                .cp_ready                (cmd_xbar_demux_001_src2_ready),                                                                      //              cp.ready
2064 
                .cp_valid                (cmd_xbar_demux_001_src2_valid),                                                                      //                .valid
2065 
                .cp_data                 (cmd_xbar_demux_001_src2_data),                                                                       //                .data
2066 
                .cp_startofpacket        (cmd_xbar_demux_001_src2_startofpacket),                                                              //                .startofpacket
2067 
                .cp_endofpacket          (cmd_xbar_demux_001_src2_endofpacket),                                                                //                .endofpacket
2068 
                .cp_channel              (cmd_xbar_demux_001_src2_channel),                                                                    //                .channel
2069 
                .rf_sink_ready           (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
2070 
                .rf_sink_valid           (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
2071 
                .rf_sink_startofpacket   (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
2072 
                .rf_sink_endofpacket     (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
2073 
                .rf_sink_data            (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
2074 
                .rf_source_ready         (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
2075 
                .rf_source_valid         (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
2076 
                .rf_source_startofpacket (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
2077 
                .rf_source_endofpacket   (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
2078 
                .rf_source_data          (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
2079 
                .rdata_fifo_sink_ready   (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
2080 
                .rdata_fifo_sink_valid   (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
2081 
                .rdata_fifo_sink_data    (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
2082 
                .rdata_fifo_src_ready    (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
2083 
                .rdata_fifo_src_valid    (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
2084 
                .rdata_fifo_src_data     (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
2085 
        );
2086 
 
2087 
        altera_avalon_sc_fifo #(
2088 
                .SYMBOLS_PER_BEAT    (1),
2089 
                .BITS_PER_SYMBOL     (100),
2090 
                .FIFO_DEPTH          (2),
2091 
                .CHANNEL_WIDTH       (0),
2092 
                .ERROR_WIDTH         (0),
2093 
                .USE_PACKETS         (1),
2094 
                .USE_FILL_LEVEL      (0),
2095 
                .EMPTY_LATENCY       (1),
2096 
                .USE_MEMORY_BLOCKS   (0),
2097 
                .USE_STORE_FORWARD   (0),
2098 
                .USE_ALMOST_FULL_IF  (0),
2099 
                .USE_ALMOST_EMPTY_IF (0)
2100 
        ) jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo (
2101 
                .clk               (clk_clk),                                                                                            //       clk.clk
2102 
                .reset             (rst_controller_reset_out_reset),                                                                     // clk_reset.reset
2103 
                .in_data           (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
2104 
                .in_valid          (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
2105 
                .in_ready          (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
2106 
                .in_startofpacket  (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
2107 
                .in_endofpacket    (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
2108 
                .out_data          (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
2109 
                .out_valid         (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
2110 
                .out_ready         (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
2111 
                .out_startofpacket (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
2112 
                .out_endofpacket   (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
2113 
                .csr_address       (2'b00),                                                                                              // (terminated)
2114 
                .csr_read          (1'b0),                                                                                               // (terminated)
2115 
                .csr_write         (1'b0),                                                                                               // (terminated)
2116 
                .csr_readdata      (),                                                                                                   // (terminated)
2117 
                .csr_writedata     (32'b00000000000000000000000000000000),                                                               // (terminated)
2118 
                .almost_full_data  (),                                                                                                   // (terminated)
2119 
                .almost_empty_data (),                                                                                                   // (terminated)
2120 
                .in_empty          (1'b0),                                                                                               // (terminated)
2121 
                .out_empty         (),                                                                                                   // (terminated)
2122 
                .in_error          (1'b0),                                                                                               // (terminated)
2123 
                .out_error         (),                                                                                                   // (terminated)
2124 
                .in_channel        (1'b0),                                                                                               // (terminated)
2125 
                .out_channel       ()                                                                                                    // (terminated)
2126 
        );
2127 
 
2128 
        altera_merlin_slave_agent #(
2129 
                .PKT_DATA_H                (31),
2130 
                .PKT_DATA_L                (0),
2131 
                .PKT_BEGIN_BURST           (81),
2132 
                .PKT_SYMBOL_W              (8),
2133 
                .PKT_BYTEEN_H              (35),
2134 
                .PKT_BYTEEN_L              (32),
2135 
                .PKT_ADDR_H                (61),
2136 
                .PKT_ADDR_L                (36),
2137 
                .PKT_TRANS_COMPRESSED_READ (62),
2138 
                .PKT_TRANS_POSTED          (63),
2139 
                .PKT_TRANS_WRITE           (64),
2140 
                .PKT_TRANS_READ            (65),
2141 
                .PKT_TRANS_LOCK            (66),
2142 
                .PKT_SRC_ID_H              (85),
2143 
                .PKT_SRC_ID_L              (83),
2144 
                .PKT_DEST_ID_H             (88),
2145 
                .PKT_DEST_ID_L             (86),
2146 
                .PKT_BURSTWRAP_H           (73),
2147 
                .PKT_BURSTWRAP_L           (71),
2148 
                .PKT_BYTE_CNT_H            (70),
2149 
                .PKT_BYTE_CNT_L            (68),
2150 
                .PKT_PROTECTION_H          (92),
2151 
                .PKT_PROTECTION_L          (90),
2152 
                .PKT_RESPONSE_STATUS_H     (98),
2153 
                .PKT_RESPONSE_STATUS_L     (97),
2154 
                .PKT_BURST_SIZE_H          (76),
2155 
                .PKT_BURST_SIZE_L          (74),
2156 
                .ST_CHANNEL_W              (8),
2157 
                .ST_DATA_W                 (99),
2158 
                .AVS_BURSTCOUNT_W          (3),
2159 
                .SUPPRESS_0_BYTEEN_CMD     (0),
2160 
                .PREVENT_FIFO_OVERFLOW     (1)
2161 
        ) timer_1_s1_translator_avalon_universal_slave_0_agent (
2162 
                .clk                     (clk_clk),                                                                         //             clk.clk
2163 
                .reset                   (rst_controller_reset_out_reset),                                                  //       clk_reset.reset
2164 
                .m0_address              (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
2165 
                .m0_burstcount           (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
2166 
                .m0_byteenable           (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
2167 
                .m0_debugaccess          (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
2168 
                .m0_lock                 (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
2169 
                .m0_readdata             (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
2170 
                .m0_readdatavalid        (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
2171 
                .m0_read                 (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
2172 
                .m0_waitrequest          (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
2173 
                .m0_writedata            (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
2174 
                .m0_write                (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
2175 
                .rp_endofpacket          (timer_1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
2176 
                .rp_ready                (timer_1_s1_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
2177 
                .rp_valid                (timer_1_s1_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
2178 
                .rp_data                 (timer_1_s1_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
2179 
                .rp_startofpacket        (timer_1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
2180 
                .cp_ready                (cmd_xbar_demux_001_src3_ready),                                                   //              cp.ready
2181 
                .cp_valid                (cmd_xbar_demux_001_src3_valid),                                                   //                .valid
2182 
                .cp_data                 (cmd_xbar_demux_001_src3_data),                                                    //                .data
2183 
                .cp_startofpacket        (cmd_xbar_demux_001_src3_startofpacket),                                           //                .startofpacket
2184 
                .cp_endofpacket          (cmd_xbar_demux_001_src3_endofpacket),                                             //                .endofpacket
2185 
                .cp_channel              (cmd_xbar_demux_001_src3_channel),                                                 //                .channel
2186 
                .rf_sink_ready           (timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
2187 
                .rf_sink_valid           (timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
2188 
                .rf_sink_startofpacket   (timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
2189 
                .rf_sink_endofpacket     (timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
2190 
                .rf_sink_data            (timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
2191 
                .rf_source_ready         (timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
2192 
                .rf_source_valid         (timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
2193 
                .rf_source_startofpacket (timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
2194 
                .rf_source_endofpacket   (timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
2195 
                .rf_source_data          (timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
2196 
                .rdata_fifo_sink_ready   (timer_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
2197 
                .rdata_fifo_sink_valid   (timer_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
2198 
                .rdata_fifo_sink_data    (timer_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
2199 
                .rdata_fifo_src_ready    (timer_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
2200 
                .rdata_fifo_src_valid    (timer_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
2201 
                .rdata_fifo_src_data     (timer_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
2202 
        );
2203 
 
2204 
        altera_avalon_sc_fifo #(
2205 
                .SYMBOLS_PER_BEAT    (1),
2206 
                .BITS_PER_SYMBOL     (100),
2207 
                .FIFO_DEPTH          (2),
2208 
                .CHANNEL_WIDTH       (0),
2209 
                .ERROR_WIDTH         (0),
2210 
                .USE_PACKETS         (1),
2211 
                .USE_FILL_LEVEL      (0),
2212 
                .EMPTY_LATENCY       (1),
2213 
                .USE_MEMORY_BLOCKS   (0),
2214 
                .USE_STORE_FORWARD   (0),
2215 
                .USE_ALMOST_FULL_IF  (0),
2216 
                .USE_ALMOST_EMPTY_IF (0)
2217 
        ) timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
2218 
                .clk               (clk_clk),                                                                         //       clk.clk
2219 
                .reset             (rst_controller_reset_out_reset),                                                  // clk_reset.reset
2220 
                .in_data           (timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
2221 
                .in_valid          (timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
2222 
                .in_ready          (timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
2223 
                .in_startofpacket  (timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
2224 
                .in_endofpacket    (timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
2225 
                .out_data          (timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
2226 
                .out_valid         (timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
2227 
                .out_ready         (timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
2228 
                .out_startofpacket (timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
2229 
                .out_endofpacket   (timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
2230 
                .csr_address       (2'b00),                                                                           // (terminated)
2231 
                .csr_read          (1'b0),                                                                            // (terminated)
2232 
                .csr_write         (1'b0),                                                                            // (terminated)
2233 
                .csr_readdata      (),                                                                                // (terminated)
2234 
                .csr_writedata     (32'b00000000000000000000000000000000),                                            // (terminated)
2235 
                .almost_full_data  (),                                                                                // (terminated)
2236 
                .almost_empty_data (),                                                                                // (terminated)
2237 
                .in_empty          (1'b0),                                                                            // (terminated)
2238 
                .out_empty         (),                                                                                // (terminated)
2239 
                .in_error          (1'b0),                                                                            // (terminated)
2240 
                .out_error         (),                                                                                // (terminated)
2241 
                .in_channel        (1'b0),                                                                            // (terminated)
2242 
                .out_channel       ()                                                                                 // (terminated)
2243 
        );
2244 
 
2245 
        altera_merlin_slave_agent #(
2246 
                .PKT_DATA_H                (31),
2247 
                .PKT_DATA_L                (0),
2248 
                .PKT_BEGIN_BURST           (81),
2249 
                .PKT_SYMBOL_W              (8),
2250 
                .PKT_BYTEEN_H              (35),
2251 
                .PKT_BYTEEN_L              (32),
2252 
                .PKT_ADDR_H                (61),
2253 
                .PKT_ADDR_L                (36),
2254 
                .PKT_TRANS_COMPRESSED_READ (62),
2255 
                .PKT_TRANS_POSTED          (63),
2256 
                .PKT_TRANS_WRITE           (64),
2257 
                .PKT_TRANS_READ            (65),
2258 
                .PKT_TRANS_LOCK            (66),
2259 
                .PKT_SRC_ID_H              (85),
2260 
                .PKT_SRC_ID_L              (83),
2261 
                .PKT_DEST_ID_H             (88),
2262 
                .PKT_DEST_ID_L             (86),
2263 
                .PKT_BURSTWRAP_H           (73),
2264 
                .PKT_BURSTWRAP_L           (71),
2265 
                .PKT_BYTE_CNT_H            (70),
2266 
                .PKT_BYTE_CNT_L            (68),
2267 
                .PKT_PROTECTION_H          (92),
2268 
                .PKT_PROTECTION_L          (90),
2269 
                .PKT_RESPONSE_STATUS_H     (98),
2270 
                .PKT_RESPONSE_STATUS_L     (97),
2271 
                .PKT_BURST_SIZE_H          (76),
2272 
                .PKT_BURST_SIZE_L          (74),
2273 
                .ST_CHANNEL_W              (8),
2274 
                .ST_DATA_W                 (99),
2275 
                .AVS_BURSTCOUNT_W          (3),
2276 
                .SUPPRESS_0_BYTEEN_CMD     (0),
2277 
                .PREVENT_FIFO_OVERFLOW     (1)
2278 
        ) timer_0_s1_translator_avalon_universal_slave_0_agent (
2279 
                .clk                     (clk_clk),                                                                         //             clk.clk
2280 
                .reset                   (rst_controller_reset_out_reset),                                                  //       clk_reset.reset
2281 
                .m0_address              (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
2282 
                .m0_burstcount           (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
2283 
                .m0_byteenable           (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
2284 
                .m0_debugaccess          (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
2285 
                .m0_lock                 (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
2286 
                .m0_readdata             (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
2287 
                .m0_readdatavalid        (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
2288 
                .m0_read                 (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
2289 
                .m0_waitrequest          (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
2290 
                .m0_writedata            (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
2291 
                .m0_write                (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
2292 
                .rp_endofpacket          (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
2293 
                .rp_ready                (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
2294 
                .rp_valid                (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
2295 
                .rp_data                 (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
2296 
                .rp_startofpacket        (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
2297 
                .cp_ready                (cmd_xbar_demux_001_src4_ready),                                                   //              cp.ready
2298 
                .cp_valid                (cmd_xbar_demux_001_src4_valid),                                                   //                .valid
2299 
                .cp_data                 (cmd_xbar_demux_001_src4_data),                                                    //                .data
2300 
                .cp_startofpacket        (cmd_xbar_demux_001_src4_startofpacket),                                           //                .startofpacket
2301 
                .cp_endofpacket          (cmd_xbar_demux_001_src4_endofpacket),                                             //                .endofpacket
2302 
                .cp_channel              (cmd_xbar_demux_001_src4_channel),                                                 //                .channel
2303 
                .rf_sink_ready           (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
2304 
                .rf_sink_valid           (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
2305 
                .rf_sink_startofpacket   (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
2306 
                .rf_sink_endofpacket     (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
2307 
                .rf_sink_data            (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
2308 
                .rf_source_ready         (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
2309 
                .rf_source_valid         (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
2310 
                .rf_source_startofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
2311 
                .rf_source_endofpacket   (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
2312 
                .rf_source_data          (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
2313 
                .rdata_fifo_sink_ready   (timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
2314 
                .rdata_fifo_sink_valid   (timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
2315 
                .rdata_fifo_sink_data    (timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
2316 
                .rdata_fifo_src_ready    (timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
2317 
                .rdata_fifo_src_valid    (timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
2318 
                .rdata_fifo_src_data     (timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
2319 
        );
2320 
 
2321 
        altera_avalon_sc_fifo #(
2322 
                .SYMBOLS_PER_BEAT    (1),
2323 
                .BITS_PER_SYMBOL     (100),
2324 
                .FIFO_DEPTH          (2),
2325 
                .CHANNEL_WIDTH       (0),
2326 
                .ERROR_WIDTH         (0),
2327 
                .USE_PACKETS         (1),
2328 
                .USE_FILL_LEVEL      (0),
2329 
                .EMPTY_LATENCY       (1),
2330 
                .USE_MEMORY_BLOCKS   (0),
2331 
                .USE_STORE_FORWARD   (0),
2332 
                .USE_ALMOST_FULL_IF  (0),
2333 
                .USE_ALMOST_EMPTY_IF (0)
2334 
        ) timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
2335 
                .clk               (clk_clk),                                                                         //       clk.clk
2336 
                .reset             (rst_controller_reset_out_reset),                                                  // clk_reset.reset
2337 
                .in_data           (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
2338 
                .in_valid          (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
2339 
                .in_ready          (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
2340 
                .in_startofpacket  (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
2341 
                .in_endofpacket    (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
2342 
                .out_data          (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
2343 
                .out_valid         (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
2344 
                .out_ready         (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
2345 
                .out_startofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
2346 
                .out_endofpacket   (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
2347 
                .csr_address       (2'b00),                                                                           // (terminated)
2348 
                .csr_read          (1'b0),                                                                            // (terminated)
2349 
                .csr_write         (1'b0),                                                                            // (terminated)
2350 
                .csr_readdata      (),                                                                                // (terminated)
2351 
                .csr_writedata     (32'b00000000000000000000000000000000),                                            // (terminated)
2352 
                .almost_full_data  (),                                                                                // (terminated)
2353 
                .almost_empty_data (),                                                                                // (terminated)
2354 
                .in_empty          (1'b0),                                                                            // (terminated)
2355 
                .out_empty         (),                                                                                // (terminated)
2356 
                .in_error          (1'b0),                                                                            // (terminated)
2357 
                .out_error         (),                                                                                // (terminated)
2358 
                .in_channel        (1'b0),                                                                            // (terminated)
2359 
                .out_channel       ()                                                                                 // (terminated)
2360 
        );
2361 
 
2362 
        altera_merlin_slave_agent #(
2363 
                .PKT_DATA_H                (31),
2364 
                .PKT_DATA_L                (0),
2365 
                .PKT_BEGIN_BURST           (81),
2366 
                .PKT_SYMBOL_W              (8),
2367 
                .PKT_BYTEEN_H              (35),
2368 
                .PKT_BYTEEN_L              (32),
2369 
                .PKT_ADDR_H                (61),
2370 
                .PKT_ADDR_L                (36),
2371 
                .PKT_TRANS_COMPRESSED_READ (62),
2372 
                .PKT_TRANS_POSTED          (63),
2373 
                .PKT_TRANS_WRITE           (64),
2374 
                .PKT_TRANS_READ            (65),
2375 
                .PKT_TRANS_LOCK            (66),
2376 
                .PKT_SRC_ID_H              (85),
2377 
                .PKT_SRC_ID_L              (83),
2378 
                .PKT_DEST_ID_H             (88),
2379 
                .PKT_DEST_ID_L             (86),
2380 
                .PKT_BURSTWRAP_H           (73),
2381 
                .PKT_BURSTWRAP_L           (71),
2382 
                .PKT_BYTE_CNT_H            (70),
2383 
                .PKT_BYTE_CNT_L            (68),
2384 
                .PKT_PROTECTION_H          (92),
2385 
                .PKT_PROTECTION_L          (90),
2386 
                .PKT_RESPONSE_STATUS_H     (98),
2387 
                .PKT_RESPONSE_STATUS_L     (97),
2388 
                .PKT_BURST_SIZE_H          (76),
2389 
                .PKT_BURST_SIZE_L          (74),
2390 
                .ST_CHANNEL_W              (8),
2391 
                .ST_DATA_W                 (99),
2392 
                .AVS_BURSTCOUNT_W          (3),
2393 
                .SUPPRESS_0_BYTEEN_CMD     (0),
2394 
                .PREVENT_FIFO_OVERFLOW     (1)
2395 
        ) sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent (
2396 
                .clk                     (clk_clk),                                                                                         //             clk.clk
2397 
                .reset                   (rst_controller_reset_out_reset),                                                                  //       clk_reset.reset
2398 
                .m0_address              (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
2399 
                .m0_burstcount           (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
2400 
                .m0_byteenable           (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
2401 
                .m0_debugaccess          (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
2402 
                .m0_lock                 (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
2403 
                .m0_readdata             (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
2404 
                .m0_readdatavalid        (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
2405 
                .m0_read                 (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
2406 
                .m0_waitrequest          (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
2407 
                .m0_writedata            (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
2408 
                .m0_write                (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
2409 
                .rp_endofpacket          (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
2410 
                .rp_ready                (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
2411 
                .rp_valid                (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
2412 
                .rp_data                 (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
2413 
                .rp_startofpacket        (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
2414 
                .cp_ready                (cmd_xbar_demux_001_src5_ready),                                                                   //              cp.ready
2415 
                .cp_valid                (cmd_xbar_demux_001_src5_valid),                                                                   //                .valid
2416 
                .cp_data                 (cmd_xbar_demux_001_src5_data),                                                                    //                .data
2417 
                .cp_startofpacket        (cmd_xbar_demux_001_src5_startofpacket),                                                           //                .startofpacket
2418 
                .cp_endofpacket          (cmd_xbar_demux_001_src5_endofpacket),                                                             //                .endofpacket
2419 
                .cp_channel              (cmd_xbar_demux_001_src5_channel),                                                                 //                .channel
2420 
                .rf_sink_ready           (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
2421 
                .rf_sink_valid           (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
2422 
                .rf_sink_startofpacket   (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
2423 
                .rf_sink_endofpacket     (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
2424 
                .rf_sink_data            (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
2425 
                .rf_source_ready         (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
2426 
                .rf_source_valid         (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
2427 
                .rf_source_startofpacket (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
2428 
                .rf_source_endofpacket   (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
2429 
                .rf_source_data          (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
2430 
                .rdata_fifo_sink_ready   (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
2431 
                .rdata_fifo_sink_valid   (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
2432 
                .rdata_fifo_sink_data    (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
2433 
                .rdata_fifo_src_ready    (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
2434 
                .rdata_fifo_src_valid    (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
2435 
                .rdata_fifo_src_data     (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
2436 
        );
2437 
 
2438 
        altera_avalon_sc_fifo #(
2439 
                .SYMBOLS_PER_BEAT    (1),
2440 
                .BITS_PER_SYMBOL     (100),
2441 
                .FIFO_DEPTH          (2),
2442 
                .CHANNEL_WIDTH       (0),
2443 
                .ERROR_WIDTH         (0),
2444 
                .USE_PACKETS         (1),
2445 
                .USE_FILL_LEVEL      (0),
2446 
                .EMPTY_LATENCY       (1),
2447 
                .USE_MEMORY_BLOCKS   (0),
2448 
                .USE_STORE_FORWARD   (0),
2449 
                .USE_ALMOST_FULL_IF  (0),
2450 
                .USE_ALMOST_EMPTY_IF (0)
2451 
        ) sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo (
2452 
                .clk               (clk_clk),                                                                                         //       clk.clk
2453 
                .reset             (rst_controller_reset_out_reset),                                                                  // clk_reset.reset
2454 
                .in_data           (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
2455 
                .in_valid          (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
2456 
                .in_ready          (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
2457 
                .in_startofpacket  (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
2458 
                .in_endofpacket    (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
2459 
                .out_data          (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
2460 
                .out_valid         (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
2461 
                .out_ready         (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
2462 
                .out_startofpacket (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
2463 
                .out_endofpacket   (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
2464 
                .csr_address       (2'b00),                                                                                           // (terminated)
2465 
                .csr_read          (1'b0),                                                                                            // (terminated)
2466 
                .csr_write         (1'b0),                                                                                            // (terminated)
2467 
                .csr_readdata      (),                                                                                                // (terminated)
2468 
                .csr_writedata     (32'b00000000000000000000000000000000),                                                            // (terminated)
2469 
                .almost_full_data  (),                                                                                                // (terminated)
2470 
                .almost_empty_data (),                                                                                                // (terminated)
2471 
                .in_empty          (1'b0),                                                                                            // (terminated)
2472 
                .out_empty         (),                                                                                                // (terminated)
2473 
                .in_error          (1'b0),                                                                                            // (terminated)
2474 
                .out_error         (),                                                                                                // (terminated)
2475 
                .in_channel        (1'b0),                                                                                            // (terminated)
2476 
                .out_channel       ()                                                                                                 // (terminated)
2477 
        );
2478 
 
2479 
        altera_merlin_slave_agent #(
2480 
                .PKT_DATA_H                (31),
2481 
                .PKT_DATA_L                (0),
2482 
                .PKT_BEGIN_BURST           (81),
2483 
                .PKT_SYMBOL_W              (8),
2484 
                .PKT_BYTEEN_H              (35),
2485 
                .PKT_BYTEEN_L              (32),
2486 
                .PKT_ADDR_H                (61),
2487 
                .PKT_ADDR_L                (36),
2488 
                .PKT_TRANS_COMPRESSED_READ (62),
2489 
                .PKT_TRANS_POSTED          (63),
2490 
                .PKT_TRANS_WRITE           (64),
2491 
                .PKT_TRANS_READ            (65),
2492 
                .PKT_TRANS_LOCK            (66),
2493 
                .PKT_SRC_ID_H              (85),
2494 
                .PKT_SRC_ID_L              (83),
2495 
                .PKT_DEST_ID_H             (88),
2496 
                .PKT_DEST_ID_L             (86),
2497 
                .PKT_BURSTWRAP_H           (73),
2498 
                .PKT_BURSTWRAP_L           (71),
2499 
                .PKT_BYTE_CNT_H            (70),
2500 
                .PKT_BYTE_CNT_L            (68),
2501 
                .PKT_PROTECTION_H          (92),
2502 
                .PKT_PROTECTION_L          (90),
2503 
                .PKT_RESPONSE_STATUS_H     (98),
2504 
                .PKT_RESPONSE_STATUS_L     (97),
2505 
                .PKT_BURST_SIZE_H          (76),
2506 
                .PKT_BURST_SIZE_L          (74),
2507 
                .ST_CHANNEL_W              (8),
2508 
                .ST_DATA_W                 (99),
2509 
                .AVS_BURSTCOUNT_W          (3),
2510 
                .SUPPRESS_0_BYTEEN_CMD     (0),
2511 
                .PREVENT_FIFO_OVERFLOW     (1)
2512 
        ) onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent (
2513 
                .clk                     (clk_clk),                                                                                  //             clk.clk
2514 
                .reset                   (rst_controller_reset_out_reset),                                                           //       clk_reset.reset
2515 
                .m0_address              (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
2516 
                .m0_burstcount           (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
2517 
                .m0_byteenable           (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
2518 
                .m0_debugaccess          (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
2519 
                .m0_lock                 (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
2520 
                .m0_readdata             (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
2521 
                .m0_readdatavalid        (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
2522 
                .m0_read                 (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
2523 
                .m0_waitrequest          (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
2524 
                .m0_writedata            (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
2525 
                .m0_write                (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
2526 
                .rp_endofpacket          (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
2527 
                .rp_ready                (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
2528 
                .rp_valid                (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
2529 
                .rp_data                 (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
2530 
                .rp_startofpacket        (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
2531 
                .cp_ready                (cmd_xbar_demux_001_src6_ready),                                                            //              cp.ready
2532 
                .cp_valid                (cmd_xbar_demux_001_src6_valid),                                                            //                .valid
2533 
                .cp_data                 (cmd_xbar_demux_001_src6_data),                                                             //                .data
2534 
                .cp_startofpacket        (cmd_xbar_demux_001_src6_startofpacket),                                                    //                .startofpacket
2535 
                .cp_endofpacket          (cmd_xbar_demux_001_src6_endofpacket),                                                      //                .endofpacket
2536 
                .cp_channel              (cmd_xbar_demux_001_src6_channel),                                                          //                .channel
2537 
                .rf_sink_ready           (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
2538 
                .rf_sink_valid           (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
2539 
                .rf_sink_startofpacket   (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
2540 
                .rf_sink_endofpacket     (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
2541 
                .rf_sink_data            (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
2542 
                .rf_source_ready         (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
2543 
                .rf_source_valid         (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
2544 
                .rf_source_startofpacket (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
2545 
                .rf_source_endofpacket   (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
2546 
                .rf_source_data          (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
2547 
                .rdata_fifo_sink_ready   (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
2548 
                .rdata_fifo_sink_valid   (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
2549 
                .rdata_fifo_sink_data    (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
2550 
                .rdata_fifo_src_ready    (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
2551 
                .rdata_fifo_src_valid    (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
2552 
                .rdata_fifo_src_data     (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
2553 
        );
2554 
 
2555 
        altera_avalon_sc_fifo #(
2556 
                .SYMBOLS_PER_BEAT    (1),
2557 
                .BITS_PER_SYMBOL     (100),
2558 
                .FIFO_DEPTH          (2),
2559 
                .CHANNEL_WIDTH       (0),
2560 
                .ERROR_WIDTH         (0),
2561 
                .USE_PACKETS         (1),
2562 
                .USE_FILL_LEVEL      (0),
2563 
                .EMPTY_LATENCY       (1),
2564 
                .USE_MEMORY_BLOCKS   (0),
2565 
                .USE_STORE_FORWARD   (0),
2566 
                .USE_ALMOST_FULL_IF  (0),
2567 
                .USE_ALMOST_EMPTY_IF (0)
2568 
        ) onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
2569 
                .clk               (clk_clk),                                                                                  //       clk.clk
2570 
                .reset             (rst_controller_reset_out_reset),                                                           // clk_reset.reset
2571 
                .in_data           (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
2572 
                .in_valid          (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
2573 
                .in_ready          (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
2574 
                .in_startofpacket  (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
2575 
                .in_endofpacket    (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
2576 
                .out_data          (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
2577 
                .out_valid         (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
2578 
                .out_ready         (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
2579 
                .out_startofpacket (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
2580 
                .out_endofpacket   (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
2581 
                .csr_address       (2'b00),                                                                                    // (terminated)
2582 
                .csr_read          (1'b0),                                                                                     // (terminated)
2583 
                .csr_write         (1'b0),                                                                                     // (terminated)
2584 
                .csr_readdata      (),                                                                                         // (terminated)
2585 
                .csr_writedata     (32'b00000000000000000000000000000000),                                                     // (terminated)
2586 
                .almost_full_data  (),                                                                                         // (terminated)
2587 
                .almost_empty_data (),                                                                                         // (terminated)
2588 
                .in_empty          (1'b0),                                                                                     // (terminated)
2589 
                .out_empty         (),                                                                                         // (terminated)
2590 
                .in_error          (1'b0),                                                                                     // (terminated)
2591 
                .out_error         (),                                                                                         // (terminated)
2592 
                .in_channel        (1'b0),                                                                                     // (terminated)
2593 
                .out_channel       ()                                                                                          // (terminated)
2594 
        );
2595 
 
2596 
        altera_merlin_slave_agent #(
2597 
                .PKT_DATA_H                (31),
2598 
                .PKT_DATA_L                (0),
2599 
                .PKT_BEGIN_BURST           (81),
2600 
                .PKT_SYMBOL_W              (8),
2601 
                .PKT_BYTEEN_H              (35),
2602 
                .PKT_BYTEEN_L              (32),
2603 
                .PKT_ADDR_H                (61),
2604 
                .PKT_ADDR_L                (36),
2605 
                .PKT_TRANS_COMPRESSED_READ (62),
2606 
                .PKT_TRANS_POSTED          (63),
2607 
                .PKT_TRANS_WRITE           (64),
2608 
                .PKT_TRANS_READ            (65),
2609 
                .PKT_TRANS_LOCK            (66),
2610 
                .PKT_SRC_ID_H              (85),
2611 
                .PKT_SRC_ID_L              (83),
2612 
                .PKT_DEST_ID_H             (88),
2613 
                .PKT_DEST_ID_L             (86),
2614 
                .PKT_BURSTWRAP_H           (73),
2615 
                .PKT_BURSTWRAP_L           (71),
2616 
                .PKT_BYTE_CNT_H            (70),
2617 
                .PKT_BYTE_CNT_L            (68),
2618 
                .PKT_PROTECTION_H          (92),
2619 
                .PKT_PROTECTION_L          (90),
2620 
                .PKT_RESPONSE_STATUS_H     (98),
2621 
                .PKT_RESPONSE_STATUS_L     (97),
2622 
                .PKT_BURST_SIZE_H          (76),
2623 
                .PKT_BURST_SIZE_L          (74),
2624 
                .ST_CHANNEL_W              (8),
2625 
                .ST_DATA_W                 (99),
2626 
                .AVS_BURSTCOUNT_W          (3),
2627 
                .SUPPRESS_0_BYTEEN_CMD     (0),
2628 
                .PREVENT_FIFO_OVERFLOW     (1)
2629 
        ) hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent (
2630 
                .clk                     (clk_clk),                                                                                           //             clk.clk
2631 
                .reset                   (rst_controller_reset_out_reset),                                                                    //       clk_reset.reset
2632 
                .m0_address              (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
2633 
                .m0_burstcount           (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
2634 
                .m0_byteenable           (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
2635 
                .m0_debugaccess          (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
2636 
                .m0_lock                 (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
2637 
                .m0_readdata             (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
2638 
                .m0_readdatavalid        (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
2639 
                .m0_read                 (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
2640 
                .m0_waitrequest          (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
2641 
                .m0_writedata            (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
2642 
                .m0_write                (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
2643 
                .rp_endofpacket          (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
2644 
                .rp_ready                (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
2645 
                .rp_valid                (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
2646 
                .rp_data                 (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
2647 
                .rp_startofpacket        (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
2648 
                .cp_ready                (cmd_xbar_demux_001_src7_ready),                                                                     //              cp.ready
2649 
                .cp_valid                (cmd_xbar_demux_001_src7_valid),                                                                     //                .valid
2650 
                .cp_data                 (cmd_xbar_demux_001_src7_data),                                                                      //                .data
2651 
                .cp_startofpacket        (cmd_xbar_demux_001_src7_startofpacket),                                                             //                .startofpacket
2652 
                .cp_endofpacket          (cmd_xbar_demux_001_src7_endofpacket),                                                               //                .endofpacket
2653 
                .cp_channel              (cmd_xbar_demux_001_src7_channel),                                                                   //                .channel
2654 
                .rf_sink_ready           (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
2655 
                .rf_sink_valid           (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
2656 
                .rf_sink_startofpacket   (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
2657 
                .rf_sink_endofpacket     (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
2658 
                .rf_sink_data            (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
2659 
                .rf_source_ready         (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
2660 
                .rf_source_valid         (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
2661 
                .rf_source_startofpacket (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
2662 
                .rf_source_endofpacket   (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
2663 
                .rf_source_data          (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
2664 
                .rdata_fifo_sink_ready   (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
2665 
                .rdata_fifo_sink_valid   (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
2666 
                .rdata_fifo_sink_data    (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
2667 
                .rdata_fifo_src_ready    (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
2668 
                .rdata_fifo_src_valid    (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
2669 
                .rdata_fifo_src_data     (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
2670 
        );
2671 
 
2672 
        altera_avalon_sc_fifo #(
2673 
                .SYMBOLS_PER_BEAT    (1),
2674 
                .BITS_PER_SYMBOL     (100),
2675 
                .FIFO_DEPTH          (2),
2676 
                .CHANNEL_WIDTH       (0),
2677 
                .ERROR_WIDTH         (0),
2678 
                .USE_PACKETS         (1),
2679 
                .USE_FILL_LEVEL      (0),
2680 
                .EMPTY_LATENCY       (1),
2681 
                .USE_MEMORY_BLOCKS   (0),
2682 
                .USE_STORE_FORWARD   (0),
2683 
                .USE_ALMOST_FULL_IF  (0),
2684 
                .USE_ALMOST_EMPTY_IF (0)
2685 
        ) hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo (
2686 
                .clk               (clk_clk),                                                                                           //       clk.clk
2687 
                .reset             (rst_controller_reset_out_reset),                                                                    // clk_reset.reset
2688 
                .in_data           (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
2689 
                .in_valid          (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
2690 
                .in_ready          (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
2691 
                .in_startofpacket  (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
2692 
                .in_endofpacket    (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
2693 
                .out_data          (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
2694 
                .out_valid         (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
2695 
                .out_ready         (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
2696 
                .out_startofpacket (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
2697 
                .out_endofpacket   (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
2698 
                .csr_address       (2'b00),                                                                                             // (terminated)
2699 
                .csr_read          (1'b0),                                                                                              // (terminated)
2700 
                .csr_write         (1'b0),                                                                                              // (terminated)
2701 
                .csr_readdata      (),                                                                                                  // (terminated)
2702 
                .csr_writedata     (32'b00000000000000000000000000000000),                                                              // (terminated)
2703 
                .almost_full_data  (),                                                                                                  // (terminated)
2704 
                .almost_empty_data (),                                                                                                  // (terminated)
2705 
                .in_empty          (1'b0),                                                                                              // (terminated)
2706 
                .out_empty         (),                                                                                                  // (terminated)
2707 
                .in_error          (1'b0),                                                                                              // (terminated)
2708 
                .out_error         (),                                                                                                  // (terminated)
2709 
                .in_channel        (1'b0),                                                                                              // (terminated)
2710 
                .out_channel       ()                                                                                                   // (terminated)
2711 
        );
2712 
 
2713 
        altera_merlin_master_agent #(
2714 
                .PKT_PROTECTION_H          (94),
2715 
                .PKT_PROTECTION_L          (92),
2716 
                .PKT_BEGIN_BURST           (87),
2717 
                .PKT_BURSTWRAP_H           (79),
2718 
                .PKT_BURSTWRAP_L           (77),
2719 
                .PKT_BURST_SIZE_H          (82),
2720 
                .PKT_BURST_SIZE_L          (80),
2721 
                .PKT_BURST_TYPE_H          (84),
2722 
                .PKT_BURST_TYPE_L          (83),
2723 
                .PKT_BYTE_CNT_H            (76),
2724 
                .PKT_BYTE_CNT_L            (74),
2725 
                .PKT_ADDR_H                (67),
2726 
                .PKT_ADDR_L                (36),
2727 
                .PKT_TRANS_COMPRESSED_READ (68),
2728 
                .PKT_TRANS_POSTED          (69),
2729 
                .PKT_TRANS_WRITE           (70),
2730 
                .PKT_TRANS_READ            (71),
2731 
                .PKT_TRANS_LOCK            (72),
2732 
                .PKT_TRANS_EXCLUSIVE       (73),
2733 
                .PKT_DATA_H                (31),
2734 
                .PKT_DATA_L                (0),
2735 
                .PKT_BYTEEN_H              (35),
2736 
                .PKT_BYTEEN_L              (32),
2737 
                .PKT_SRC_ID_H              (89),
2738 
                .PKT_SRC_ID_L              (89),
2739 
                .PKT_DEST_ID_H             (90),
2740 
                .PKT_DEST_ID_L             (90),
2741 
                .PKT_THREAD_ID_H           (91),
2742 
                .PKT_THREAD_ID_L           (91),
2743 
                .PKT_CACHE_H               (98),
2744 
                .PKT_CACHE_L               (95),
2745 
                .PKT_DATA_SIDEBAND_H       (86),
2746 
                .PKT_DATA_SIDEBAND_L       (86),
2747 
                .PKT_QOS_H                 (88),
2748 
                .PKT_QOS_L                 (88),
2749 
                .PKT_ADDR_SIDEBAND_H       (85),
2750 
                .PKT_ADDR_SIDEBAND_L       (85),
2751 
                .ST_DATA_W                 (101),
2752 
                .ST_CHANNEL_W              (2),
2753 
                .AV_BURSTCOUNT_W           (3),
2754 
                .SUPPRESS_0_BYTEEN_RSP     (0),
2755 
                .ID                        (0),
2756 
                .BURSTWRAP_VALUE           (7),
2757 
                .CACHE_VALUE               (4'b0000)
2758 
        ) hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent (
2759 
                .clk              (clk_clk),                                                                                 //       clk.clk
2760 
                .reset            (rst_controller_reset_out_reset),                                                          // clk_reset.reset
2761 
                .av_address       (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_address),                //        av.address
2762 
                .av_write         (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_write),                  //          .write
2763 
                .av_read          (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_read),                   //          .read
2764 
                .av_writedata     (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_writedata),              //          .writedata
2765 
                .av_readdata      (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_readdata),               //          .readdata
2766 
                .av_waitrequest   (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_waitrequest),            //          .waitrequest
2767 
                .av_readdatavalid (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_readdatavalid),          //          .readdatavalid
2768 
                .av_byteenable    (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_byteenable),             //          .byteenable
2769 
                .av_burstcount    (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_burstcount),             //          .burstcount
2770 
                .av_debugaccess   (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_debugaccess),            //          .debugaccess
2771 
                .av_lock          (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_lock),                   //          .lock
2772 
                .cp_valid         (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_valid),         //        cp.valid
2773 
                .cp_data          (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_data),          //          .data
2774 
                .cp_startofpacket (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
2775 
                .cp_endofpacket   (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
2776 
                .cp_ready         (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_ready),         //          .ready
2777 
                .rp_valid         (rsp_xbar_demux_008_src0_valid),                                                           //        rp.valid
2778 
                .rp_data          (rsp_xbar_demux_008_src0_data),                                                            //          .data
2779 
                .rp_channel       (rsp_xbar_demux_008_src0_channel),                                                         //          .channel
2780 
                .rp_startofpacket (rsp_xbar_demux_008_src0_startofpacket),                                                   //          .startofpacket
2781 
                .rp_endofpacket   (rsp_xbar_demux_008_src0_endofpacket),                                                     //          .endofpacket
2782 
                .rp_ready         (rsp_xbar_demux_008_src0_ready)                                                            //          .ready
2783 
        );
2784 
 
2785 
        altera_merlin_master_agent #(
2786 
                .PKT_PROTECTION_H          (94),
2787 
                .PKT_PROTECTION_L          (92),
2788 
                .PKT_BEGIN_BURST           (87),
2789 
                .PKT_BURSTWRAP_H           (79),
2790 
                .PKT_BURSTWRAP_L           (77),
2791 
                .PKT_BURST_SIZE_H          (82),
2792 
                .PKT_BURST_SIZE_L          (80),
2793 
                .PKT_BURST_TYPE_H          (84),
2794 
                .PKT_BURST_TYPE_L          (83),
2795 
                .PKT_BYTE_CNT_H            (76),
2796 
                .PKT_BYTE_CNT_L            (74),
2797 
                .PKT_ADDR_H                (67),
2798 
                .PKT_ADDR_L                (36),
2799 
                .PKT_TRANS_COMPRESSED_READ (68),
2800 
                .PKT_TRANS_POSTED          (69),
2801 
                .PKT_TRANS_WRITE           (70),
2802 
                .PKT_TRANS_READ            (71),
2803 
                .PKT_TRANS_LOCK            (72),
2804 
                .PKT_TRANS_EXCLUSIVE       (73),
2805 
                .PKT_DATA_H                (31),
2806 
                .PKT_DATA_L                (0),
2807 
                .PKT_BYTEEN_H              (35),
2808 
                .PKT_BYTEEN_L              (32),
2809 
                .PKT_SRC_ID_H              (89),
2810 
                .PKT_SRC_ID_L              (89),
2811 
                .PKT_DEST_ID_H             (90),
2812 
                .PKT_DEST_ID_L             (90),
2813 
                .PKT_THREAD_ID_H           (91),
2814 
                .PKT_THREAD_ID_L           (91),
2815 
                .PKT_CACHE_H               (98),
2816 
                .PKT_CACHE_L               (95),
2817 
                .PKT_DATA_SIDEBAND_H       (86),
2818 
                .PKT_DATA_SIDEBAND_L       (86),
2819 
                .PKT_QOS_H                 (88),
2820 
                .PKT_QOS_L                 (88),
2821 
                .PKT_ADDR_SIDEBAND_H       (85),
2822 
                .PKT_ADDR_SIDEBAND_L       (85),
2823 
                .ST_DATA_W                 (101),
2824 
                .ST_CHANNEL_W              (2),
2825 
                .AV_BURSTCOUNT_W           (3),
2826 
                .SUPPRESS_0_BYTEEN_RSP     (0),
2827 
                .ID                        (1),
2828 
                .BURSTWRAP_VALUE           (7),
2829 
                .CACHE_VALUE               (4'b0000)
2830 
        ) hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent (
2831 
                .clk              (clk_clk),                                                                                   //       clk.clk
2832 
                .reset            (rst_controller_reset_out_reset),                                                            // clk_reset.reset
2833 
                .av_address       (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_address),                //        av.address
2834 
                .av_write         (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_write),                  //          .write
2835 
                .av_read          (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_read),                   //          .read
2836 
                .av_writedata     (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_writedata),              //          .writedata
2837 
                .av_readdata      (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_readdata),               //          .readdata
2838 
                .av_waitrequest   (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_waitrequest),            //          .waitrequest
2839 
                .av_readdatavalid (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_readdatavalid),          //          .readdatavalid
2840 
                .av_byteenable    (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_byteenable),             //          .byteenable
2841 
                .av_burstcount    (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_burstcount),             //          .burstcount
2842 
                .av_debugaccess   (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_debugaccess),            //          .debugaccess
2843 
                .av_lock          (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_lock),                   //          .lock
2844 
                .cp_valid         (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_valid),         //        cp.valid
2845 
                .cp_data          (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_data),          //          .data
2846 
                .cp_startofpacket (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
2847 
                .cp_endofpacket   (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
2848 
                .cp_ready         (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_ready),         //          .ready
2849 
                .rp_valid         (rsp_xbar_demux_008_src1_valid),                                                             //        rp.valid
2850 
                .rp_data          (rsp_xbar_demux_008_src1_data),                                                              //          .data
2851 
                .rp_channel       (rsp_xbar_demux_008_src1_channel),                                                           //          .channel
2852 
                .rp_startofpacket (rsp_xbar_demux_008_src1_startofpacket),                                                     //          .startofpacket
2853 
                .rp_endofpacket   (rsp_xbar_demux_008_src1_endofpacket),                                                       //          .endofpacket
2854 
                .rp_ready         (rsp_xbar_demux_008_src1_ready)                                                              //          .ready
2855 
        );
2856 
 
2857 
        altera_merlin_slave_agent #(
2858 
                .PKT_DATA_H                (31),
2859 
                .PKT_DATA_L                (0),
2860 
                .PKT_BEGIN_BURST           (87),
2861 
                .PKT_SYMBOL_W              (8),
2862 
                .PKT_BYTEEN_H              (35),
2863 
                .PKT_BYTEEN_L              (32),
2864 
                .PKT_ADDR_H                (67),
2865 
                .PKT_ADDR_L                (36),
2866 
                .PKT_TRANS_COMPRESSED_READ (68),
2867 
                .PKT_TRANS_POSTED          (69),
2868 
                .PKT_TRANS_WRITE           (70),
2869 
                .PKT_TRANS_READ            (71),
2870 
                .PKT_TRANS_LOCK            (72),
2871 
                .PKT_SRC_ID_H              (89),
2872 
                .PKT_SRC_ID_L              (89),
2873 
                .PKT_DEST_ID_H             (90),
2874 
                .PKT_DEST_ID_L             (90),
2875 
                .PKT_BURSTWRAP_H           (79),
2876 
                .PKT_BURSTWRAP_L           (77),
2877 
                .PKT_BYTE_CNT_H            (76),
2878 
                .PKT_BYTE_CNT_L            (74),
2879 
                .PKT_PROTECTION_H          (94),
2880 
                .PKT_PROTECTION_L          (92),
2881 
                .PKT_RESPONSE_STATUS_H     (100),
2882 
                .PKT_RESPONSE_STATUS_L     (99),
2883 
                .PKT_BURST_SIZE_H          (82),
2884 
                .PKT_BURST_SIZE_L          (80),
2885 
                .ST_CHANNEL_W              (2),
2886 
                .ST_DATA_W                 (101),
2887 
                .AVS_BURSTCOUNT_W          (3),
2888 
                .SUPPRESS_0_BYTEEN_CMD     (0),
2889 
                .PREVENT_FIFO_OVERFLOW     (1)
2890 
        ) onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent (
2891 
                .clk                     (clk_clk),                                                                                  //             clk.clk
2892 
                .reset                   (rst_controller_reset_out_reset),                                                           //       clk_reset.reset
2893 
                .m0_address              (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
2894 
                .m0_burstcount           (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
2895 
                .m0_byteenable           (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
2896 
                .m0_debugaccess          (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
2897 
                .m0_lock                 (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
2898 
                .m0_readdata             (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
2899 
                .m0_readdatavalid        (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
2900 
                .m0_read                 (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
2901 
                .m0_waitrequest          (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
2902 
                .m0_writedata            (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
2903 
                .m0_write                (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
2904 
                .rp_endofpacket          (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
2905 
                .rp_ready                (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
2906 
                .rp_valid                (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
2907 
                .rp_data                 (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
2908 
                .rp_startofpacket        (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
2909 
                .cp_ready                (cmd_xbar_mux_008_src_ready),                                                               //              cp.ready
2910 
                .cp_valid                (cmd_xbar_mux_008_src_valid),                                                               //                .valid
2911 
                .cp_data                 (cmd_xbar_mux_008_src_data),                                                                //                .data
2912 
                .cp_startofpacket        (cmd_xbar_mux_008_src_startofpacket),                                                       //                .startofpacket
2913 
                .cp_endofpacket          (cmd_xbar_mux_008_src_endofpacket),                                                         //                .endofpacket
2914 
                .cp_channel              (cmd_xbar_mux_008_src_channel),                                                             //                .channel
2915 
                .rf_sink_ready           (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
2916 
                .rf_sink_valid           (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
2917 
                .rf_sink_startofpacket   (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
2918 
                .rf_sink_endofpacket     (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
2919 
                .rf_sink_data            (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
2920 
                .rf_source_ready         (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
2921 
                .rf_source_valid         (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
2922 
                .rf_source_startofpacket (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
2923 
                .rf_source_endofpacket   (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
2924 
                .rf_source_data          (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
2925 
                .rdata_fifo_sink_ready   (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
2926 
                .rdata_fifo_sink_valid   (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
2927 
                .rdata_fifo_sink_data    (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
2928 
                .rdata_fifo_src_ready    (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
2929 
                .rdata_fifo_src_valid    (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
2930 
                .rdata_fifo_src_data     (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
2931 
        );
2932 
 
2933 
        altera_avalon_sc_fifo #(
2934 
                .SYMBOLS_PER_BEAT    (1),
2935 
                .BITS_PER_SYMBOL     (102),
2936 
                .FIFO_DEPTH          (2),
2937 
                .CHANNEL_WIDTH       (0),
2938 
                .ERROR_WIDTH         (0),
2939 
                .USE_PACKETS         (1),
2940 
                .USE_FILL_LEVEL      (0),
2941 
                .EMPTY_LATENCY       (1),
2942 
                .USE_MEMORY_BLOCKS   (0),
2943 
                .USE_STORE_FORWARD   (0),
2944 
                .USE_ALMOST_FULL_IF  (0),
2945 
                .USE_ALMOST_EMPTY_IF (0)
2946 
        ) onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo (
2947 
                .clk               (clk_clk),                                                                                  //       clk.clk
2948 
                .reset             (rst_controller_reset_out_reset),                                                           // clk_reset.reset
2949 
                .in_data           (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
2950 
                .in_valid          (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
2951 
                .in_ready          (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
2952 
                .in_startofpacket  (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
2953 
                .in_endofpacket    (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
2954 
                .out_data          (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
2955 
                .out_valid         (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
2956 
                .out_ready         (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
2957 
                .out_startofpacket (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
2958 
                .out_endofpacket   (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
2959 
                .csr_address       (2'b00),                                                                                    // (terminated)
2960 
                .csr_read          (1'b0),                                                                                     // (terminated)
2961 
                .csr_write         (1'b0),                                                                                     // (terminated)
2962 
                .csr_readdata      (),                                                                                         // (terminated)
2963 
                .csr_writedata     (32'b00000000000000000000000000000000),                                                     // (terminated)
2964 
                .almost_full_data  (),                                                                                         // (terminated)
2965 
                .almost_empty_data (),                                                                                         // (terminated)
2966 
                .in_empty          (1'b0),                                                                                     // (terminated)
2967 
                .out_empty         (),                                                                                         // (terminated)
2968 
                .in_error          (1'b0),                                                                                     // (terminated)
2969 
                .out_error         (),                                                                                         // (terminated)
2970 
                .in_channel        (1'b0),                                                                                     // (terminated)
2971 
                .out_channel       ()                                                                                          // (terminated)
2972 
        );
2973 
 
2974 
        nios2_sdram_addr_router addr_router (
2975 
                .sink_ready         (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_ready),         //      sink.ready
2976 
                .sink_valid         (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_valid),         //          .valid
2977 
                .sink_data          (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_data),          //          .data
2978 
                .sink_startofpacket (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
2979 
                .sink_endofpacket   (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
2980 
                .clk                (clk_clk),                                                                                     //       clk.clk
2981 
                .reset              (rst_controller_reset_out_reset),                                                              // clk_reset.reset
2982 
                .src_ready          (addr_router_src_ready),                                                                       //       src.ready
2983 
                .src_valid          (addr_router_src_valid),                                                                       //          .valid
2984 
                .src_data           (addr_router_src_data),                                                                        //          .data
2985 
                .src_channel        (addr_router_src_channel),                                                                     //          .channel
2986 
                .src_startofpacket  (addr_router_src_startofpacket),                                                               //          .startofpacket
2987 
                .src_endofpacket    (addr_router_src_endofpacket)                                                                  //          .endofpacket
2988 
        );
2989 
 
2990 
        nios2_sdram_addr_router_001 addr_router_001 (
2991 
                .sink_ready         (nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_ready),         //      sink.ready
2992 
                .sink_valid         (nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_valid),         //          .valid
2993 
                .sink_data          (nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_data),          //          .data
2994 
                .sink_startofpacket (nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
2995 
                .sink_endofpacket   (nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
2996 
                .clk                (clk_clk),                                                                              //       clk.clk
2997 
                .reset              (rst_controller_reset_out_reset),                                                       // clk_reset.reset
2998 
                .src_ready          (addr_router_001_src_ready),                                                            //       src.ready
2999 
                .src_valid          (addr_router_001_src_valid),                                                            //          .valid
3000 
                .src_data           (addr_router_001_src_data),                                                             //          .data
3001 
                .src_channel        (addr_router_001_src_channel),                                                          //          .channel
3002 
                .src_startofpacket  (addr_router_001_src_startofpacket),                                                    //          .startofpacket
3003 
                .src_endofpacket    (addr_router_001_src_endofpacket)                                                       //          .endofpacket
3004 
        );
3005 
 
3006 
        nios2_sdram_id_router id_router (
3007 
                .sink_ready         (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
3008 
                .sink_valid         (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
3009 
                .sink_data          (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
3010 
                .sink_startofpacket (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
3011 
                .sink_endofpacket   (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
3012 
                .clk                (clk_clk),                                                                                   //       clk.clk
3013 
                .reset              (rst_controller_reset_out_reset),                                                            // clk_reset.reset
3014 
                .src_ready          (id_router_src_ready),                                                                       //       src.ready
3015 
                .src_valid          (id_router_src_valid),                                                                       //          .valid
3016 
                .src_data           (id_router_src_data),                                                                        //          .data
3017 
                .src_channel        (id_router_src_channel),                                                                     //          .channel
3018 
                .src_startofpacket  (id_router_src_startofpacket),                                                               //          .startofpacket
3019 
                .src_endofpacket    (id_router_src_endofpacket)                                                                  //          .endofpacket
3020 
        );
3021 
 
3022 
        nios2_sdram_id_router_001 id_router_001 (
3023 
                .sink_ready         (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
3024 
                .sink_valid         (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
3025 
                .sink_data          (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
3026 
                .sink_startofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
3027 
                .sink_endofpacket   (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
3028 
                .clk                (clk_clk),                                                               //       clk.clk
3029 
                .reset              (rst_controller_reset_out_reset),                                        // clk_reset.reset
3030 
                .src_ready          (id_router_001_src_ready),                                               //       src.ready
3031 
                .src_valid          (id_router_001_src_valid),                                               //          .valid
3032 
                .src_data           (id_router_001_src_data),                                                //          .data
3033 
                .src_channel        (id_router_001_src_channel),                                             //          .channel
3034 
                .src_startofpacket  (id_router_001_src_startofpacket),                                       //          .startofpacket
3035 
                .src_endofpacket    (id_router_001_src_endofpacket)                                          //          .endofpacket
3036 
        );
3037 
 
3038 
        nios2_sdram_id_router_002 id_router_002 (
3039 
                .sink_ready         (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
3040 
                .sink_valid         (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
3041 
                .sink_data          (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
3042 
                .sink_startofpacket (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
3043 
                .sink_endofpacket   (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
3044 
                .clk                (clk_clk),                                                                                  //       clk.clk
3045 
                .reset              (rst_controller_reset_out_reset),                                                           // clk_reset.reset
3046 
                .src_ready          (id_router_002_src_ready),                                                                  //       src.ready
3047 
                .src_valid          (id_router_002_src_valid),                                                                  //          .valid
3048 
                .src_data           (id_router_002_src_data),                                                                   //          .data
3049 
                .src_channel        (id_router_002_src_channel),                                                                //          .channel
3050 
                .src_startofpacket  (id_router_002_src_startofpacket),                                                          //          .startofpacket
3051 
                .src_endofpacket    (id_router_002_src_endofpacket)                                                             //          .endofpacket
3052 
        );
3053 
 
3054 
        nios2_sdram_id_router_002 id_router_003 (
3055 
                .sink_ready         (timer_1_s1_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
3056 
                .sink_valid         (timer_1_s1_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
3057 
                .sink_data          (timer_1_s1_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
3058 
                .sink_startofpacket (timer_1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
3059 
                .sink_endofpacket   (timer_1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
3060 
                .clk                (clk_clk),                                                               //       clk.clk
3061 
                .reset              (rst_controller_reset_out_reset),                                        // clk_reset.reset
3062 
                .src_ready          (id_router_003_src_ready),                                               //       src.ready
3063 
                .src_valid          (id_router_003_src_valid),                                               //          .valid
3064 
                .src_data           (id_router_003_src_data),                                                //          .data
3065 
                .src_channel        (id_router_003_src_channel),                                             //          .channel
3066 
                .src_startofpacket  (id_router_003_src_startofpacket),                                       //          .startofpacket
3067 
                .src_endofpacket    (id_router_003_src_endofpacket)                                          //          .endofpacket
3068 
        );
3069 
 
3070 
        nios2_sdram_id_router_002 id_router_004 (
3071 
                .sink_ready         (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
3072 
                .sink_valid         (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
3073 
                .sink_data          (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
3074 
                .sink_startofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
3075 
                .sink_endofpacket   (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
3076 
                .clk                (clk_clk),                                                               //       clk.clk
3077 
                .reset              (rst_controller_reset_out_reset),                                        // clk_reset.reset
3078 
                .src_ready          (id_router_004_src_ready),                                               //       src.ready
3079 
                .src_valid          (id_router_004_src_valid),                                               //          .valid
3080 
                .src_data           (id_router_004_src_data),                                                //          .data
3081 
                .src_channel        (id_router_004_src_channel),                                             //          .channel
3082 
                .src_startofpacket  (id_router_004_src_startofpacket),                                       //          .startofpacket
3083 
                .src_endofpacket    (id_router_004_src_endofpacket)                                          //          .endofpacket
3084 
        );
3085 
 
3086 
        nios2_sdram_id_router_002 id_router_005 (
3087 
                .sink_ready         (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
3088 
                .sink_valid         (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
3089 
                .sink_data          (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
3090 
                .sink_startofpacket (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
3091 
                .sink_endofpacket   (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
3092 
                .clk                (clk_clk),                                                                               //       clk.clk
3093 
                .reset              (rst_controller_reset_out_reset),                                                        // clk_reset.reset
3094 
                .src_ready          (id_router_005_src_ready),                                                               //       src.ready
3095 
                .src_valid          (id_router_005_src_valid),                                                               //          .valid
3096 
                .src_data           (id_router_005_src_data),                                                                //          .data
3097 
                .src_channel        (id_router_005_src_channel),                                                             //          .channel
3098 
                .src_startofpacket  (id_router_005_src_startofpacket),                                                       //          .startofpacket
3099 
                .src_endofpacket    (id_router_005_src_endofpacket)                                                          //          .endofpacket
3100 
        );
3101 
 
3102 
        nios2_sdram_id_router_002 id_router_006 (
3103 
                .sink_ready         (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
3104 
                .sink_valid         (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
3105 
                .sink_data          (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
3106 
                .sink_startofpacket (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
3107 
                .sink_endofpacket   (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
3108 
                .clk                (clk_clk),                                                                        //       clk.clk
3109 
                .reset              (rst_controller_reset_out_reset),                                                 // clk_reset.reset
3110 
                .src_ready          (id_router_006_src_ready),                                                        //       src.ready
3111 
                .src_valid          (id_router_006_src_valid),                                                        //          .valid
3112 
                .src_data           (id_router_006_src_data),                                                         //          .data
3113 
                .src_channel        (id_router_006_src_channel),                                                      //          .channel
3114 
                .src_startofpacket  (id_router_006_src_startofpacket),                                                //          .startofpacket
3115 
                .src_endofpacket    (id_router_006_src_endofpacket)                                                   //          .endofpacket
3116 
        );
3117 
 
3118 
        nios2_sdram_id_router_002 id_router_007 (
3119 
                .sink_ready         (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
3120 
                .sink_valid         (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
3121 
                .sink_data          (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
3122 
                .sink_startofpacket (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
3123 
                .sink_endofpacket   (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
3124 
                .clk                (clk_clk),                                                                                 //       clk.clk
3125 
                .reset              (rst_controller_reset_out_reset),                                                          // clk_reset.reset
3126 
                .src_ready          (id_router_007_src_ready),                                                                 //       src.ready
3127 
                .src_valid          (id_router_007_src_valid),                                                                 //          .valid
3128 
                .src_data           (id_router_007_src_data),                                                                  //          .data
3129 
                .src_channel        (id_router_007_src_channel),                                                               //          .channel
3130 
                .src_startofpacket  (id_router_007_src_startofpacket),                                                         //          .startofpacket
3131 
                .src_endofpacket    (id_router_007_src_endofpacket)                                                            //          .endofpacket
3132 
        );
3133 
 
3134 
        nios2_sdram_addr_router_002 addr_router_002 (
3135 
                .sink_ready         (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_ready),         //      sink.ready
3136 
                .sink_valid         (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_valid),         //          .valid
3137 
                .sink_data          (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_data),          //          .data
3138 
                .sink_startofpacket (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
3139 
                .sink_endofpacket   (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
3140 
                .clk                (clk_clk),                                                                                 //       clk.clk
3141 
                .reset              (rst_controller_reset_out_reset),                                                          // clk_reset.reset
3142 
                .src_ready          (addr_router_002_src_ready),                                                               //       src.ready
3143 
                .src_valid          (addr_router_002_src_valid),                                                               //          .valid
3144 
                .src_data           (addr_router_002_src_data),                                                                //          .data
3145 
                .src_channel        (addr_router_002_src_channel),                                                             //          .channel
3146 
                .src_startofpacket  (addr_router_002_src_startofpacket),                                                       //          .startofpacket
3147 
                .src_endofpacket    (addr_router_002_src_endofpacket)                                                          //          .endofpacket
3148 
        );
3149 
 
3150 
        nios2_sdram_addr_router_002 addr_router_003 (
3151 
                .sink_ready         (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_ready),         //      sink.ready
3152 
                .sink_valid         (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_valid),         //          .valid
3153 
                .sink_data          (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_data),          //          .data
3154 
                .sink_startofpacket (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
3155 
                .sink_endofpacket   (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
3156 
                .clk                (clk_clk),                                                                                   //       clk.clk
3157 
                .reset              (rst_controller_reset_out_reset),                                                            // clk_reset.reset
3158 
                .src_ready          (addr_router_003_src_ready),                                                                 //       src.ready
3159 
                .src_valid          (addr_router_003_src_valid),                                                                 //          .valid
3160 
                .src_data           (addr_router_003_src_data),                                                                  //          .data
3161 
                .src_channel        (addr_router_003_src_channel),                                                               //          .channel
3162 
                .src_startofpacket  (addr_router_003_src_startofpacket),                                                         //          .startofpacket
3163 
                .src_endofpacket    (addr_router_003_src_endofpacket)                                                            //          .endofpacket
3164 
        );
3165 
 
3166 
        nios2_sdram_id_router_008 id_router_008 (
3167 
                .sink_ready         (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
3168 
                .sink_valid         (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
3169 
                .sink_data          (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
3170 
                .sink_startofpacket (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
3171 
                .sink_endofpacket   (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
3172 
                .clk                (clk_clk),                                                                        //       clk.clk
3173 
                .reset              (rst_controller_reset_out_reset),                                                 // clk_reset.reset
3174 
                .src_ready          (id_router_008_src_ready),                                                        //       src.ready
3175 
                .src_valid          (id_router_008_src_valid),                                                        //          .valid
3176 
                .src_data           (id_router_008_src_data),                                                         //          .data
3177 
                .src_channel        (id_router_008_src_channel),                                                      //          .channel
3178 
                .src_startofpacket  (id_router_008_src_startofpacket),                                                //          .startofpacket
3179 
                .src_endofpacket    (id_router_008_src_endofpacket)                                                   //          .endofpacket
3180 
        );
3181 
 
3182 
        altera_merlin_traffic_limiter #(
3183 
                .PKT_DEST_ID_H             (88),
3184 
                .PKT_DEST_ID_L             (86),
3185 
                .PKT_TRANS_POSTED          (63),
3186 
                .PKT_TRANS_WRITE           (64),
3187 
                .MAX_OUTSTANDING_RESPONSES (9),
3188 
                .PIPELINED                 (0),
3189 
                .ST_DATA_W                 (99),
3190 
                .ST_CHANNEL_W              (8),
3191 
                .VALID_WIDTH               (8),
3192 
                .ENFORCE_ORDER             (1),
3193 
                .PREVENT_HAZARDS           (0),
3194 
                .PKT_BYTE_CNT_H            (70),
3195 
                .PKT_BYTE_CNT_L            (68),
3196 
                .PKT_BYTEEN_H              (35),
3197 
                .PKT_BYTEEN_L              (32)
3198 
        ) limiter (
3199 
                .clk                    (clk_clk),                        //       clk.clk
3200 
                .reset                  (rst_controller_reset_out_reset), // clk_reset.reset
3201 
                .cmd_sink_ready         (addr_router_src_ready),          //  cmd_sink.ready
3202 
                .cmd_sink_valid         (addr_router_src_valid),          //          .valid
3203 
                .cmd_sink_data          (addr_router_src_data),           //          .data
3204 
                .cmd_sink_channel       (addr_router_src_channel),        //          .channel
3205 
                .cmd_sink_startofpacket (addr_router_src_startofpacket),  //          .startofpacket
3206 
                .cmd_sink_endofpacket   (addr_router_src_endofpacket),    //          .endofpacket
3207 
                .cmd_src_ready          (limiter_cmd_src_ready),          //   cmd_src.ready
3208 
                .cmd_src_data           (limiter_cmd_src_data),           //          .data
3209 
                .cmd_src_channel        (limiter_cmd_src_channel),        //          .channel
3210 
                .cmd_src_startofpacket  (limiter_cmd_src_startofpacket),  //          .startofpacket
3211 
                .cmd_src_endofpacket    (limiter_cmd_src_endofpacket),    //          .endofpacket
3212 
                .rsp_sink_ready         (rsp_xbar_mux_src_ready),         //  rsp_sink.ready
3213 
                .rsp_sink_valid         (rsp_xbar_mux_src_valid),         //          .valid
3214 
                .rsp_sink_channel       (rsp_xbar_mux_src_channel),       //          .channel
3215 
                .rsp_sink_data          (rsp_xbar_mux_src_data),          //          .data
3216 
                .rsp_sink_startofpacket (rsp_xbar_mux_src_startofpacket), //          .startofpacket
3217 
                .rsp_sink_endofpacket   (rsp_xbar_mux_src_endofpacket),   //          .endofpacket
3218 
                .rsp_src_ready          (limiter_rsp_src_ready),          //   rsp_src.ready
3219 
                .rsp_src_valid          (limiter_rsp_src_valid),          //          .valid
3220 
                .rsp_src_data           (limiter_rsp_src_data),           //          .data
3221 
                .rsp_src_channel        (limiter_rsp_src_channel),        //          .channel
3222 
                .rsp_src_startofpacket  (limiter_rsp_src_startofpacket),  //          .startofpacket
3223 
                .rsp_src_endofpacket    (limiter_rsp_src_endofpacket),    //          .endofpacket
3224 
                .cmd_src_valid          (limiter_cmd_valid_data)          // cmd_valid.data
3225 
        );
3226 
 
3227 
        altera_merlin_traffic_limiter #(
3228 
                .PKT_DEST_ID_H             (88),
3229 
                .PKT_DEST_ID_L             (86),
3230 
                .PKT_TRANS_POSTED          (63),
3231 
                .PKT_TRANS_WRITE           (64),
3232 
                .MAX_OUTSTANDING_RESPONSES (9),
3233 
                .PIPELINED                 (0),
3234 
                .ST_DATA_W                 (99),
3235 
                .ST_CHANNEL_W              (8),
3236 
                .VALID_WIDTH               (8),
3237 
                .ENFORCE_ORDER             (1),
3238 
                .PREVENT_HAZARDS           (0),
3239 
                .PKT_BYTE_CNT_H            (70),
3240 
                .PKT_BYTE_CNT_L            (68),
3241 
                .PKT_BYTEEN_H              (35),
3242 
                .PKT_BYTEEN_L              (32)
3243 
        ) limiter_001 (
3244 
                .clk                    (clk_clk),                            //       clk.clk
3245 
                .reset                  (rst_controller_reset_out_reset),     // clk_reset.reset
3246 
                .cmd_sink_ready         (addr_router_001_src_ready),          //  cmd_sink.ready
3247 
                .cmd_sink_valid         (addr_router_001_src_valid),          //          .valid
3248 
                .cmd_sink_data          (addr_router_001_src_data),           //          .data
3249 
                .cmd_sink_channel       (addr_router_001_src_channel),        //          .channel
3250 
                .cmd_sink_startofpacket (addr_router_001_src_startofpacket),  //          .startofpacket
3251 
                .cmd_sink_endofpacket   (addr_router_001_src_endofpacket),    //          .endofpacket
3252 
                .cmd_src_ready          (limiter_001_cmd_src_ready),          //   cmd_src.ready
3253 
                .cmd_src_data           (limiter_001_cmd_src_data),           //          .data
3254 
                .cmd_src_channel        (limiter_001_cmd_src_channel),        //          .channel
3255 
                .cmd_src_startofpacket  (limiter_001_cmd_src_startofpacket),  //          .startofpacket
3256 
                .cmd_src_endofpacket    (limiter_001_cmd_src_endofpacket),    //          .endofpacket
3257 
                .rsp_sink_ready         (rsp_xbar_mux_001_src_ready),         //  rsp_sink.ready
3258 
                .rsp_sink_valid         (rsp_xbar_mux_001_src_valid),         //          .valid
3259 
                .rsp_sink_channel       (rsp_xbar_mux_001_src_channel),       //          .channel
3260 
                .rsp_sink_data          (rsp_xbar_mux_001_src_data),          //          .data
3261 
                .rsp_sink_startofpacket (rsp_xbar_mux_001_src_startofpacket), //          .startofpacket
3262 
                .rsp_sink_endofpacket   (rsp_xbar_mux_001_src_endofpacket),   //          .endofpacket
3263 
                .rsp_src_ready          (limiter_001_rsp_src_ready),          //   rsp_src.ready
3264 
                .rsp_src_valid          (limiter_001_rsp_src_valid),          //          .valid
3265 
                .rsp_src_data           (limiter_001_rsp_src_data),           //          .data
3266 
                .rsp_src_channel        (limiter_001_rsp_src_channel),        //          .channel
3267 
                .rsp_src_startofpacket  (limiter_001_rsp_src_startofpacket),  //          .startofpacket
3268 
                .rsp_src_endofpacket    (limiter_001_rsp_src_endofpacket),    //          .endofpacket
3269 
                .cmd_src_valid          (limiter_001_cmd_valid_data)          // cmd_valid.data
3270 
        );
3271 
 
3272 
        altera_merlin_burst_adapter #(
3273 
                .PKT_ADDR_H                (43),
3274 
                .PKT_ADDR_L                (18),
3275 
                .PKT_BEGIN_BURST           (63),
3276 
                .PKT_BYTE_CNT_H            (52),
3277 
                .PKT_BYTE_CNT_L            (50),
3278 
                .PKT_BYTEEN_H              (17),
3279 
                .PKT_BYTEEN_L              (16),
3280 
                .PKT_BURST_SIZE_H          (58),
3281 
                .PKT_BURST_SIZE_L          (56),
3282 
                .PKT_BURST_TYPE_H          (60),
3283 
                .PKT_BURST_TYPE_L          (59),
3284 
                .PKT_BURSTWRAP_H           (55),
3285 
                .PKT_BURSTWRAP_L           (53),
3286 
                .PKT_TRANS_COMPRESSED_READ (44),
3287 
                .PKT_TRANS_WRITE           (46),
3288 
                .PKT_TRANS_READ            (47),
3289 
                .OUT_NARROW_SIZE           (0),
3290 
                .IN_NARROW_SIZE            (0),
3291 
                .OUT_FIXED                 (0),
3292 
                .OUT_COMPLETE_WRAP         (0),
3293 
                .ST_DATA_W                 (81),
3294 
                .ST_CHANNEL_W              (8),
3295 
                .OUT_BYTE_CNT_H            (51),
3296 
                .OUT_BURSTWRAP_H           (55),
3297 
                .COMPRESSED_READ_SUPPORT   (0),
3298 
                .BYTEENABLE_SYNTHESIS      (0),
3299 
                .PIPE_INPUTS               (0),
3300 
                .NO_WRAP_SUPPORT           (0),
3301 
                .BURSTWRAP_CONST_MASK      (3),
3302 
                .BURSTWRAP_CONST_VALUE     (3)
3303 
        ) burst_adapter (
3304 
                .clk                   (clk_clk),                             //       cr0.clk
3305 
                .reset                 (rst_controller_reset_out_reset),      // cr0_reset.reset
3306 
                .sink0_valid           (width_adapter_src_valid),             //     sink0.valid
3307 
                .sink0_data            (width_adapter_src_data),              //          .data
3308 
                .sink0_channel         (width_adapter_src_channel),           //          .channel
3309 
                .sink0_startofpacket   (width_adapter_src_startofpacket),     //          .startofpacket
3310 
                .sink0_endofpacket     (width_adapter_src_endofpacket),       //          .endofpacket
3311 
                .sink0_ready           (width_adapter_src_ready),             //          .ready
3312 
                .source0_valid         (burst_adapter_source0_valid),         //   source0.valid
3313 
                .source0_data          (burst_adapter_source0_data),          //          .data
3314 
                .source0_channel       (burst_adapter_source0_channel),       //          .channel
3315 
                .source0_startofpacket (burst_adapter_source0_startofpacket), //          .startofpacket
3316 
                .source0_endofpacket   (burst_adapter_source0_endofpacket),   //          .endofpacket
3317 
                .source0_ready         (burst_adapter_source0_ready)          //          .ready
3318 
        );
3319 
 
3320 
        altera_reset_controller #(
3321 
                .NUM_RESET_INPUTS        (1),
3322 
                .OUTPUT_RESET_SYNC_EDGES ("deassert"),
3323 
                .SYNC_DEPTH              (2)
3324 
        ) rst_controller (
3325 
                .reset_in0  (~reset_reset_n),                 // reset_in0.reset
3326 
                .clk        (clk_clk),                        //       clk.clk
3327 
                .reset_out  (rst_controller_reset_out_reset), // reset_out.reset
3328 
                .reset_in1  (1'b0),                           // (terminated)
3329 
                .reset_in2  (1'b0),                           // (terminated)
3330 
                .reset_in3  (1'b0),                           // (terminated)
3331 
                .reset_in4  (1'b0),                           // (terminated)
3332 
                .reset_in5  (1'b0),                           // (terminated)
3333 
                .reset_in6  (1'b0),                           // (terminated)
3334 
                .reset_in7  (1'b0),                           // (terminated)
3335 
                .reset_in8  (1'b0),                           // (terminated)
3336 
                .reset_in9  (1'b0),                           // (terminated)
3337 
                .reset_in10 (1'b0),                           // (terminated)
3338 
                .reset_in11 (1'b0),                           // (terminated)
3339 
                .reset_in12 (1'b0),                           // (terminated)
3340 
                .reset_in13 (1'b0),                           // (terminated)
3341 
                .reset_in14 (1'b0),                           // (terminated)
3342 
                .reset_in15 (1'b0)                            // (terminated)
3343 
        );
3344 
 
3345 
        nios2_sdram_cmd_xbar_demux cmd_xbar_demux (
3346 
                .clk                (clk_clk),                           //        clk.clk
3347 
                .reset              (rst_controller_reset_out_reset),    //  clk_reset.reset
3348 
                .sink_ready         (limiter_cmd_src_ready),             //       sink.ready
3349 
                .sink_channel       (limiter_cmd_src_channel),           //           .channel
3350 
                .sink_data          (limiter_cmd_src_data),              //           .data
3351 
                .sink_startofpacket (limiter_cmd_src_startofpacket),     //           .startofpacket
3352 
                .sink_endofpacket   (limiter_cmd_src_endofpacket),       //           .endofpacket
3353 
                .sink_valid         (limiter_cmd_valid_data),            // sink_valid.data
3354 
                .src0_ready         (cmd_xbar_demux_src0_ready),         //       src0.ready
3355 
                .src0_valid         (cmd_xbar_demux_src0_valid),         //           .valid
3356 
                .src0_data          (cmd_xbar_demux_src0_data),          //           .data
3357 
                .src0_channel       (cmd_xbar_demux_src0_channel),       //           .channel
3358 
                .src0_startofpacket (cmd_xbar_demux_src0_startofpacket), //           .startofpacket
3359 
                .src0_endofpacket   (cmd_xbar_demux_src0_endofpacket),   //           .endofpacket
3360 
                .src1_ready         (cmd_xbar_demux_src1_ready),         //       src1.ready
3361 
                .src1_valid         (cmd_xbar_demux_src1_valid),         //           .valid
3362 
                .src1_data          (cmd_xbar_demux_src1_data),          //           .data
3363 
                .src1_channel       (cmd_xbar_demux_src1_channel),       //           .channel
3364 
                .src1_startofpacket (cmd_xbar_demux_src1_startofpacket), //           .startofpacket
3365 
                .src1_endofpacket   (cmd_xbar_demux_src1_endofpacket)    //           .endofpacket
3366 
        );
3367 
 
3368 
        nios2_sdram_cmd_xbar_demux_001 cmd_xbar_demux_001 (
3369 
                .clk                (clk_clk),                               //        clk.clk
3370 
                .reset              (rst_controller_reset_out_reset),        //  clk_reset.reset
3371 
                .sink_ready         (limiter_001_cmd_src_ready),             //       sink.ready
3372 
                .sink_channel       (limiter_001_cmd_src_channel),           //           .channel
3373 
                .sink_data          (limiter_001_cmd_src_data),              //           .data
3374 
                .sink_startofpacket (limiter_001_cmd_src_startofpacket),     //           .startofpacket
3375 
                .sink_endofpacket   (limiter_001_cmd_src_endofpacket),       //           .endofpacket
3376 
                .sink_valid         (limiter_001_cmd_valid_data),            // sink_valid.data
3377 
                .src0_ready         (cmd_xbar_demux_001_src0_ready),         //       src0.ready
3378 
                .src0_valid         (cmd_xbar_demux_001_src0_valid),         //           .valid
3379 
                .src0_data          (cmd_xbar_demux_001_src0_data),          //           .data
3380 
                .src0_channel       (cmd_xbar_demux_001_src0_channel),       //           .channel
3381 
                .src0_startofpacket (cmd_xbar_demux_001_src0_startofpacket), //           .startofpacket
3382 
                .src0_endofpacket   (cmd_xbar_demux_001_src0_endofpacket),   //           .endofpacket
3383 
                .src1_ready         (cmd_xbar_demux_001_src1_ready),         //       src1.ready
3384 
                .src1_valid         (cmd_xbar_demux_001_src1_valid),         //           .valid
3385 
                .src1_data          (cmd_xbar_demux_001_src1_data),          //           .data
3386 
                .src1_channel       (cmd_xbar_demux_001_src1_channel),       //           .channel
3387 
                .src1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), //           .startofpacket
3388 
                .src1_endofpacket   (cmd_xbar_demux_001_src1_endofpacket),   //           .endofpacket
3389 
                .src2_ready         (cmd_xbar_demux_001_src2_ready),         //       src2.ready
3390 
                .src2_valid         (cmd_xbar_demux_001_src2_valid),         //           .valid
3391 
                .src2_data          (cmd_xbar_demux_001_src2_data),          //           .data
3392 
                .src2_channel       (cmd_xbar_demux_001_src2_channel),       //           .channel
3393 
                .src2_startofpacket (cmd_xbar_demux_001_src2_startofpacket), //           .startofpacket
3394 
                .src2_endofpacket   (cmd_xbar_demux_001_src2_endofpacket),   //           .endofpacket
3395 
                .src3_ready         (cmd_xbar_demux_001_src3_ready),         //       src3.ready
3396 
                .src3_valid         (cmd_xbar_demux_001_src3_valid),         //           .valid
3397 
                .src3_data          (cmd_xbar_demux_001_src3_data),          //           .data
3398 
                .src3_channel       (cmd_xbar_demux_001_src3_channel),       //           .channel
3399 
                .src3_startofpacket (cmd_xbar_demux_001_src3_startofpacket), //           .startofpacket
3400 
                .src3_endofpacket   (cmd_xbar_demux_001_src3_endofpacket),   //           .endofpacket
3401 
                .src4_ready         (cmd_xbar_demux_001_src4_ready),         //       src4.ready
3402 
                .src4_valid         (cmd_xbar_demux_001_src4_valid),         //           .valid
3403 
                .src4_data          (cmd_xbar_demux_001_src4_data),          //           .data
3404 
                .src4_channel       (cmd_xbar_demux_001_src4_channel),       //           .channel
3405 
                .src4_startofpacket (cmd_xbar_demux_001_src4_startofpacket), //           .startofpacket
3406 
                .src4_endofpacket   (cmd_xbar_demux_001_src4_endofpacket),   //           .endofpacket
3407 
                .src5_ready         (cmd_xbar_demux_001_src5_ready),         //       src5.ready
3408 
                .src5_valid         (cmd_xbar_demux_001_src5_valid),         //           .valid
3409 
                .src5_data          (cmd_xbar_demux_001_src5_data),          //           .data
3410 
                .src5_channel       (cmd_xbar_demux_001_src5_channel),       //           .channel
3411 
                .src5_startofpacket (cmd_xbar_demux_001_src5_startofpacket), //           .startofpacket
3412 
                .src5_endofpacket   (cmd_xbar_demux_001_src5_endofpacket),   //           .endofpacket
3413 
                .src6_ready         (cmd_xbar_demux_001_src6_ready),         //       src6.ready
3414 
                .src6_valid         (cmd_xbar_demux_001_src6_valid),         //           .valid
3415 
                .src6_data          (cmd_xbar_demux_001_src6_data),          //           .data
3416 
                .src6_channel       (cmd_xbar_demux_001_src6_channel),       //           .channel
3417 
                .src6_startofpacket (cmd_xbar_demux_001_src6_startofpacket), //           .startofpacket
3418 
                .src6_endofpacket   (cmd_xbar_demux_001_src6_endofpacket),   //           .endofpacket
3419 
                .src7_ready         (cmd_xbar_demux_001_src7_ready),         //       src7.ready
3420 
                .src7_valid         (cmd_xbar_demux_001_src7_valid),         //           .valid
3421 
                .src7_data          (cmd_xbar_demux_001_src7_data),          //           .data
3422 
                .src7_channel       (cmd_xbar_demux_001_src7_channel),       //           .channel
3423 
                .src7_startofpacket (cmd_xbar_demux_001_src7_startofpacket), //           .startofpacket
3424 
                .src7_endofpacket   (cmd_xbar_demux_001_src7_endofpacket)    //           .endofpacket
3425 
        );
3426 
 
3427 
        nios2_sdram_cmd_xbar_mux cmd_xbar_mux (
3428 
                .clk                 (clk_clk),                               //       clk.clk
3429 
                .reset               (rst_controller_reset_out_reset),        // clk_reset.reset
3430 
                .src_ready           (cmd_xbar_mux_src_ready),                //       src.ready
3431 
                .src_valid           (cmd_xbar_mux_src_valid),                //          .valid
3432 
                .src_data            (cmd_xbar_mux_src_data),                 //          .data
3433 
                .src_channel         (cmd_xbar_mux_src_channel),              //          .channel
3434 
                .src_startofpacket   (cmd_xbar_mux_src_startofpacket),        //          .startofpacket
3435 
                .src_endofpacket     (cmd_xbar_mux_src_endofpacket),          //          .endofpacket
3436 
                .sink0_ready         (cmd_xbar_demux_src0_ready),             //     sink0.ready
3437 
                .sink0_valid         (cmd_xbar_demux_src0_valid),             //          .valid
3438 
                .sink0_channel       (cmd_xbar_demux_src0_channel),           //          .channel
3439 
                .sink0_data          (cmd_xbar_demux_src0_data),              //          .data
3440 
                .sink0_startofpacket (cmd_xbar_demux_src0_startofpacket),     //          .startofpacket
3441 
                .sink0_endofpacket   (cmd_xbar_demux_src0_endofpacket),       //          .endofpacket
3442 
                .sink1_ready         (cmd_xbar_demux_001_src0_ready),         //     sink1.ready
3443 
                .sink1_valid         (cmd_xbar_demux_001_src0_valid),         //          .valid
3444 
                .sink1_channel       (cmd_xbar_demux_001_src0_channel),       //          .channel
3445 
                .sink1_data          (cmd_xbar_demux_001_src0_data),          //          .data
3446 
                .sink1_startofpacket (cmd_xbar_demux_001_src0_startofpacket), //          .startofpacket
3447 
                .sink1_endofpacket   (cmd_xbar_demux_001_src0_endofpacket)    //          .endofpacket
3448 
        );
3449 
 
3450 
        nios2_sdram_cmd_xbar_mux cmd_xbar_mux_001 (
3451 
                .clk                 (clk_clk),                               //       clk.clk
3452 
                .reset               (rst_controller_reset_out_reset),        // clk_reset.reset
3453 
                .src_ready           (cmd_xbar_mux_001_src_ready),            //       src.ready
3454 
                .src_valid           (cmd_xbar_mux_001_src_valid),            //          .valid
3455 
                .src_data            (cmd_xbar_mux_001_src_data),             //          .data
3456 
                .src_channel         (cmd_xbar_mux_001_src_channel),          //          .channel
3457 
                .src_startofpacket   (cmd_xbar_mux_001_src_startofpacket),    //          .startofpacket
3458 
                .src_endofpacket     (cmd_xbar_mux_001_src_endofpacket),      //          .endofpacket
3459 
                .sink0_ready         (cmd_xbar_demux_src1_ready),             //     sink0.ready
3460 
                .sink0_valid         (cmd_xbar_demux_src1_valid),             //          .valid
3461 
                .sink0_channel       (cmd_xbar_demux_src1_channel),           //          .channel
3462 
                .sink0_data          (cmd_xbar_demux_src1_data),              //          .data
3463 
                .sink0_startofpacket (cmd_xbar_demux_src1_startofpacket),     //          .startofpacket
3464 
                .sink0_endofpacket   (cmd_xbar_demux_src1_endofpacket),       //          .endofpacket
3465 
                .sink1_ready         (cmd_xbar_demux_001_src1_ready),         //     sink1.ready
3466 
                .sink1_valid         (cmd_xbar_demux_001_src1_valid),         //          .valid
3467 
                .sink1_channel       (cmd_xbar_demux_001_src1_channel),       //          .channel
3468 
                .sink1_data          (cmd_xbar_demux_001_src1_data),          //          .data
3469 
                .sink1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), //          .startofpacket
3470 
                .sink1_endofpacket   (cmd_xbar_demux_001_src1_endofpacket)    //          .endofpacket
3471 
        );
3472 
 
3473 
        nios2_sdram_rsp_xbar_demux rsp_xbar_demux (
3474 
                .clk                (clk_clk),                           //       clk.clk
3475 
                .reset              (rst_controller_reset_out_reset),    // clk_reset.reset
3476 
                .sink_ready         (id_router_src_ready),               //      sink.ready
3477 
                .sink_channel       (id_router_src_channel),             //          .channel
3478 
                .sink_data          (id_router_src_data),                //          .data
3479 
                .sink_startofpacket (id_router_src_startofpacket),       //          .startofpacket
3480 
                .sink_endofpacket   (id_router_src_endofpacket),         //          .endofpacket
3481 
                .sink_valid         (id_router_src_valid),               //          .valid
3482 
                .src0_ready         (rsp_xbar_demux_src0_ready),         //      src0.ready
3483 
                .src0_valid         (rsp_xbar_demux_src0_valid),         //          .valid
3484 
                .src0_data          (rsp_xbar_demux_src0_data),          //          .data
3485 
                .src0_channel       (rsp_xbar_demux_src0_channel),       //          .channel
3486 
                .src0_startofpacket (rsp_xbar_demux_src0_startofpacket), //          .startofpacket
3487 
                .src0_endofpacket   (rsp_xbar_demux_src0_endofpacket),   //          .endofpacket
3488 
                .src1_ready         (rsp_xbar_demux_src1_ready),         //      src1.ready
3489 
                .src1_valid         (rsp_xbar_demux_src1_valid),         //          .valid
3490 
                .src1_data          (rsp_xbar_demux_src1_data),          //          .data
3491 
                .src1_channel       (rsp_xbar_demux_src1_channel),       //          .channel
3492 
                .src1_startofpacket (rsp_xbar_demux_src1_startofpacket), //          .startofpacket
3493 
                .src1_endofpacket   (rsp_xbar_demux_src1_endofpacket)    //          .endofpacket
3494 
        );
3495 
 
3496 
        nios2_sdram_rsp_xbar_demux rsp_xbar_demux_001 (
3497 
                .clk                (clk_clk),                               //       clk.clk
3498 
                .reset              (rst_controller_reset_out_reset),        // clk_reset.reset
3499 
                .sink_ready         (width_adapter_001_src_ready),           //      sink.ready
3500 
                .sink_channel       (width_adapter_001_src_channel),         //          .channel
3501 
                .sink_data          (width_adapter_001_src_data),            //          .data
3502 
                .sink_startofpacket (width_adapter_001_src_startofpacket),   //          .startofpacket
3503 
                .sink_endofpacket   (width_adapter_001_src_endofpacket),     //          .endofpacket
3504 
                .sink_valid         (width_adapter_001_src_valid),           //          .valid
3505 
                .src0_ready         (rsp_xbar_demux_001_src0_ready),         //      src0.ready
3506 
                .src0_valid         (rsp_xbar_demux_001_src0_valid),         //          .valid
3507 
                .src0_data          (rsp_xbar_demux_001_src0_data),          //          .data
3508 
                .src0_channel       (rsp_xbar_demux_001_src0_channel),       //          .channel
3509 
                .src0_startofpacket (rsp_xbar_demux_001_src0_startofpacket), //          .startofpacket
3510 
                .src0_endofpacket   (rsp_xbar_demux_001_src0_endofpacket),   //          .endofpacket
3511 
                .src1_ready         (rsp_xbar_demux_001_src1_ready),         //      src1.ready
3512 
                .src1_valid         (rsp_xbar_demux_001_src1_valid),         //          .valid
3513 
                .src1_data          (rsp_xbar_demux_001_src1_data),          //          .data
3514 
                .src1_channel       (rsp_xbar_demux_001_src1_channel),       //          .channel
3515 
                .src1_startofpacket (rsp_xbar_demux_001_src1_startofpacket), //          .startofpacket
3516 
                .src1_endofpacket   (rsp_xbar_demux_001_src1_endofpacket)    //          .endofpacket
3517 
        );
3518 
 
3519 
        nios2_sdram_rsp_xbar_demux_002 rsp_xbar_demux_002 (
3520 
                .clk                (clk_clk),                               //       clk.clk
3521 
                .reset              (rst_controller_reset_out_reset),        // clk_reset.reset
3522 
                .sink_ready         (id_router_002_src_ready),               //      sink.ready
3523 
                .sink_channel       (id_router_002_src_channel),             //          .channel
3524 
                .sink_data          (id_router_002_src_data),                //          .data
3525 
                .sink_startofpacket (id_router_002_src_startofpacket),       //          .startofpacket
3526 
                .sink_endofpacket   (id_router_002_src_endofpacket),         //          .endofpacket
3527 
                .sink_valid         (id_router_002_src_valid),               //          .valid
3528 
                .src0_ready         (rsp_xbar_demux_002_src0_ready),         //      src0.ready
3529 
                .src0_valid         (rsp_xbar_demux_002_src0_valid),         //          .valid
3530 
                .src0_data          (rsp_xbar_demux_002_src0_data),          //          .data
3531 
                .src0_channel       (rsp_xbar_demux_002_src0_channel),       //          .channel
3532 
                .src0_startofpacket (rsp_xbar_demux_002_src0_startofpacket), //          .startofpacket
3533 
                .src0_endofpacket   (rsp_xbar_demux_002_src0_endofpacket)    //          .endofpacket
3534 
        );
3535 
 
3536 
        nios2_sdram_rsp_xbar_demux_002 rsp_xbar_demux_003 (
3537 
                .clk                (clk_clk),                               //       clk.clk
3538 
                .reset              (rst_controller_reset_out_reset),        // clk_reset.reset
3539 
                .sink_ready         (id_router_003_src_ready),               //      sink.ready
3540 
                .sink_channel       (id_router_003_src_channel),             //          .channel
3541 
                .sink_data          (id_router_003_src_data),                //          .data
3542 
                .sink_startofpacket (id_router_003_src_startofpacket),       //          .startofpacket
3543 
                .sink_endofpacket   (id_router_003_src_endofpacket),         //          .endofpacket
3544 
                .sink_valid         (id_router_003_src_valid),               //          .valid
3545 
                .src0_ready         (rsp_xbar_demux_003_src0_ready),         //      src0.ready
3546 
                .src0_valid         (rsp_xbar_demux_003_src0_valid),         //          .valid
3547 
                .src0_data          (rsp_xbar_demux_003_src0_data),          //          .data
3548 
                .src0_channel       (rsp_xbar_demux_003_src0_channel),       //          .channel
3549 
                .src0_startofpacket (rsp_xbar_demux_003_src0_startofpacket), //          .startofpacket
3550 
                .src0_endofpacket   (rsp_xbar_demux_003_src0_endofpacket)    //          .endofpacket
3551 
        );
3552 
 
3553 
        nios2_sdram_rsp_xbar_demux_002 rsp_xbar_demux_004 (
3554 
                .clk                (clk_clk),                               //       clk.clk
3555 
                .reset              (rst_controller_reset_out_reset),        // clk_reset.reset
3556 
                .sink_ready         (id_router_004_src_ready),               //      sink.ready
3557 
                .sink_channel       (id_router_004_src_channel),             //          .channel
3558 
                .sink_data          (id_router_004_src_data),                //          .data
3559 
                .sink_startofpacket (id_router_004_src_startofpacket),       //          .startofpacket
3560 
                .sink_endofpacket   (id_router_004_src_endofpacket),         //          .endofpacket
3561 
                .sink_valid         (id_router_004_src_valid),               //          .valid
3562 
                .src0_ready         (rsp_xbar_demux_004_src0_ready),         //      src0.ready
3563 
                .src0_valid         (rsp_xbar_demux_004_src0_valid),         //          .valid
3564 
                .src0_data          (rsp_xbar_demux_004_src0_data),          //          .data
3565 
                .src0_channel       (rsp_xbar_demux_004_src0_channel),       //          .channel
3566 
                .src0_startofpacket (rsp_xbar_demux_004_src0_startofpacket), //          .startofpacket
3567 
                .src0_endofpacket   (rsp_xbar_demux_004_src0_endofpacket)    //          .endofpacket
3568 
        );
3569 
 
3570 
        nios2_sdram_rsp_xbar_demux_002 rsp_xbar_demux_005 (
3571 
                .clk                (clk_clk),                               //       clk.clk
3572 
                .reset              (rst_controller_reset_out_reset),        // clk_reset.reset
3573 
                .sink_ready         (id_router_005_src_ready),               //      sink.ready
3574 
                .sink_channel       (id_router_005_src_channel),             //          .channel
3575 
                .sink_data          (id_router_005_src_data),                //          .data
3576 
                .sink_startofpacket (id_router_005_src_startofpacket),       //          .startofpacket
3577 
                .sink_endofpacket   (id_router_005_src_endofpacket),         //          .endofpacket
3578 
                .sink_valid         (id_router_005_src_valid),               //          .valid
3579 
                .src0_ready         (rsp_xbar_demux_005_src0_ready),         //      src0.ready
3580 
                .src0_valid         (rsp_xbar_demux_005_src0_valid),         //          .valid
3581 
                .src0_data          (rsp_xbar_demux_005_src0_data),          //          .data
3582 
                .src0_channel       (rsp_xbar_demux_005_src0_channel),       //          .channel
3583 
                .src0_startofpacket (rsp_xbar_demux_005_src0_startofpacket), //          .startofpacket
3584 
                .src0_endofpacket   (rsp_xbar_demux_005_src0_endofpacket)    //          .endofpacket
3585 
        );
3586 
 
3587 
        nios2_sdram_rsp_xbar_demux_002 rsp_xbar_demux_006 (
3588 
                .clk                (clk_clk),                               //       clk.clk
3589 
                .reset              (rst_controller_reset_out_reset),        // clk_reset.reset
3590 
                .sink_ready         (id_router_006_src_ready),               //      sink.ready
3591 
                .sink_channel       (id_router_006_src_channel),             //          .channel
3592 
                .sink_data          (id_router_006_src_data),                //          .data
3593 
                .sink_startofpacket (id_router_006_src_startofpacket),       //          .startofpacket
3594 
                .sink_endofpacket   (id_router_006_src_endofpacket),         //          .endofpacket
3595 
                .sink_valid         (id_router_006_src_valid),               //          .valid
3596 
                .src0_ready         (rsp_xbar_demux_006_src0_ready),         //      src0.ready
3597 
                .src0_valid         (rsp_xbar_demux_006_src0_valid),         //          .valid
3598 
                .src0_data          (rsp_xbar_demux_006_src0_data),          //          .data
3599 
                .src0_channel       (rsp_xbar_demux_006_src0_channel),       //          .channel
3600 
                .src0_startofpacket (rsp_xbar_demux_006_src0_startofpacket), //          .startofpacket
3601 
                .src0_endofpacket   (rsp_xbar_demux_006_src0_endofpacket)    //          .endofpacket
3602 
        );
3603 
 
3604 
        nios2_sdram_rsp_xbar_demux_002 rsp_xbar_demux_007 (
3605 
                .clk                (clk_clk),                               //       clk.clk
3606 
                .reset              (rst_controller_reset_out_reset),        // clk_reset.reset
3607 
                .sink_ready         (id_router_007_src_ready),               //      sink.ready
3608 
                .sink_channel       (id_router_007_src_channel),             //          .channel
3609 
                .sink_data          (id_router_007_src_data),                //          .data
3610 
                .sink_startofpacket (id_router_007_src_startofpacket),       //          .startofpacket
3611 
                .sink_endofpacket   (id_router_007_src_endofpacket),         //          .endofpacket
3612 
                .sink_valid         (id_router_007_src_valid),               //          .valid
3613 
                .src0_ready         (rsp_xbar_demux_007_src0_ready),         //      src0.ready
3614 
                .src0_valid         (rsp_xbar_demux_007_src0_valid),         //          .valid
3615 
                .src0_data          (rsp_xbar_demux_007_src0_data),          //          .data
3616 
                .src0_channel       (rsp_xbar_demux_007_src0_channel),       //          .channel
3617 
                .src0_startofpacket (rsp_xbar_demux_007_src0_startofpacket), //          .startofpacket
3618 
                .src0_endofpacket   (rsp_xbar_demux_007_src0_endofpacket)    //          .endofpacket
3619 
        );
3620 
 
3621 
        nios2_sdram_rsp_xbar_mux rsp_xbar_mux (
3622 
                .clk                 (clk_clk),                               //       clk.clk
3623 
                .reset               (rst_controller_reset_out_reset),        // clk_reset.reset
3624 
                .src_ready           (rsp_xbar_mux_src_ready),                //       src.ready
3625 
                .src_valid           (rsp_xbar_mux_src_valid),                //          .valid
3626 
                .src_data            (rsp_xbar_mux_src_data),                 //          .data
3627 
                .src_channel         (rsp_xbar_mux_src_channel),              //          .channel
3628 
                .src_startofpacket   (rsp_xbar_mux_src_startofpacket),        //          .startofpacket
3629 
                .src_endofpacket     (rsp_xbar_mux_src_endofpacket),          //          .endofpacket
3630 
                .sink0_ready         (rsp_xbar_demux_src0_ready),             //     sink0.ready
3631 
                .sink0_valid         (rsp_xbar_demux_src0_valid),             //          .valid
3632 
                .sink0_channel       (rsp_xbar_demux_src0_channel),           //          .channel
3633 
                .sink0_data          (rsp_xbar_demux_src0_data),              //          .data
3634 
                .sink0_startofpacket (rsp_xbar_demux_src0_startofpacket),     //          .startofpacket
3635 
                .sink0_endofpacket   (rsp_xbar_demux_src0_endofpacket),       //          .endofpacket
3636 
                .sink1_ready         (rsp_xbar_demux_001_src0_ready),         //     sink1.ready
3637 
                .sink1_valid         (rsp_xbar_demux_001_src0_valid),         //          .valid
3638 
                .sink1_channel       (rsp_xbar_demux_001_src0_channel),       //          .channel
3639 
                .sink1_data          (rsp_xbar_demux_001_src0_data),          //          .data
3640 
                .sink1_startofpacket (rsp_xbar_demux_001_src0_startofpacket), //          .startofpacket
3641 
                .sink1_endofpacket   (rsp_xbar_demux_001_src0_endofpacket)    //          .endofpacket
3642 
        );
3643 
 
3644 
        nios2_sdram_rsp_xbar_mux_001 rsp_xbar_mux_001 (
3645 
                .clk                 (clk_clk),                               //       clk.clk
3646 
                .reset               (rst_controller_reset_out_reset),        // clk_reset.reset
3647 
                .src_ready           (rsp_xbar_mux_001_src_ready),            //       src.ready
3648 
                .src_valid           (rsp_xbar_mux_001_src_valid),            //          .valid
3649 
                .src_data            (rsp_xbar_mux_001_src_data),             //          .data
3650 
                .src_channel         (rsp_xbar_mux_001_src_channel),          //          .channel
3651 
                .src_startofpacket   (rsp_xbar_mux_001_src_startofpacket),    //          .startofpacket
3652 
                .src_endofpacket     (rsp_xbar_mux_001_src_endofpacket),      //          .endofpacket
3653 
                .sink0_ready         (rsp_xbar_demux_src1_ready),             //     sink0.ready
3654 
                .sink0_valid         (rsp_xbar_demux_src1_valid),             //          .valid
3655 
                .sink0_channel       (rsp_xbar_demux_src1_channel),           //          .channel
3656 
                .sink0_data          (rsp_xbar_demux_src1_data),              //          .data
3657 
                .sink0_startofpacket (rsp_xbar_demux_src1_startofpacket),     //          .startofpacket
3658 
                .sink0_endofpacket   (rsp_xbar_demux_src1_endofpacket),       //          .endofpacket
3659 
                .sink1_ready         (rsp_xbar_demux_001_src1_ready),         //     sink1.ready
3660 
                .sink1_valid         (rsp_xbar_demux_001_src1_valid),         //          .valid
3661 
                .sink1_channel       (rsp_xbar_demux_001_src1_channel),       //          .channel
3662 
                .sink1_data          (rsp_xbar_demux_001_src1_data),          //          .data
3663 
                .sink1_startofpacket (rsp_xbar_demux_001_src1_startofpacket), //          .startofpacket
3664 
                .sink1_endofpacket   (rsp_xbar_demux_001_src1_endofpacket),   //          .endofpacket
3665 
                .sink2_ready         (rsp_xbar_demux_002_src0_ready),         //     sink2.ready
3666 
                .sink2_valid         (rsp_xbar_demux_002_src0_valid),         //          .valid
3667 
                .sink2_channel       (rsp_xbar_demux_002_src0_channel),       //          .channel
3668 
                .sink2_data          (rsp_xbar_demux_002_src0_data),          //          .data
3669 
                .sink2_startofpacket (rsp_xbar_demux_002_src0_startofpacket), //          .startofpacket
3670 
                .sink2_endofpacket   (rsp_xbar_demux_002_src0_endofpacket),   //          .endofpacket
3671 
                .sink3_ready         (rsp_xbar_demux_003_src0_ready),         //     sink3.ready
3672 
                .sink3_valid         (rsp_xbar_demux_003_src0_valid),         //          .valid
3673 
                .sink3_channel       (rsp_xbar_demux_003_src0_channel),       //          .channel
3674 
                .sink3_data          (rsp_xbar_demux_003_src0_data),          //          .data
3675 
                .sink3_startofpacket (rsp_xbar_demux_003_src0_startofpacket), //          .startofpacket
3676 
                .sink3_endofpacket   (rsp_xbar_demux_003_src0_endofpacket),   //          .endofpacket
3677 
                .sink4_ready         (rsp_xbar_demux_004_src0_ready),         //     sink4.ready
3678 
                .sink4_valid         (rsp_xbar_demux_004_src0_valid),         //          .valid
3679 
                .sink4_channel       (rsp_xbar_demux_004_src0_channel),       //          .channel
3680 
                .sink4_data          (rsp_xbar_demux_004_src0_data),          //          .data
3681 
                .sink4_startofpacket (rsp_xbar_demux_004_src0_startofpacket), //          .startofpacket
3682 
                .sink4_endofpacket   (rsp_xbar_demux_004_src0_endofpacket),   //          .endofpacket
3683 
                .sink5_ready         (rsp_xbar_demux_005_src0_ready),         //     sink5.ready
3684 
                .sink5_valid         (rsp_xbar_demux_005_src0_valid),         //          .valid
3685 
                .sink5_channel       (rsp_xbar_demux_005_src0_channel),       //          .channel
3686 
                .sink5_data          (rsp_xbar_demux_005_src0_data),          //          .data
3687 
                .sink5_startofpacket (rsp_xbar_demux_005_src0_startofpacket), //          .startofpacket
3688 
                .sink5_endofpacket   (rsp_xbar_demux_005_src0_endofpacket),   //          .endofpacket
3689 
                .sink6_ready         (rsp_xbar_demux_006_src0_ready),         //     sink6.ready
3690 
                .sink6_valid         (rsp_xbar_demux_006_src0_valid),         //          .valid
3691 
                .sink6_channel       (rsp_xbar_demux_006_src0_channel),       //          .channel
3692 
                .sink6_data          (rsp_xbar_demux_006_src0_data),          //          .data
3693 
                .sink6_startofpacket (rsp_xbar_demux_006_src0_startofpacket), //          .startofpacket
3694 
                .sink6_endofpacket   (rsp_xbar_demux_006_src0_endofpacket),   //          .endofpacket
3695 
                .sink7_ready         (rsp_xbar_demux_007_src0_ready),         //     sink7.ready
3696 
                .sink7_valid         (rsp_xbar_demux_007_src0_valid),         //          .valid
3697 
                .sink7_channel       (rsp_xbar_demux_007_src0_channel),       //          .channel
3698 
                .sink7_data          (rsp_xbar_demux_007_src0_data),          //          .data
3699 
                .sink7_startofpacket (rsp_xbar_demux_007_src0_startofpacket), //          .startofpacket
3700 
                .sink7_endofpacket   (rsp_xbar_demux_007_src0_endofpacket)    //          .endofpacket
3701 
        );
3702 
 
3703 
        nios2_sdram_cmd_xbar_demux_002 cmd_xbar_demux_002 (
3704 
                .clk                (clk_clk),                               //       clk.clk
3705 
                .reset              (rst_controller_reset_out_reset),        // clk_reset.reset
3706 
                .sink_ready         (addr_router_002_src_ready),             //      sink.ready
3707 
                .sink_channel       (addr_router_002_src_channel),           //          .channel
3708 
                .sink_data          (addr_router_002_src_data),              //          .data
3709 
                .sink_startofpacket (addr_router_002_src_startofpacket),     //          .startofpacket
3710 
                .sink_endofpacket   (addr_router_002_src_endofpacket),       //          .endofpacket
3711 
                .sink_valid         (addr_router_002_src_valid),             //          .valid
3712 
                .src0_ready         (cmd_xbar_demux_002_src0_ready),         //      src0.ready
3713 
                .src0_valid         (cmd_xbar_demux_002_src0_valid),         //          .valid
3714 
                .src0_data          (cmd_xbar_demux_002_src0_data),          //          .data
3715 
                .src0_channel       (cmd_xbar_demux_002_src0_channel),       //          .channel
3716 
                .src0_startofpacket (cmd_xbar_demux_002_src0_startofpacket), //          .startofpacket
3717 
                .src0_endofpacket   (cmd_xbar_demux_002_src0_endofpacket)    //          .endofpacket
3718 
        );
3719 
 
3720 
        nios2_sdram_cmd_xbar_demux_002 cmd_xbar_demux_003 (
3721 
                .clk                (clk_clk),                               //       clk.clk
3722 
                .reset              (rst_controller_reset_out_reset),        // clk_reset.reset
3723 
                .sink_ready         (addr_router_003_src_ready),             //      sink.ready
3724 
                .sink_channel       (addr_router_003_src_channel),           //          .channel
3725 
                .sink_data          (addr_router_003_src_data),              //          .data
3726 
                .sink_startofpacket (addr_router_003_src_startofpacket),     //          .startofpacket
3727 
                .sink_endofpacket   (addr_router_003_src_endofpacket),       //          .endofpacket
3728 
                .sink_valid         (addr_router_003_src_valid),             //          .valid
3729 
                .src0_ready         (cmd_xbar_demux_003_src0_ready),         //      src0.ready
3730 
                .src0_valid         (cmd_xbar_demux_003_src0_valid),         //          .valid
3731 
                .src0_data          (cmd_xbar_demux_003_src0_data),          //          .data
3732 
                .src0_channel       (cmd_xbar_demux_003_src0_channel),       //          .channel
3733 
                .src0_startofpacket (cmd_xbar_demux_003_src0_startofpacket), //          .startofpacket
3734 
                .src0_endofpacket   (cmd_xbar_demux_003_src0_endofpacket)    //          .endofpacket
3735 
        );
3736 
 
3737 
        nios2_sdram_cmd_xbar_mux_008 cmd_xbar_mux_008 (
3738 
                .clk                 (clk_clk),                               //       clk.clk
3739 
                .reset               (rst_controller_reset_out_reset),        // clk_reset.reset
3740 
                .src_ready           (cmd_xbar_mux_008_src_ready),            //       src.ready
3741 
                .src_valid           (cmd_xbar_mux_008_src_valid),            //          .valid
3742 
                .src_data            (cmd_xbar_mux_008_src_data),             //          .data
3743 
                .src_channel         (cmd_xbar_mux_008_src_channel),          //          .channel
3744 
                .src_startofpacket   (cmd_xbar_mux_008_src_startofpacket),    //          .startofpacket
3745 
                .src_endofpacket     (cmd_xbar_mux_008_src_endofpacket),      //          .endofpacket
3746 
                .sink0_ready         (cmd_xbar_demux_002_src0_ready),         //     sink0.ready
3747 
                .sink0_valid         (cmd_xbar_demux_002_src0_valid),         //          .valid
3748 
                .sink0_channel       (cmd_xbar_demux_002_src0_channel),       //          .channel
3749 
                .sink0_data          (cmd_xbar_demux_002_src0_data),          //          .data
3750 
                .sink0_startofpacket (cmd_xbar_demux_002_src0_startofpacket), //          .startofpacket
3751 
                .sink0_endofpacket   (cmd_xbar_demux_002_src0_endofpacket),   //          .endofpacket
3752 
                .sink1_ready         (cmd_xbar_demux_003_src0_ready),         //     sink1.ready
3753 
                .sink1_valid         (cmd_xbar_demux_003_src0_valid),         //          .valid
3754 
                .sink1_channel       (cmd_xbar_demux_003_src0_channel),       //          .channel
3755 
                .sink1_data          (cmd_xbar_demux_003_src0_data),          //          .data
3756 
                .sink1_startofpacket (cmd_xbar_demux_003_src0_startofpacket), //          .startofpacket
3757 
                .sink1_endofpacket   (cmd_xbar_demux_003_src0_endofpacket)    //          .endofpacket
3758 
        );
3759 
 
3760 
        nios2_sdram_rsp_xbar_demux_008 rsp_xbar_demux_008 (
3761 
                .clk                (clk_clk),                               //       clk.clk
3762 
                .reset              (rst_controller_reset_out_reset),        // clk_reset.reset
3763 
                .sink_ready         (id_router_008_src_ready),               //      sink.ready
3764 
                .sink_channel       (id_router_008_src_channel),             //          .channel
3765 
                .sink_data          (id_router_008_src_data),                //          .data
3766 
                .sink_startofpacket (id_router_008_src_startofpacket),       //          .startofpacket
3767 
                .sink_endofpacket   (id_router_008_src_endofpacket),         //          .endofpacket
3768 
                .sink_valid         (id_router_008_src_valid),               //          .valid
3769 
                .src0_ready         (rsp_xbar_demux_008_src0_ready),         //      src0.ready
3770 
                .src0_valid         (rsp_xbar_demux_008_src0_valid),         //          .valid
3771 
                .src0_data          (rsp_xbar_demux_008_src0_data),          //          .data
3772 
                .src0_channel       (rsp_xbar_demux_008_src0_channel),       //          .channel
3773 
                .src0_startofpacket (rsp_xbar_demux_008_src0_startofpacket), //          .startofpacket
3774 
                .src0_endofpacket   (rsp_xbar_demux_008_src0_endofpacket),   //          .endofpacket
3775 
                .src1_ready         (rsp_xbar_demux_008_src1_ready),         //      src1.ready
3776 
                .src1_valid         (rsp_xbar_demux_008_src1_valid),         //          .valid
3777 
                .src1_data          (rsp_xbar_demux_008_src1_data),          //          .data
3778 
                .src1_channel       (rsp_xbar_demux_008_src1_channel),       //          .channel
3779 
                .src1_startofpacket (rsp_xbar_demux_008_src1_startofpacket), //          .startofpacket
3780 
                .src1_endofpacket   (rsp_xbar_demux_008_src1_endofpacket)    //          .endofpacket
3781 
        );
3782 
 
3783 
        altera_merlin_width_adapter #(
3784 
                .IN_PKT_ADDR_H                 (61),
3785 
                .IN_PKT_ADDR_L                 (36),
3786 
                .IN_PKT_DATA_H                 (31),
3787 
                .IN_PKT_DATA_L                 (0),
3788 
                .IN_PKT_BYTEEN_H               (35),
3789 
                .IN_PKT_BYTEEN_L               (32),
3790 
                .IN_PKT_BYTE_CNT_H             (70),
3791 
                .IN_PKT_BYTE_CNT_L             (68),
3792 
                .IN_PKT_TRANS_COMPRESSED_READ  (62),
3793 
                .IN_PKT_BURSTWRAP_H            (73),
3794 
                .IN_PKT_BURSTWRAP_L            (71),
3795 
                .IN_PKT_BURST_SIZE_H           (76),
3796 
                .IN_PKT_BURST_SIZE_L           (74),
3797 
                .IN_PKT_RESPONSE_STATUS_H      (98),
3798 
                .IN_PKT_RESPONSE_STATUS_L      (97),
3799 
                .IN_PKT_TRANS_EXCLUSIVE        (67),
3800 
                .IN_PKT_BURST_TYPE_H           (78),
3801 
                .IN_PKT_BURST_TYPE_L           (77),
3802 
                .IN_ST_DATA_W                  (99),
3803 
                .OUT_PKT_ADDR_H                (43),
3804 
                .OUT_PKT_ADDR_L                (18),
3805 
                .OUT_PKT_DATA_H                (15),
3806 
                .OUT_PKT_DATA_L                (0),
3807 
                .OUT_PKT_BYTEEN_H              (17),
3808 
                .OUT_PKT_BYTEEN_L              (16),
3809 
                .OUT_PKT_BYTE_CNT_H            (52),
3810 
                .OUT_PKT_BYTE_CNT_L            (50),
3811 
                .OUT_PKT_TRANS_COMPRESSED_READ (44),
3812 
                .OUT_PKT_BURST_SIZE_H          (58),
3813 
                .OUT_PKT_BURST_SIZE_L          (56),
3814 
                .OUT_PKT_RESPONSE_STATUS_H     (80),
3815 
                .OUT_PKT_RESPONSE_STATUS_L     (79),
3816 
                .OUT_PKT_TRANS_EXCLUSIVE       (49),
3817 
                .OUT_PKT_BURST_TYPE_H          (60),
3818 
                .OUT_PKT_BURST_TYPE_L          (59),
3819 
                .OUT_ST_DATA_W                 (81),
3820 
                .ST_CHANNEL_W                  (8),
3821 
                .OPTIMIZE_FOR_RSP              (0)
3822 
        ) width_adapter (
3823 
                .clk                  (clk_clk),                            //       clk.clk
3824 
                .reset                (rst_controller_reset_out_reset),     // clk_reset.reset
3825 
                .in_valid             (cmd_xbar_mux_001_src_valid),         //      sink.valid
3826 
                .in_channel           (cmd_xbar_mux_001_src_channel),       //          .channel
3827 
                .in_startofpacket     (cmd_xbar_mux_001_src_startofpacket), //          .startofpacket
3828 
                .in_endofpacket       (cmd_xbar_mux_001_src_endofpacket),   //          .endofpacket
3829 
                .in_ready             (cmd_xbar_mux_001_src_ready),         //          .ready
3830 
                .in_data              (cmd_xbar_mux_001_src_data),          //          .data
3831 
                .out_endofpacket      (width_adapter_src_endofpacket),      //       src.endofpacket
3832 
                .out_data             (width_adapter_src_data),             //          .data
3833 
                .out_channel          (width_adapter_src_channel),          //          .channel
3834 
                .out_valid            (width_adapter_src_valid),            //          .valid
3835 
                .out_ready            (width_adapter_src_ready),            //          .ready
3836 
                .out_startofpacket    (width_adapter_src_startofpacket),    //          .startofpacket
3837 
                .in_command_size_data (3'b000)                              // (terminated)
3838 
        );
3839 
 
3840 
        altera_merlin_width_adapter #(
3841 
                .IN_PKT_ADDR_H                 (43),
3842 
                .IN_PKT_ADDR_L                 (18),
3843 
                .IN_PKT_DATA_H                 (15),
3844 
                .IN_PKT_DATA_L                 (0),
3845 
                .IN_PKT_BYTEEN_H               (17),
3846 
                .IN_PKT_BYTEEN_L               (16),
3847 
                .IN_PKT_BYTE_CNT_H             (52),
3848 
                .IN_PKT_BYTE_CNT_L             (50),
3849 
                .IN_PKT_TRANS_COMPRESSED_READ  (44),
3850 
                .IN_PKT_BURSTWRAP_H            (55),
3851 
                .IN_PKT_BURSTWRAP_L            (53),
3852 
                .IN_PKT_BURST_SIZE_H           (58),
3853 
                .IN_PKT_BURST_SIZE_L           (56),
3854 
                .IN_PKT_RESPONSE_STATUS_H      (80),
3855 
                .IN_PKT_RESPONSE_STATUS_L      (79),
3856 
                .IN_PKT_TRANS_EXCLUSIVE        (49),
3857 
                .IN_PKT_BURST_TYPE_H           (60),
3858 
                .IN_PKT_BURST_TYPE_L           (59),
3859 
                .IN_ST_DATA_W                  (81),
3860 
                .OUT_PKT_ADDR_H                (61),
3861 
                .OUT_PKT_ADDR_L                (36),
3862 
                .OUT_PKT_DATA_H                (31),
3863 
                .OUT_PKT_DATA_L                (0),
3864 
                .OUT_PKT_BYTEEN_H              (35),
3865 
                .OUT_PKT_BYTEEN_L              (32),
3866 
                .OUT_PKT_BYTE_CNT_H            (70),
3867 
                .OUT_PKT_BYTE_CNT_L            (68),
3868 
                .OUT_PKT_TRANS_COMPRESSED_READ (62),
3869 
                .OUT_PKT_BURST_SIZE_H          (76),
3870 
                .OUT_PKT_BURST_SIZE_L          (74),
3871 
                .OUT_PKT_RESPONSE_STATUS_H     (98),
3872 
                .OUT_PKT_RESPONSE_STATUS_L     (97),
3873 
                .OUT_PKT_TRANS_EXCLUSIVE       (67),
3874 
                .OUT_PKT_BURST_TYPE_H          (78),
3875 
                .OUT_PKT_BURST_TYPE_L          (77),
3876 
                .OUT_ST_DATA_W                 (99),
3877 
                .ST_CHANNEL_W                  (8),
3878 
                .OPTIMIZE_FOR_RSP              (1)
3879 
        ) width_adapter_001 (
3880 
                .clk                  (clk_clk),                             //       clk.clk
3881 
                .reset                (rst_controller_reset_out_reset),      // clk_reset.reset
3882 
                .in_valid             (id_router_001_src_valid),             //      sink.valid
3883 
                .in_channel           (id_router_001_src_channel),           //          .channel
3884 
                .in_startofpacket     (id_router_001_src_startofpacket),     //          .startofpacket
3885 
                .in_endofpacket       (id_router_001_src_endofpacket),       //          .endofpacket
3886 
                .in_ready             (id_router_001_src_ready),             //          .ready
3887 
                .in_data              (id_router_001_src_data),              //          .data
3888 
                .out_endofpacket      (width_adapter_001_src_endofpacket),   //       src.endofpacket
3889 
                .out_data             (width_adapter_001_src_data),          //          .data
3890 
                .out_channel          (width_adapter_001_src_channel),       //          .channel
3891 
                .out_valid            (width_adapter_001_src_valid),         //          .valid
3892 
                .out_ready            (width_adapter_001_src_ready),         //          .ready
3893 
                .out_startofpacket    (width_adapter_001_src_startofpacket), //          .startofpacket
3894 
                .in_command_size_data (3'b000)                               // (terminated)
3895 
        );
3896 
 
3897 
        nios2_sdram_irq_mapper irq_mapper (
3898 
                .clk           (clk_clk),                        //       clk.clk
3899 
                .reset         (rst_controller_reset_out_reset), // clk_reset.reset
3900 
                .receiver0_irq (irq_mapper_receiver0_irq),       // receiver0.irq
3901 
                .receiver1_irq (irq_mapper_receiver1_irq),       // receiver1.irq
3902 
                .receiver2_irq (irq_mapper_receiver2_irq),       // receiver2.irq
3903 
                .receiver3_irq (irq_mapper_receiver3_irq),       // receiver3.irq
3904 
                .sender_irq    (nios2_qsys_1_d_irq_irq)          //    sender.irq
3905 
        );
3906 
 
3907 
endmodule

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