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lanttu |
-- hibi_pe_dma_1.vhd
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-- This file was auto-generated as part of a SOPC Builder generate operation.
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-- If you edit it your changes will probably be lost.
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity hibi_pe_dma_1 is
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port (
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avalon_cfg_addr_in : in std_logic_vector(6 downto 0) := (others => '0'); -- avalon_slave_0.address
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avalon_cfg_we_in : in std_logic := '0'; -- .write
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avalon_cfg_re_in : in std_logic := '0'; -- .read
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avalon_cfg_cs_in : in std_logic := '0'; -- .chipselect
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avalon_cfg_waitrequest_out : out std_logic; -- .waitrequest
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avalon_cfg_writedata_in : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
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avalon_cfg_readdata_out : out std_logic_vector(31 downto 0); -- .readdata
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hibi_data_in : in std_logic_vector(31 downto 0) := (others => '0'); -- conduit_end.export
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hibi_av_in : in std_logic := '0'; -- .export
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hibi_empty_in : in std_logic := '0'; -- .export
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hibi_comm_in : in std_logic_vector(4 downto 0) := (others => '0'); -- .export
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hibi_re_out : out std_logic; -- .export
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hibi_data_out : out std_logic_vector(31 downto 0); -- .export
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hibi_av_out : out std_logic; -- .export
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hibi_full_in : in std_logic := '0'; -- .export
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hibi_comm_out : out std_logic_vector(4 downto 0); -- .export
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hibi_we_out : out std_logic; -- .export
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clk : in std_logic := '0'; -- clock_sink.clk
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rst_n : in std_logic := '0'; -- clock_sink_reset.reset_n
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rx_irq_out : out std_logic; -- interrupt_sender.irq
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avalon_addr_out_rx : out std_logic_vector(31 downto 0); -- avalon_master.address
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avalon_we_out_rx : out std_logic; -- .write
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avalon_be_out_rx : out std_logic_vector(3 downto 0); -- .byteenable
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avalon_writedata_out_rx : out std_logic_vector(31 downto 0); -- .writedata
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avalon_waitrequest_in_rx : in std_logic := '0'; -- .waitrequest
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avalon_readdatavalid_in_tx : in std_logic := '0'; -- avalon_master_1.readdatavalid
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avalon_waitrequest_in_tx : in std_logic := '0'; -- .waitrequest
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avalon_readdata_in_tx : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
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avalon_re_out_tx : out std_logic; -- .read
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avalon_addr_out_tx : out std_logic_vector(31 downto 0) -- .address
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);
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end entity hibi_pe_dma_1;
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architecture rtl of hibi_pe_dma_1 is
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component hibi_pe_dma is
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generic (
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data_width_g : integer := 32;
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addr_width_g : integer := 32;
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words_width_g : integer := 16;
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n_stream_chans_g : integer := 4;
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n_packet_chans_g : integer := 4;
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n_chans_bits_g : integer := 3;
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hibi_addr_cmp_lo_g : integer := 8;
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hibi_addr_cmp_hi_g : integer := 31
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);
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port (
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avalon_cfg_addr_in : in std_logic_vector(6 downto 0) := (others => 'X'); -- address
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avalon_cfg_we_in : in std_logic := 'X'; -- write
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avalon_cfg_re_in : in std_logic := 'X'; -- read
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avalon_cfg_cs_in : in std_logic := 'X'; -- chipselect
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avalon_cfg_waitrequest_out : out std_logic; -- waitrequest
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avalon_cfg_writedata_in : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
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avalon_cfg_readdata_out : out std_logic_vector(31 downto 0); -- readdata
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hibi_data_in : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
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hibi_av_in : in std_logic := 'X'; -- export
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hibi_empty_in : in std_logic := 'X'; -- export
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hibi_comm_in : in std_logic_vector(4 downto 0) := (others => 'X'); -- export
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hibi_re_out : out std_logic; -- export
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hibi_data_out : out std_logic_vector(31 downto 0); -- export
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hibi_av_out : out std_logic; -- export
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hibi_full_in : in std_logic := 'X'; -- export
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hibi_comm_out : out std_logic_vector(4 downto 0); -- export
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hibi_we_out : out std_logic; -- export
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clk : in std_logic := 'X'; -- clk
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rst_n : in std_logic := 'X'; -- reset_n
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rx_irq_out : out std_logic; -- irq
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avalon_addr_out_rx : out std_logic_vector(31 downto 0); -- address
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avalon_we_out_rx : out std_logic; -- write
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avalon_be_out_rx : out std_logic_vector(3 downto 0); -- byteenable
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avalon_writedata_out_rx : out std_logic_vector(31 downto 0); -- writedata
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avalon_waitrequest_in_rx : in std_logic := 'X'; -- waitrequest
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avalon_readdatavalid_in_tx : in std_logic := 'X'; -- readdatavalid
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avalon_waitrequest_in_tx : in std_logic := 'X'; -- waitrequest
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avalon_readdata_in_tx : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
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avalon_re_out_tx : out std_logic; -- read
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avalon_addr_out_tx : out std_logic_vector(31 downto 0) -- address
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);
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end component hibi_pe_dma;
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begin
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hibi_pe_dma_1 : component hibi_pe_dma
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generic map (
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data_width_g => 32,
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addr_width_g => 32,
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words_width_g => 16,
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n_stream_chans_g => 0,
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n_packet_chans_g => 8,
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n_chans_bits_g => 3,
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hibi_addr_cmp_lo_g => 0,
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hibi_addr_cmp_hi_g => 31
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)
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port map (
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avalon_cfg_addr_in => avalon_cfg_addr_in, -- avalon_slave_0.address
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avalon_cfg_we_in => avalon_cfg_we_in, -- .write
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avalon_cfg_re_in => avalon_cfg_re_in, -- .read
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avalon_cfg_cs_in => avalon_cfg_cs_in, -- .chipselect
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avalon_cfg_waitrequest_out => avalon_cfg_waitrequest_out, -- .waitrequest
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avalon_cfg_writedata_in => avalon_cfg_writedata_in, -- .writedata
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avalon_cfg_readdata_out => avalon_cfg_readdata_out, -- .readdata
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hibi_data_in => hibi_data_in, -- conduit_end.export
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hibi_av_in => hibi_av_in, -- .export
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hibi_empty_in => hibi_empty_in, -- .export
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hibi_comm_in => hibi_comm_in, -- .export
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hibi_re_out => hibi_re_out, -- .export
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hibi_data_out => hibi_data_out, -- .export
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hibi_av_out => hibi_av_out, -- .export
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hibi_full_in => hibi_full_in, -- .export
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hibi_comm_out => hibi_comm_out, -- .export
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hibi_we_out => hibi_we_out, -- .export
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clk => clk, -- clock_sink.clk
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rst_n => rst_n, -- clock_sink_reset.reset_n
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rx_irq_out => rx_irq_out, -- interrupt_sender.irq
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avalon_addr_out_rx => avalon_addr_out_rx, -- avalon_master.address
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avalon_we_out_rx => avalon_we_out_rx, -- .write
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avalon_be_out_rx => avalon_be_out_rx, -- .byteenable
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avalon_writedata_out_rx => avalon_writedata_out_rx, -- .writedata
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avalon_waitrequest_in_rx => avalon_waitrequest_in_rx, -- .waitrequest
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avalon_readdatavalid_in_tx => avalon_readdatavalid_in_tx, -- avalon_master_1.readdatavalid
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avalon_waitrequest_in_tx => avalon_waitrequest_in_tx, -- .waitrequest
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avalon_readdata_in_tx => avalon_readdata_in_tx, -- .readdata
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avalon_re_out_tx => avalon_re_out_tx, -- .read
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avalon_addr_out_tx => avalon_addr_out_tx -- .address
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);
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end architecture rtl; -- of hibi_pe_dma_1
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