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//megafunction wizard: %Altera SOPC Builder%

//GENERATION: STANDARD

//VERSION: WM1.0

//Legal Notice: (C)2012 Altera Corporation. All rights reserved.  Your

//use of Altera Corporation's design tools, logic functions and other

//software and tools, and its AMPP partner logic functions, and any

//output files any of the foregoing (including device programming or

//simulation files), and any associated documentation or information are

//expressly subject to the terms and conditions of the Altera Program

//License Subscription Agreement or other applicable license agreement,

//including, without limitation, that your use is for the sole purpose

//of programming logic devices manufactured by Altera and sold by Altera

//or its authorized distributors.  Please refer to the applicable

//agreement for further details.

// synthesis translate_off

`timescale 1ns / 1ps

// synthesis translate_on

// turn off superfluous verilog processor warnings 

// altera message_level Level1 

// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cpu_1_jtag_debug_module_arbitrator (

                                            // inputs:

                                             clk,

                                             cpu_1_data_master_address_to_slave,

                                             cpu_1_data_master_byteenable,

                                             cpu_1_data_master_debugaccess,

                                             cpu_1_data_master_latency_counter,

                                             cpu_1_data_master_read,

                                             cpu_1_data_master_read_data_valid_sdram_1_s1_shift_register,

                                             cpu_1_data_master_write,

                                             cpu_1_data_master_writedata,

                                             cpu_1_instruction_master_address_to_slave,

                                             cpu_1_instruction_master_latency_counter,

                                             cpu_1_instruction_master_read,

                                             cpu_1_instruction_master_read_data_valid_sdram_1_s1_shift_register,

                                             cpu_1_jtag_debug_module_readdata,

                                             cpu_1_jtag_debug_module_resetrequest,

                                             reset_n,

                                            // outputs:

                                             cpu_1_data_master_granted_cpu_1_jtag_debug_module,

                                             cpu_1_data_master_qualified_request_cpu_1_jtag_debug_module,

                                             cpu_1_data_master_read_data_valid_cpu_1_jtag_debug_module,

                                             cpu_1_data_master_requests_cpu_1_jtag_debug_module,

                                             cpu_1_instruction_master_granted_cpu_1_jtag_debug_module,

                                             cpu_1_instruction_master_qualified_request_cpu_1_jtag_debug_module,

                                             cpu_1_instruction_master_read_data_valid_cpu_1_jtag_debug_module,

                                             cpu_1_instruction_master_requests_cpu_1_jtag_debug_module,

                                             cpu_1_jtag_debug_module_address,

                                             cpu_1_jtag_debug_module_begintransfer,

                                             cpu_1_jtag_debug_module_byteenable,

                                             cpu_1_jtag_debug_module_chipselect,

                                             cpu_1_jtag_debug_module_debugaccess,

                                             cpu_1_jtag_debug_module_readdata_from_sa,

                                             cpu_1_jtag_debug_module_reset_n,

                                             cpu_1_jtag_debug_module_resetrequest_from_sa,

                                             cpu_1_jtag_debug_module_write,

                                             cpu_1_jtag_debug_module_writedata,

                                             d1_cpu_1_jtag_debug_module_end_xfer

                                          )

;

  output           cpu_1_data_master_granted_cpu_1_jtag_debug_module;

  output           cpu_1_data_master_qualified_request_cpu_1_jtag_debug_module;

  output           cpu_1_data_master_read_data_valid_cpu_1_jtag_debug_module;

  output           cpu_1_data_master_requests_cpu_1_jtag_debug_module;

  output           cpu_1_instruction_master_granted_cpu_1_jtag_debug_module;

  output           cpu_1_instruction_master_qualified_request_cpu_1_jtag_debug_module;

  output           cpu_1_instruction_master_read_data_valid_cpu_1_jtag_debug_module;

  output           cpu_1_instruction_master_requests_cpu_1_jtag_debug_module;

  output  [  8: 0] cpu_1_jtag_debug_module_address;

  output           cpu_1_jtag_debug_module_begintransfer;

  output  [  3: 0] cpu_1_jtag_debug_module_byteenable;

  output           cpu_1_jtag_debug_module_chipselect;

  output           cpu_1_jtag_debug_module_debugaccess;

  output  [ 31: 0] cpu_1_jtag_debug_module_readdata_from_sa;

  output           cpu_1_jtag_debug_module_reset_n;

  output           cpu_1_jtag_debug_module_resetrequest_from_sa;

  output           cpu_1_jtag_debug_module_write;

  output  [ 31: 0] cpu_1_jtag_debug_module_writedata;

  output           d1_cpu_1_jtag_debug_module_end_xfer;

  input            clk;

  input   [ 24: 0] cpu_1_data_master_address_to_slave;

  input   [  3: 0] cpu_1_data_master_byteenable;

  input            cpu_1_data_master_debugaccess;

  input            cpu_1_data_master_latency_counter;

  input            cpu_1_data_master_read;

  input            cpu_1_data_master_read_data_valid_sdram_1_s1_shift_register;

  input            cpu_1_data_master_write;

  input   [ 31: 0] cpu_1_data_master_writedata;

  input   [ 24: 0] cpu_1_instruction_master_address_to_slave;

  input            cpu_1_instruction_master_latency_counter;

  input            cpu_1_instruction_master_read;

  input            cpu_1_instruction_master_read_data_valid_sdram_1_s1_shift_register;

  input   [ 31: 0] cpu_1_jtag_debug_module_readdata;

  input            cpu_1_jtag_debug_module_resetrequest;

  input            reset_n;

  wire             cpu_1_data_master_arbiterlock;

  wire             cpu_1_data_master_arbiterlock2;

  wire             cpu_1_data_master_continuerequest;

  wire             cpu_1_data_master_granted_cpu_1_jtag_debug_module;

  wire             cpu_1_data_master_qualified_request_cpu_1_jtag_debug_module;

  wire             cpu_1_data_master_read_data_valid_cpu_1_jtag_debug_module;

  wire             cpu_1_data_master_requests_cpu_1_jtag_debug_module;

  wire             cpu_1_data_master_saved_grant_cpu_1_jtag_debug_module;

  wire             cpu_1_instruction_master_arbiterlock;

  wire             cpu_1_instruction_master_arbiterlock2;

  wire             cpu_1_instruction_master_continuerequest;

  wire             cpu_1_instruction_master_granted_cpu_1_jtag_debug_module;

  wire             cpu_1_instruction_master_qualified_request_cpu_1_jtag_debug_module;

  wire             cpu_1_instruction_master_read_data_valid_cpu_1_jtag_debug_module;

  wire             cpu_1_instruction_master_requests_cpu_1_jtag_debug_module;

  wire             cpu_1_instruction_master_saved_grant_cpu_1_jtag_debug_module;

  wire    [  8: 0] cpu_1_jtag_debug_module_address;

  wire             cpu_1_jtag_debug_module_allgrants;

  wire             cpu_1_jtag_debug_module_allow_new_arb_cycle;

  wire             cpu_1_jtag_debug_module_any_bursting_master_saved_grant;

  wire             cpu_1_jtag_debug_module_any_continuerequest;

  reg     [  1: 0] cpu_1_jtag_debug_module_arb_addend;

  wire             cpu_1_jtag_debug_module_arb_counter_enable;

  reg     [  1: 0] cpu_1_jtag_debug_module_arb_share_counter;

  wire    [  1: 0] cpu_1_jtag_debug_module_arb_share_counter_next_value;

  wire    [  1: 0] cpu_1_jtag_debug_module_arb_share_set_values;

  wire    [  1: 0] cpu_1_jtag_debug_module_arb_winner;

  wire             cpu_1_jtag_debug_module_arbitration_holdoff_internal;

  wire             cpu_1_jtag_debug_module_beginbursttransfer_internal;

  wire             cpu_1_jtag_debug_module_begins_xfer;

  wire             cpu_1_jtag_debug_module_begintransfer;

  wire    [  3: 0] cpu_1_jtag_debug_module_byteenable;

  wire             cpu_1_jtag_debug_module_chipselect;

  wire    [  3: 0] cpu_1_jtag_debug_module_chosen_master_double_vector;

  wire    [  1: 0] cpu_1_jtag_debug_module_chosen_master_rot_left;

  wire             cpu_1_jtag_debug_module_debugaccess;

  wire             cpu_1_jtag_debug_module_end_xfer;

  wire             cpu_1_jtag_debug_module_firsttransfer;

  wire    [  1: 0] cpu_1_jtag_debug_module_grant_vector;

  wire             cpu_1_jtag_debug_module_in_a_read_cycle;

  wire             cpu_1_jtag_debug_module_in_a_write_cycle;

  wire    [  1: 0] cpu_1_jtag_debug_module_master_qreq_vector;

  wire             cpu_1_jtag_debug_module_non_bursting_master_requests;

  wire    [ 31: 0] cpu_1_jtag_debug_module_readdata_from_sa;

  reg              cpu_1_jtag_debug_module_reg_firsttransfer;

  wire             cpu_1_jtag_debug_module_reset_n;

  wire             cpu_1_jtag_debug_module_resetrequest_from_sa;

  reg     [  1: 0] cpu_1_jtag_debug_module_saved_chosen_master_vector;

  reg              cpu_1_jtag_debug_module_slavearbiterlockenable;

  wire             cpu_1_jtag_debug_module_slavearbiterlockenable2;

  wire             cpu_1_jtag_debug_module_unreg_firsttransfer;

  wire             cpu_1_jtag_debug_module_waits_for_read;

  wire             cpu_1_jtag_debug_module_waits_for_write;

  wire             cpu_1_jtag_debug_module_write;

  wire    [ 31: 0] cpu_1_jtag_debug_module_writedata;

  reg              d1_cpu_1_jtag_debug_module_end_xfer;

  reg              d1_reasons_to_wait;

  reg              enable_nonzero_assertions;

  wire             end_xfer_arb_share_counter_term_cpu_1_jtag_debug_module;

  wire             in_a_read_cycle;

  wire             in_a_write_cycle;

  reg              last_cycle_cpu_1_data_master_granted_slave_cpu_1_jtag_debug_module;

  reg              last_cycle_cpu_1_instruction_master_granted_slave_cpu_1_jtag_debug_module;

  wire    [ 24: 0] shifted_address_to_cpu_1_jtag_debug_module_from_cpu_1_data_master;

  wire    [ 24: 0] shifted_address_to_cpu_1_jtag_debug_module_from_cpu_1_instruction_master;

  wire             wait_for_cpu_1_jtag_debug_module_counter;

  always @(posedge clk or negedge reset_n)

    begin

      if (reset_n == 0)

          d1_reasons_to_wait <= 0;

      else

        d1_reasons_to_wait <= ~cpu_1_jtag_debug_module_end_xfer;

    end

  assign cpu_1_jtag_debug_module_begins_xfer = ~d1_reasons_to_wait & ((cpu_1_data_master_qualified_request_cpu_1_jtag_debug_module | cpu_1_instruction_master_qualified_request_cpu_1_jtag_debug_module));

  //assign cpu_1_jtag_debug_module_readdata_from_sa = cpu_1_jtag_debug_module_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign

  assign cpu_1_jtag_debug_module_readdata_from_sa = cpu_1_jtag_debug_module_readdata;

  assign cpu_1_data_master_requests_cpu_1_jtag_debug_module = ({cpu_1_data_master_address_to_slave[24 : 11] , 11'b0} == 25'h1000800) & (cpu_1_data_master_read | cpu_1_data_master_write);

  //cpu_1_jtag_debug_module_arb_share_counter set values, which is an e_mux

  assign cpu_1_jtag_debug_module_arb_share_set_values = 1;

  //cpu_1_jtag_debug_module_non_bursting_master_requests mux, which is an e_mux

  assign cpu_1_jtag_debug_module_non_bursting_master_requests = cpu_1_data_master_requests_cpu_1_jtag_debug_module |

    cpu_1_instruction_master_requests_cpu_1_jtag_debug_module |

    cpu_1_data_master_requests_cpu_1_jtag_debug_module |

    cpu_1_instruction_master_requests_cpu_1_jtag_debug_module;

  //cpu_1_jtag_debug_module_any_bursting_master_saved_grant mux, which is an e_mux

  assign cpu_1_jtag_debug_module_any_bursting_master_saved_grant = 0;

  //cpu_1_jtag_debug_module_arb_share_counter_next_value assignment, which is an e_assign

  assign cpu_1_jtag_debug_module_arb_share_counter_next_value = cpu_1_jtag_debug_module_firsttransfer ? (cpu_1_jtag_debug_module_arb_share_set_values - 1) : |cpu_1_jtag_debug_module_arb_share_counter ? (cpu_1_jtag_debug_module_arb_share_counter - 1) : 0;

  //cpu_1_jtag_debug_module_allgrants all slave grants, which is an e_mux

  assign cpu_1_jtag_debug_module_allgrants = (|cpu_1_jtag_debug_module_grant_vector) |

    (|cpu_1_jtag_debug_module_grant_vector) |

    (|cpu_1_jtag_debug_module_grant_vector) |

    (|cpu_1_jtag_debug_module_grant_vector);

  //cpu_1_jtag_debug_module_end_xfer assignment, which is an e_assign

  assign cpu_1_jtag_debug_module_end_xfer = ~(cpu_1_jtag_debug_module_waits_for_read | cpu_1_jtag_debug_module_waits_for_write);

  //end_xfer_arb_share_counter_term_cpu_1_jtag_debug_module arb share counter enable term, which is an e_assign

  assign end_xfer_arb_share_counter_term_cpu_1_jtag_debug_module = cpu_1_jtag_debug_module_end_xfer & (~cpu_1_jtag_debug_module_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //cpu_1_jtag_debug_module_arb_share_counter arbitration counter enable, which is an e_assign

  assign cpu_1_jtag_debug_module_arb_counter_enable = (end_xfer_arb_share_counter_term_cpu_1_jtag_debug_module & cpu_1_jtag_debug_module_allgrants) | (end_xfer_arb_share_counter_term_cpu_1_jtag_debug_module & ~cpu_1_jtag_debug_module_non_bursting_master_requests);

  //cpu_1_jtag_debug_module_arb_share_counter counter, which is an e_register

  always @(posedge clk or negedge reset_n)

    begin

      if (reset_n == 0)

          cpu_1_jtag_debug_module_arb_share_counter <= 0;

      else if (cpu_1_jtag_debug_module_arb_counter_enable)

          cpu_1_jtag_debug_module_arb_share_counter <= cpu_1_jtag_debug_module_arb_share_counter_next_value;

    end

  //cpu_1_jtag_debug_module_slavearbiterlockenable slave enables arbiterlock, which is an e_register

  always @(posedge clk or negedge reset_n)

    begin

      if (reset_n == 0)

          cpu_1_jtag_debug_module_slavearbiterlockenable <= 0;

      else if ((|cpu_1_jtag_debug_module_master_qreq_vector & end_xfer_arb_share_counter_term_cpu_1_jtag_debug_module) | (end_xfer_arb_share_counter_term_cpu_1_jtag_debug_module & ~cpu_1_jtag_debug_module_non_bursting_master_requests))

          cpu_1_jtag_debug_module_slavearbiterlockenable <= |cpu_1_jtag_debug_module_arb_share_counter_next_value;

    end

  //cpu_1/data_master cpu_1/jtag_debug_module arbiterlock, which is an e_assign

  assign cpu_1_data_master_arbiterlock = cpu_1_jtag_debug_module_slavearbiterlockenable & cpu_1_data_master_continuerequest;

  //cpu_1_jtag_debug_module_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign

  assign cpu_1_jtag_debug_module_slavearbiterlockenable2 = |cpu_1_jtag_debug_module_arb_share_counter_next_value;

  //cpu_1/data_master cpu_1/jtag_debug_module arbiterlock2, which is an e_assign

  assign cpu_1_data_master_arbiterlock2 = cpu_1_jtag_debug_module_slavearbiterlockenable2 & cpu_1_data_master_continuerequest;

  //cpu_1/instruction_master cpu_1/jtag_debug_module arbiterlock, which is an e_assign

  assign cpu_1_instruction_master_arbiterlock = cpu_1_jtag_debug_module_slavearbiterlockenable & cpu_1_instruction_master_continuerequest;

  //cpu_1/instruction_master cpu_1/jtag_debug_module arbiterlock2, which is an e_assign

  assign cpu_1_instruction_master_arbiterlock2 = cpu_1_jtag_debug_module_slavearbiterlockenable2 & cpu_1_instruction_master_continuerequest;

  //cpu_1/instruction_master granted cpu_1/jtag_debug_module last time, which is an e_register

  always @(posedge clk or negedge reset_n)

    begin

      if (reset_n == 0)

          last_cycle_cpu_1_instruction_master_granted_slave_cpu_1_jtag_debug_module <= 0;

      else

        last_cycle_cpu_1_instruction_master_granted_slave_cpu_1_jtag_debug_module <= cpu_1_instruction_master_saved_grant_cpu_1_jtag_debug_module ? 1 : (cpu_1_jtag_debug_module_arbitration_holdoff_internal | ~cpu_1_instruction_master_requests_cpu_1_jtag_debug_module) ? 0 : last_cycle_cpu_1_instruction_master_granted_slave_cpu_1_jtag_debug_module;

    end

  //cpu_1_instruction_master_continuerequest continued request, which is an e_mux

  assign cpu_1_instruction_master_continuerequest = last_cycle_cpu_1_instruction_master_granted_slave_cpu_1_jtag_debug_module & cpu_1_instruction_master_requests_cpu_1_jtag_debug_module;

  //cpu_1_jtag_debug_module_any_continuerequest at least one master continues requesting, which is an e_mux

  assign cpu_1_jtag_debug_module_any_continuerequest = cpu_1_instruction_master_continuerequest |

    cpu_1_data_master_continuerequest;

  assign cpu_1_data_master_qualified_request_cpu_1_jtag_debug_module = cpu_1_data_master_requests_cpu_1_jtag_debug_module & ~((cpu_1_data_master_read & ((cpu_1_data_master_latency_counter != 0) | (|cpu_1_data_master_read_data_valid_sdram_1_s1_shift_register))) | cpu_1_instruction_master_arbiterlock);

  //local readdatavalid cpu_1_data_master_read_data_valid_cpu_1_jtag_debug_module, which is an e_mux

  assign cpu_1_data_master_read_data_valid_cpu_1_jtag_debug_module = cpu_1_data_master_granted_cpu_1_jtag_debug_module & cpu_1_data_master_read & ~cpu_1_jtag_debug_module_waits_for_read;

  //cpu_1_jtag_debug_module_writedata mux, which is an e_mux

  assign cpu_1_jtag_debug_module_writedata = cpu_1_data_master_writedata;

  assign cpu_1_instruction_master_requests_cpu_1_jtag_debug_module = (({cpu_1_instruction_master_address_to_slave[24 : 11] , 11'b0} == 25'h1000800) & (cpu_1_instruction_master_read)) & cpu_1_instruction_master_read;

  //cpu_1/data_master granted cpu_1/jtag_debug_module last time, which is an e_register

  always @(posedge clk or negedge reset_n)

    begin

      if (reset_n == 0)

          last_cycle_cpu_1_data_master_granted_slave_cpu_1_jtag_debug_module <= 0;

      else

        last_cycle_cpu_1_data_master_granted_slave_cpu_1_jtag_debug_module <= cpu_1_data_master_saved_grant_cpu_1_jtag_debug_module ? 1 : (cpu_1_jtag_debug_module_arbitration_holdoff_internal | ~cpu_1_data_master_requests_cpu_1_jtag_debug_module) ? 0 : last_cycle_cpu_1_data_master_granted_slave_cpu_1_jtag_debug_module;

    end

  //cpu_1_data_master_continuerequest continued request, which is an e_mux

  assign cpu_1_data_master_continuerequest = last_cycle_cpu_1_data_master_granted_slave_cpu_1_jtag_debug_module & cpu_1_data_master_requests_cpu_1_jtag_debug_module;

  assign cpu_1_instruction_master_qualified_request_cpu_1_jtag_debug_module = cpu_1_instruction_master_requests_cpu_1_jtag_debug_module & ~((cpu_1_instruction_master_read & ((cpu_1_instruction_master_latency_counter != 0) | (|cpu_1_instruction_master_read_data_valid_sdram_1_s1_shift_register))) | cpu_1_data_master_arbiterlock);

  //local readdatavalid cpu_1_instruction_master_read_data_valid_cpu_1_jtag_debug_module, which is an e_mux

  assign cpu_1_instruction_master_read_data_valid_cpu_1_jtag_debug_module = cpu_1_instruction_master_granted_cpu_1_jtag_debug_module & cpu_1_instruction_master_read & ~cpu_1_jtag_debug_module_waits_for_read;

  //allow new arb cycle for cpu_1/jtag_debug_module, which is an e_assign

  assign cpu_1_jtag_debug_module_allow_new_arb_cycle = ~cpu_1_data_master_arbiterlock & ~cpu_1_instruction_master_arbiterlock;

  //cpu_1/instruction_master assignment into master qualified-requests vector for cpu_1/jtag_debug_module, which is an e_assign

  assign cpu_1_jtag_debug_module_master_qreq_vector[0] = cpu_1_instruction_master_qualified_request_cpu_1_jtag_debug_module;

  //cpu_1/instruction_master grant cpu_1/jtag_debug_module, which is an e_assign

  assign cpu_1_instruction_master_granted_cpu_1_jtag_debug_module = cpu_1_jtag_debug_module_grant_vector[0];

  //cpu_1/instruction_master saved-grant cpu_1/jtag_debug_module, which is an e_assign

  assign cpu_1_instruction_master_saved_grant_cpu_1_jtag_debug_module = cpu_1_jtag_debug_module_arb_winner[0] && cpu_1_instruction_master_requests_cpu_1_jtag_debug_module;

  //cpu_1/data_master assignment into master qualified-requests vector for cpu_1/jtag_debug_module, which is an e_assign

  assign cpu_1_jtag_debug_module_master_qreq_vector[1] = cpu_1_data_master_qualified_request_cpu_1_jtag_debug_module;

  //cpu_1/data_master grant cpu_1/jtag_debug_module, which is an e_assign

  assign cpu_1_data_master_granted_cpu_1_jtag_debug_module = cpu_1_jtag_debug_module_grant_vector[1];

  //cpu_1/data_master saved-grant cpu_1/jtag_debug_module, which is an e_assign

  assign cpu_1_data_master_saved_grant_cpu_1_jtag_debug_module = cpu_1_jtag_debug_module_arb_winner[1] && cpu_1_data_master_requests_cpu_1_jtag_debug_module;

  //cpu_1/jtag_debug_module chosen-master double-vector, which is an e_assign

  assign cpu_1_jtag_debug_module_chosen_master_double_vector = {cpu_1_jtag_debug_module_master_qreq_vector, cpu_1_jtag_debug_module_master_qreq_vector} & ({~cpu_1_jtag_debug_module_master_qreq_vector, ~cpu_1_jtag_debug_module_master_qreq_vector} + cpu_1_jtag_debug_module_arb_addend);

  //stable onehot encoding of arb winner

  assign cpu_1_jtag_debug_module_arb_winner = (cpu_1_jtag_debug_module_allow_new_arb_cycle & | cpu_1_jtag_debug_module_grant_vector) ? cpu_1_jtag_debug_module_grant_vector : cpu_1_jtag_debug_module_saved_chosen_master_vector;

  //saved cpu_1_jtag_debug_module_grant_vector, which is an e_register

  always @(posedge clk or negedge reset_n)

    begin

      if (reset_n == 0)

          cpu_1_jtag_debug_module_saved_chosen_master_vector <= 0;

      else if (cpu_1_jtag_debug_module_allow_new_arb_cycle)

          cpu_1_jtag_debug_module_saved_chosen_master_vector <= |cpu_1_jtag_debug_module_grant_vector ? cpu_1_jtag_debug_module_grant_vector : cpu_1_jtag_debug_module_saved_chosen_master_vector;

    end

  //onehot encoding of chosen master

  assign cpu_1_jtag_debug_module_grant_vector = {(cpu_1_jtag_debug_module_chosen_master_double_vector[1] | cpu_1_jtag_debug_module_chosen_master_double_vector[3]),

    (cpu_1_jtag_debug_module_chosen_master_double_vector[0] | cpu_1_jtag_debug_module_chosen_master_double_vector[2])};

  //cpu_1/jtag_debug_module chosen master rotated left, which is an e_assign

  assign cpu_1_jtag_debug_module_chosen_master_rot_left = (cpu_1_jtag_debug_module_arb_winner << 1) ? (cpu_1_jtag_debug_module_arb_winner << 1) : 1;

  //cpu_1/jtag_debug_module's addend for next-master-grant

  always @(posedge clk or negedge reset_n)

    begin

      if (reset_n == 0)

          cpu_1_jtag_debug_module_arb_addend <= 1;

      else if (|cpu_1_jtag_debug_module_grant_vector)

          cpu_1_jtag_debug_module_arb_addend <= cpu_1_jtag_debug_module_end_xfer? cpu_1_jtag_debug_module_chosen_master_rot_left : cpu_1_jtag_debug_module_grant_vector;

    end

  assign cpu_1_jtag_debug_module_begintransfer = cpu_1_jtag_debug_module_begins_xfer;

  //cpu_1_jtag_debug_module_reset_n assignment, which is an e_assign

  assign cpu_1_jtag_debug_module_reset_n = reset_n;

  //assign cpu_1_jtag_debug_module_resetrequest_from_sa = cpu_1_jtag_debug_module_resetrequest so that symbol knows where to group signals which may go to master only, which is an e_assign

  assign cpu_1_jtag_debug_module_resetrequest_from_sa = cpu_1_jtag_debug_module_resetrequest;

  assign cpu_1_jtag_debug_module_chipselect = cpu_1_data_master_granted_cpu_1_jtag_debug_module | cpu_1_instruction_master_granted_cpu_1_jtag_debug_module;

  //cpu_1_jtag_debug_module_firsttransfer first transaction, which is an e_assign

  assign cpu_1_jtag_debug_module_firsttransfer = cpu_1_jtag_debug_module_begins_xfer ? cpu_1_jtag_debug_module_unreg_firsttransfer : cpu_1_jtag_debug_module_reg_firsttransfer;

  //cpu_1_jtag_debug_module_unreg_firsttransfer first transaction, which is an e_assign

  assign cpu_1_jtag_debug_module_unreg_firsttransfer = ~(cpu_1_jtag_debug_module_slavearbiterlockenable & cpu_1_jtag_debug_module_any_continuerequest);

  //cpu_1_jtag_debug_module_reg_firsttransfer first transaction, which is an e_register

  always @(posedge clk or negedge reset_n)

    begin

      if (reset_n == 0)

          cpu_1_jtag_debug_module_reg_firsttransfer <= 1'b1;

      else if (cpu_1_jtag_debug_module_begins_xfer)

          cpu_1_jtag_debug_module_reg_firsttransfer <= cpu_1_jtag_debug_module_unreg_firsttransfer;

    end

  //cpu_1_jtag_debug_module_beginbursttransfer_internal begin burst transfer, which is an e_assign

  assign cpu_1_jtag_debug_module_beginbursttransfer_internal = cpu_1_jtag_debug_module_begins_xfer;

  //cpu_1_jtag_debug_module_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign

  assign cpu_1_jtag_debug_module_arbitration_holdoff_internal = cpu_1_jtag_debug_module_begins_xfer & cpu_1_jtag_debug_module_firsttransfer;

  //cpu_1_jtag_debug_module_write assignment, which is an e_mux

  assign cpu_1_jtag_debug_module_write = cpu_1_data_master_granted_cpu_1_jtag_debug_module & cpu_1_data_master_write;

  assign shifted_address_to_cpu_1_jtag_debug_module_from_cpu_1_data_master = cpu_1_data_master_address_to_slave;

  //cpu_1_jtag_debug_module_address mux, which is an e_mux

  assign cpu_1_jtag_debug_module_address = (cpu_1_data_master_granted_cpu_1_jtag_debug_module)? (shifted_address_to_cpu_1_jtag_debug_module_from_cpu_1_data_master >> 2) :

    (shifted_address_to_cpu_1_jtag_debug_module_from_cpu_1_instruction_master >> 2);

  assign shifted_address_to_cpu_1_jtag_debug_module_from_cpu_1_instruction_master = cpu_1_instruction_master_address_to_slave;

  //d1_cpu_1_jtag_debug_module_end_xfer register, which is an e_register

  always @(posedge clk or negedge reset_n)

    begin

      if (reset_n == 0)

          d1_cpu_1_jtag_debug_module_end_xfer <= 1;

      else

        d1_cpu_1_jtag_debug_module_end_xfer <= cpu_1_jtag_debug_module_end_xfer;

    end

  //cpu_1_jtag_debug_module_waits_for_read in a cycle, which is an e_mux

  assign cpu_1_jtag_debug_module_waits_for_read = cpu_1_jtag_debug_module_in_a_read_cycle & cpu_1_jtag_debug_module_begins_xfer;

  //cpu_1_jtag_debug_module_in_a_read_cycle assignment, which is an e_assign

  assign cpu_1_jtag_debug_module_in_a_read_cycle = (cpu_1_data_master_granted_cpu_1_jtag_debug_module & cpu_1_data_master_read) | (cpu_1_instruction_master_granted_cpu_1_jtag_debug_module & cpu_1_instruction_master_read);

  //in_a_read_cycle assignment, which is an e_mux

  assign in_a_read_cycle = cpu_1_jtag_debug_module_in_a_read_cycle;

  //cpu_1_jtag_debug_module_waits_for_write in a cycle, which is an e_mux

  assign cpu_1_jtag_debug_module_waits_for_write = cpu_1_jtag_debug_module_in_a_write_cycle & 0;

  //cpu_1_jtag_debug_module_in_a_write_cycle assignment, which is an e_assign

  assign cpu_1_jtag_debug_module_in_a_write_cycle = cpu_1_data_master_granted_cpu_1_jtag_debug_module & cpu_1_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux

  assign in_a_write_cycle = cpu_1_jtag_debug_module_in_a_write_cycle;

  assign wait_for_cpu_1_jtag_debug_module_counter = 0;

  //cpu_1_jtag_debug_module_byteenable byte enable port mux, which is an e_mux

  assign cpu_1_jtag_debug_module_byteenable = (cpu_1_data_master_granted_cpu_1_jtag_debug_module)? cpu_1_data_master_byteenable :

    -1;

  //debugaccess mux, which is an e_mux

  assign cpu_1_jtag_debug_module_debugaccess = (cpu_1_data_master_granted_cpu_1_jtag_debug_module)? cpu_1_data_master_debugaccess :

    0;

//synthesis translate_off

//////////////// SIMULATION-ONLY CONTENTS

  //cpu_1/jtag_debug_module enable non-zero assertions, which is an e_register

  always @(posedge clk or negedge reset_n)

    begin

      if (reset_n == 0)

          enable_nonzero_assertions <= 0;

      else

        enable_nonzero_assertions <= 1'b1;

    end

  //grant signals are active simultaneously, which is an e_process

  always @(posedge clk)

    begin

      if (cpu_1_data_master_granted_cpu_1_jtag_debug_module + cpu_1_instruction_master_granted_cpu_1_jtag_debug_module > 1)

        begin

          $write("%0d ns: > 1 of grant signals are active simultaneously", $time);

          $stop;

        end

    end

  //saved_grant signals are active simultaneously, which is an e_process

  always @(posedge clk)

    begin

      if (cpu_1_data_master_saved_grant_cpu_1_jtag_debug_module + cpu_1_instruction_master_saved_grant_cpu_1_jtag_debug_module > 1)

        begin

          $write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time);

          $stop;

        end

    end

//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule

// synthesis translate_off

`timescale 1ns / 1ps

// synthesis translate_on

// turn off superfluous verilog processor warnings 

// altera message_level Level1 

// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cpu_1_data_master_arbitrator (

                                      // inputs:

                                       clk,

                                       cpu_1_data_master_address,

                                       cpu_1_data_master_byteenable,

                                       cpu_1_data_master_byteenable_sdram_1_s1,

                                       cpu_1_data_master_granted_cpu_1_jtag_debug_module,

                                       cpu_1_data_master_granted_hibi_pe_dma_1_avalon_slave_0,

                                       cpu_1_data_master_granted_jtag_uart_1_avalon_jtag_slave,

                                       cpu_1_data_master_granted_onchip_memory_1_s2,

                                       cpu_1_data_master_granted_sdram_1_s1,

                                       cpu_1_data_master_granted_timer_1_s1,

                                       cpu_1_data_master_qualified_request_cpu_1_jtag_debug_module,

                                       cpu_1_data_master_qualified_request_hibi_pe_dma_1_avalon_slave_0,

                                       cpu_1_data_master_qualified_request_jtag_uart_1_avalon_jtag_slave,

                                       cpu_1_data_master_qualified_request_onchip_memory_1_s2,

                                       cpu_1_data_master_qualified_request_sdram_1_s1,

                                       cpu_1_data_master_qualified_request_timer_1_s1,

                                       cpu_1_data_master_read,

                                       cpu_1_data_master_read_data_valid_cpu_1_jtag_debug_module,

                                       cpu_1_data_master_read_data_valid_hibi_pe_dma_1_avalon_slave_0,

                                       cpu_1_data_master_read_data_valid_jtag_uart_1_avalon_jtag_slave,

                                       cpu_1_data_master_read_data_valid_onchip_memory_1_s2,

                                       cpu_1_data_master_read_data_valid_sdram_1_s1,

                                       cpu_1_data_master_read_data_valid_sdram_1_s1_shift_register,

                                       cpu_1_data_master_read_data_valid_timer_1_s1,

                                       cpu_1_data_master_requests_cpu_1_jtag_debug_module,

                                       cpu_1_data_master_requests_hibi_pe_dma_1_avalon_slave_0,

                                       cpu_1_data_master_requests_jtag_uart_1_avalon_jtag_slave,

                                       cpu_1_data_master_requests_onchip_memory_1_s2,

                                       cpu_1_data_master_requests_sdram_1_s1,

                                       cpu_1_data_master_requests_timer_1_s1,

                                       cpu_1_data_master_write,

                                       cpu_1_data_master_writedata,

                                       cpu_1_jtag_debug_module_readdata_from_sa,

                                       d1_cpu_1_jtag_debug_module_end_xfer,

                                       d1_hibi_pe_dma_1_avalon_slave_0_end_xfer,

                                       d1_jtag_uart_1_avalon_jtag_slave_end_xfer,

                                       d1_onchip_memory_1_s2_end_xfer,

                                       d1_sdram_1_s1_end_xfer,

                                       d1_timer_1_s1_end_xfer,

                                       hibi_pe_dma_1_avalon_slave_0_irq_from_sa,

                                       hibi_pe_dma_1_avalon_slave_0_readdata_from_sa,

                                       hibi_pe_dma_1_avalon_slave_0_waitrequest_from_sa,

                                       jtag_uart_1_avalon_jtag_slave_irq_from_sa,

                                       jtag_uart_1_avalon_jtag_slave_readdata_from_sa,

                                       jtag_uart_1_avalon_jtag_slave_waitrequest_from_sa,

                                       onchip_memory_1_s2_readdata_from_sa,

                                       reset_n,

                                       sdram_1_s1_readdata_from_sa,

                                       sdram_1_s1_waitrequest_from_sa,

                                       timer_1_s1_irq_from_sa,

                                       timer_1_s1_readdata_from_sa,

                                      // outputs:

                                       cpu_1_data_master_address_to_slave,

                                       cpu_1_data_master_dbs_address,

                                       cpu_1_data_master_dbs_write_16,

                                       cpu_1_data_master_irq,

                                       cpu_1_data_master_latency_counter,

                                       cpu_1_data_master_readdata,

                                       cpu_1_data_master_readdatavalid,

                                       cpu_1_data_master_waitrequest

                                    )

;

  output  [ 24: 0] cpu_1_data_master_address_to_slave;

  output  [  1: 0] cpu_1_data_master_dbs_address;

  output  [ 15: 0] cpu_1_data_master_dbs_write_16;

  output  [ 31: 0] cpu_1_data_master_irq;

  output           cpu_1_data_master_latency_counter;

  output  [ 31: 0] cpu_1_data_master_readdata;

  output           cpu_1_data_master_readdatavalid;

  output           cpu_1_data_master_waitrequest;

  input            clk;

  input   [ 24: 0] cpu_1_data_master_address;

  input   [  3: 0] cpu_1_data_master_byteenable;

  input   [  1: 0] cpu_1_data_master_byteenable_sdram_1_s1;

  input            cpu_1_data_master_granted_cpu_1_jtag_debug_module;

  input            cpu_1_data_master_granted_hibi_pe_dma_1_avalon_slave_0;

  input            cpu_1_data_master_granted_jtag_uart_1_avalon_jtag_slave;

  input            cpu_1_data_master_granted_onchip_memory_1_s2;

  input            cpu_1_data_master_granted_sdram_1_s1;

  input            cpu_1_data_master_granted_timer_1_s1;

  input            cpu_1_data_master_qualified_request_cpu_1_jtag_debug_module;

  input            cpu_1_data_master_qualified_request_hibi_pe_dma_1_avalon_slave_0;

  input            cpu_1_data_master_qualified_request_jtag_uart_1_avalon_jtag_slave;

  input            cpu_1_data_master_qualified_request_onchip_memory_1_s2;

  input            cpu_1_data_master_qualified_request_sdram_1_s1;

  input            cpu_1_data_master_qualified_request_timer_1_s1;

  input            cpu_1_data_master_read;

  input            cpu_1_data_master_read_data_valid_cpu_1_jtag_debug_module;

  input            cpu_1_data_master_read_data_valid_hibi_pe_dma_1_avalon_slave_0;

  input            cpu_1_data_master_read_data_valid_jtag_uart_1_avalon_jtag_slave;

  input            cpu_1_data_master_read_data_valid_onchip_memory_1_s2;

  input            cpu_1_data_master_read_data_valid_sdram_1_s1;

  input            cpu_1_data_master_read_data_valid_sdram_1_s1_shift_register;

  input            cpu_1_data_master_read_data_valid_timer_1_s1;

  input            cpu_1_data_master_requests_cpu_1_jtag_debug_module;

  input            cpu_1_data_master_requests_hibi_pe_dma_1_avalon_slave_0;

  input            cpu_1_data_master_requests_jtag_uart_1_avalon_jtag_slave;

  input            cpu_1_data_master_requests_onchip_memory_1_s2;

  input            cpu_1_data_master_requests_sdram_1_s1;

  input            cpu_1_data_master_requests_timer_1_s1;

  input            cpu_1_data_master_write;

  input   [ 31: 0] cpu_1_data_master_writedata;

  input   [ 31: 0] cpu_1_jtag_debug_module_readdata_from_sa;

  input            d1_cpu_1_jtag_debug_module_end_xfer;

  input            d1_hibi_pe_dma_1_avalon_slave_0_end_xfer;

  input            d1_jtag_uart_1_avalon_jtag_slave_end_xfer;

  input            d1_onchip_memory_1_s2_end_xfer;

  input            d1_sdram_1_s1_end_xfer;

  input            d1_timer_1_s1_end_xfer;

  input            hibi_pe_dma_1_avalon_slave_0_irq_from_sa;

  input   [ 31: 0] hibi_pe_dma_1_avalon_slave_0_readdata_from_sa;

  input            hibi_pe_dma_1_avalon_slave_0_waitrequest_from_sa;

  input            jtag_uart_1_avalon_jtag_slave_irq_from_sa;

  input   [ 31: 0] jtag_uart_1_avalon_jtag_slave_readdata_from_sa;

  input            jtag_uart_1_avalon_jtag_slave_waitrequest_from_sa;

  input   [ 31: 0] onchip_memory_1_s2_readdata_from_sa;

  input            reset_n;

  input   [ 15: 0] sdram_1_s1_readdata_from_sa;

  input            sdram_1_s1_waitrequest_from_sa;

  input            timer_1_s1_irq_from_sa;

  input   [ 15: 0] timer_1_s1_readdata_from_sa;

  reg              active_and_waiting_last_time;

  reg     [ 24: 0] cpu_1_data_master_address_last_time;

  wire    [ 24: 0] cpu_1_data_master_address_to_slave;

  reg     [  3: 0] cpu_1_data_master_byteenable_last_time;

  reg     [  1: 0] cpu_1_data_master_dbs_address;

  wire    [  1: 0] cpu_1_data_master_dbs_increment;

  reg     [  1: 0] cpu_1_data_master_dbs_rdv_counter;

  wire    [  1: 0] cpu_1_data_master_dbs_rdv_counter_inc;

  wire    [ 15: 0] cpu_1_data_master_dbs_write_16;

  wire    [ 31: 0] cpu_1_data_master_irq;

  wire             cpu_1_data_master_is_granted_some_slave;

  reg              cpu_1_data_master_latency_counter;

  wire    [  1: 0] cpu_1_data_master_next_dbs_rdv_counter;

  reg              cpu_1_data_master_read_but_no_slave_selected;

  reg              cpu_1_data_master_read_last_time;

  wire    [ 31: 0] cpu_1_data_master_readdata;

  wire             cpu_1_data_master_readdatavalid;

  wire             cpu_1_data_master_run;

  wire             cpu_1_data_master_waitrequest;

  reg              cpu_1_data_master_write_last_time;

  reg     [ 31: 0] cpu_1_data_master_writedata_last_time;

  wire             dbs_count_enable;

  wire             dbs_counter_overflow;

  reg     [ 15: 0] dbs_latent_16_reg_segment_0;

  wire             dbs_rdv_count_enable;

  wire             dbs_rdv_counter_overflow;

  wire             latency_load_value;

  wire    [  1: 0] next_dbs_address;

  wire             p1_cpu_1_data_master_latency_counter;

  wire    [ 15: 0] p1_dbs_latent_16_reg_segment_0;

  wire             pre_dbs_count_enable;

  wire             pre_flush_cpu_1_data_master_readdatavalid;

  wire             r_0;

  wire             r_1;

  //r_0 master_run cascaded wait assignment, which is an e_assign

  assign r_0 = 1 & (cpu_1_data_master_qualified_request_cpu_1_jtag_debug_module | ~cpu_1_data_master_requests_cpu_1_jtag_debug_module) & (cpu_1_data_master_granted_cpu_1_jtag_debug_module | ~cpu_1_data_master_qualified_request_cpu_1_jtag_debug_module) & ((~cpu_1_data_master_qualified_request_cpu_1_jtag_debug_module | ~cpu_1_data_master_read | (1 & ~d1_cpu_1_jtag_debug_module_end_xfer & cpu_1_data_master_read))) & ((~cpu_1_data_master_qualified_request_cpu_1_jtag_debug_module | ~cpu_1_data_master_write | (1 & cpu_1_data_master_write))) & 1 & (cpu_1_data_master_qualified_request_hibi_pe_dma_1_avalon_slave_0 | ~cpu_1_data_master_requests_hibi_pe_dma_1_avalon_slave_0) & ((~cpu_1_data_master_qualified_request_hibi_pe_dma_1_avalon_slave_0 | ~(cpu_1_data_master_read | cpu_1_data_master_write) | (1 & ~hibi_pe_dma_1_avalon_slave_0_waitrequest_from_sa & (cpu_1_data_master_read | cpu_1_data_master_write)))) & ((~cpu_1_data_master_qualified_request_hibi_pe_dma_1_avalon_slave_0 | ~(cpu_1_data_master_read | cpu_1_data_master_write) | (1 & ~hibi_pe_dma_1_avalon_slave_0_waitrequest_from_sa & (cpu_1_data_master_read | cpu_1_data_master_write)))) & 1 & (cpu_1_data_master_qualified_request_jtag_uart_1_avalon_jtag_slave | ~cpu_1_data_master_requests_jtag_uart_1_avalon_jtag_slave) & ((~cpu_1_data_master_qualified_request_jtag_uart_1_avalon_jtag_slave | ~(cpu_1_data_master_read | cpu_1_data_master_write) | (1 & ~jtag_uart_1_avalon_jtag_slave_waitrequest_from_sa & (cpu_1_data_master_read | cpu_1_data_master_write)))) & ((~cpu_1_data_master_qualified_request_jtag_uart_1_avalon_jtag_slave | ~(cpu_1_data_master_read | cpu_1_data_master_write) | (1 & ~jtag_uart_1_avalon_jtag_slave_waitrequest_from_sa & (cpu_1_data_master_read | cpu_1_data_master_write)))) & 1 & (cpu_1_data_master_qualified_request_onchip_memory_1_s2 | ~cpu_1_data_master_requests_onchip_memory_1_s2) & ((~cpu_1_data_master_qualified_request_onchip_memory_1_s2 | ~(cpu_1_data_master_read | cpu_1_data_master_write) | (1 & (cpu_1_data_master_read | cpu_1_data_master_write)))) & ((~cpu_1_data_master_qualified_request_onchip_memory_1_s2 | ~(cpu_1_data_master_read | cpu_1_data_master_write) | (1 & (cpu_1_data_master_read | cpu_1_data_master_write)))) & 1 & (cpu_1_data_master_qualified_request_sdram_1_s1 | (cpu_1_data_master_write & !cpu_1_data_master_byteenable_sdram_1_s1 & cpu_1_data_master_dbs_address[1]) | ~cpu_1_data_master_requests_sdram_1_s1) & (cpu_1_data_master_granted_sdram_1_s1 | ~cpu_1_data_master_qualified_request_sdram_1_s1);

  //cascaded wait assignment, which is an e_assign

  assign cpu_1_data_master_run = r_0 & r_1;

  //r_1 master_run cascaded wait assignment, which is an e_assign

  assign r_1 = ((~cpu_1_data_master_qualified_request_sdram_1_s1 | ~cpu_1_data_master_read | (1 & ~sdram_1_s1_waitrequest_from_sa & (cpu_1_data_master_dbs_address[1]) & cpu_1_data_master_read))) & ((~cpu_1_data_master_qualified_request_sdram_1_s1 | ~cpu_1_data_master_write | (1 & ~sdram_1_s1_waitrequest_from_sa & (cpu_1_data_master_dbs_address[1]) & cpu_1_data_master_write))) & 1 & (cpu_1_data_master_qualified_request_timer_1_s1 | ~cpu_1_data_master_requests_timer_1_s1) & ((~cpu_1_data_master_qualified_request_timer_1_s1 | ~cpu_1_data_master_read | (1 & ~d1_timer_1_s1_end_xfer & cpu_1_data_master_read))) & ((~cpu_1_data_master_qualified_request_timer_1_s1 | ~cpu_1_data_master_write | (1 & cpu_1_data_master_write)));

  //optimize select-logic by passing only those address bits which matter.

  assign cpu_1_data_master_address_to_slave = cpu_1_data_master_address[24 : 0];

  //cpu_1_data_master_read_but_no_slave_selected assignment, which is an e_register

  always @(posedge clk or negedge reset_n)

    begin

      if (reset_n == 0)

          cpu_1_data_master_read_but_no_slave_selected <= 0;

      else

        cpu_1_data_master_read_but_no_slave_selected <= cpu_1_data_master_read & cpu_1_data_master_run & ~cpu_1_data_master_is_granted_some_slave;

    end

  //some slave is getting selected, which is an e_mux

  assign cpu_1_data_master_is_granted_some_slave = cpu_1_data_master_granted_cpu_1_jtag_debug_module |

    cpu_1_data_master_granted_hibi_pe_dma_1_avalon_slave_0 |

    cpu_1_data_master_granted_jtag_uart_1_avalon_jtag_slave |

    cpu_1_data_master_granted_onchip_memory_1_s2 |

    cpu_1_data_master_granted_sdram_1_s1 |

    cpu_1_data_master_granted_timer_1_s1;

  //latent slave read data valids which may be flushed, which is an e_mux