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[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.communication/] [pkt_codec_mk2/] [1.0/] [vhd/] [addr_gen.vhd] - Blame information for rev 147

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1 145 lanttu 
-------------------------------------------------------------------------------
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-- Title      : Address generator for pkt_codec
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-- Project    :
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-------------------------------------------------------------------------------
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-- File       : addr_gen.vhd
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-- Author     : Lasse Lehtonen
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-- Company    :
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-- Created    : 2011-10-12
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-- Last update: 2012-05-10
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-- Platform   :
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-- Standard   : VHDL'87
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-------------------------------------------------------------------------------
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-- Description:
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--  Handles address flit repeating when data comes slowly from IP and
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--  prevents sending only address flits without at least on data flit.
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--
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-------------------------------------------------------------------------------
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-- Copyright (c) 2011
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-------------------------------------------------------------------------------
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-- Revisions  :
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-- Date        Version  Author  Description
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-- 2011-10-12  1.0      lehton87        Created
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity addr_gen is
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  generic (
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    cmd_width_g    : positive;
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    data_width_g   : positive;
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    addr_flit_en_g : natural;
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    noc_type_g     : natural);
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  port (
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    clk          : in  std_logic;
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    rst_n        : in  std_logic;
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    -- from IP side
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    ip_cmd_in    : in  std_logic_vector(cmd_width_g-1 downto 0);
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    ip_data_in   : in  std_logic_vector(data_width_g-1 downto 0);
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    ip_stall_out : out std_logic;
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    orig_addr_in : in  std_logic_vector(data_width_g-1 downto 0);
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    -- to NET
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    net_cmd_out  : out std_logic_vector(cmd_width_g-1 downto 0);
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    net_data_out : out std_logic_vector(data_width_g-1 downto 0);
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    net_stall_in : in  std_logic);
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end addr_gen;
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architecture rtl of addr_gen is
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  signal cmd_r        : std_logic_vector(cmd_width_g-1 downto 0);
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  signal data_r       : std_logic_vector(data_width_g-1 downto 0);
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  signal addr_r       : std_logic_vector(data_width_g-1 downto 0);
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  signal stall_r      : std_logic;
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  signal first_data_r : std_logic;
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  type   state_type is (idle, addr, orig, data);
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  signal state_r : state_type;
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begin  -- rtl
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  ip_stall_out <= net_stall_in or stall_r;
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  fsm_p : process (clk, rst_n)
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  begin  -- process fsm_p
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    if rst_n = '0' then                 -- asynchronous reset (active low)
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      state_r      <= idle;
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      cmd_r        <= (others => '0');
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      data_r       <= (others => '0');
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      addr_r       <= (others => '0');
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      stall_r      <= '0';
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      first_data_r <= '0';
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      net_cmd_out  <= (others => '0');
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      net_data_out <= (others => '0');
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    elsif clk'event and clk = '1' then  -- rising clock edge
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      -- FH mesh
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      if noc_type_g = 3 then
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        if net_stall_in = '0' then
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          net_cmd_out <= ip_cmd_in;
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          net_data_out <= ip_data_in;
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        end if;
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      end if;
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      -- ase nocs
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      if noc_type_g /= 3 then
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        -- default
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        if net_stall_in = '0' then
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          stall_r <= '0';
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        end if;
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        case state_r is
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          ---------------------------------------------------------------------
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          -- IDLE
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          ---------------------------------------------------------------------
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          when idle =>
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            if net_stall_in = '0' then
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              if ip_cmd_in = "00" then
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                net_cmd_out  <= "00";
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                first_data_r <= '0';
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              elsif ip_cmd_in = "01" then
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                net_cmd_out  <= "00";
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                first_data_r <= '1';
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                addr_r       <= ip_data_in;
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                state_r      <= addr;
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              else
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                first_data_r <= '1';
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                data_r       <= ip_data_in;
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                net_cmd_out  <= "01";
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                net_data_out <= addr_r;
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                state_r      <= data;
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              end if;
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            end if;
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            -------------------------------------------------------------------
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            -- ADDR
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            -------------------------------------------------------------------
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          when addr =>
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            if net_stall_in = '0' then
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              if ip_cmd_in = "00" then
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                state_r      <= idle;
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                net_cmd_out  <= "00";
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                first_data_r <= '0';
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              elsif ip_cmd_in = "01" then
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                addr_r       <= ip_data_in;
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                state_r      <= addr;
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                net_cmd_out  <= "00";
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                first_data_r <= '1';
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              else
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                net_cmd_out  <= "01";
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                net_data_out <= addr_r;
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                data_r       <= ip_data_in;
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                state_r      <= data;
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              end if;
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            end if;
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            -------------------------------------------------------------------
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            -- DATA
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            -------------------------------------------------------------------
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          when data =>
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            if net_stall_in = '0' then
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              if ip_cmd_in = "00" then
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                if first_data_r = '1' and addr_flit_en_g = 1 then
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                  stall_r      <= '1';
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                  net_cmd_out  <= "10";
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                  net_data_out <= orig_addr_in;
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                  first_data_r <= '0';
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                else
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                  net_data_out <= data_r;
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                  net_cmd_out  <= "10";
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                  state_r      <= idle;
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                end if;
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              elsif ip_cmd_in = "01" then
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                if first_data_r = '1' and addr_flit_en_g = 1 then
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                  stall_r      <= '1';
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                  net_cmd_out  <= "10";
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                  net_data_out <= orig_addr_in;
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                  first_data_r <= '0';
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                else
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                  net_data_out <= data_r;
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                  net_cmd_out  <= "10";
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                  addr_r       <= ip_data_in;
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                  state_r      <= addr;
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                  first_data_r <= '1';  -- ase 25-10-2011
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                end if;
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              else
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                if first_data_r = '1' and addr_flit_en_g = 1 then
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                  stall_r      <= '1';
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                  net_cmd_out  <= "10";
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                  net_data_out <= orig_addr_in;
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                  first_data_r <= '0';
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                else
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                  net_data_out <= data_r;
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                  net_cmd_out  <= "10";
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                  data_r       <= ip_data_in;
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                end if;
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              end if;
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            end if;
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          when others => null;
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        end case;
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      end if;
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    end if;
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  end process fsm_p;
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end rtl;

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