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URL https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk

Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.interface/] [udp2hibi/] [1.0/] [udp2hibi.1.0.xml] - Blame information for rev 183

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Line No. Rev Author Line
1 145 lanttu
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        TUT
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        ip.hwp.interface
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        udp2hibi
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        1.0
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        - Interface between a UDP/IP block and the HIBI bus.
12 
- Capable of handling one transmission and one incoming packet at a time
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- UDP2HIBI uses HIBI addresses to separate transfers from different agents
14 
- So all agents must use different addresses when sending to UDP2HIBI
15
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                        clk
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                        clock input
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                        false
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                                                CLK
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                                                        0
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                                                        0
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                                                clk
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                                                        0
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                                                        0
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                        8
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                        little
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                        clk_udp
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                        clock udp input (25MHz)
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                        false
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                                                CLK
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                                                        0
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                                                        0
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                                                clk_udp
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                                                        0
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                                                        0
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                        8
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                        little
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                        hibi_master
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                        HIBI master interface
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                        false
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                                                AV
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                                                        0
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                                                        0
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                                                hibi_av_out
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                                                        0
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                                                        0
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                                                COMM
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                                                        4
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                                                        0
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                                                hibi_comm_out
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                                                        4
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                                                        0
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                                                DATA
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                                                        31
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                                                        0
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                                                hibi_data_out
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                                                        31
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                                                        0
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                                                RE
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                                                        0
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                                                        0
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                                                hibi_re_out
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140 
                                                        0
141 
                                                        0
142
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145
146
147 
                                                WE
148
149 
                                                        0
150 
                                                        0
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152
153
154 
                                                hibi_we_out
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156 
                                                        0
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                                                        0
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159
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162 
                        8
163 
                        little
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165
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                        rst_n
167 
                        active low reset
168
169
170
171 
                        false
172
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                                                RESETn
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                                                        0
178 
                                                        0
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182 
                                                rst_n
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184 
                                                        0
185 
                                                        0
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187
188
189
190 
                        8
191 
                        little
192
193
194 
                        udp_ip_rx
195 
                        udp_ip_rx
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199 
                        false
200
201
202
203 
                                                source_port_out
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205 
                                                        15
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                                                        0
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                                                source_port_in
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212 
                                                        15
213 
                                                        0
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215
216
217
218
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                                                dest_port_out
220
221 
                                                        15
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                                                        0
223
224
225
226 
                                                dest_port_in
227
228 
                                                        15
229 
                                                        0
230
231
232
233
234
235 
                                                source_addr_out
236
237 
                                                        31
238 
                                                        0
239
240
241
242 
                                                source_ip_in
243
244 
                                                        31
245 
                                                        0
246
247
248
249
250
251 
                                                rx_re_in
252
253 
                                                        0
254 
                                                        0
255
256
257
258 
                                                rx_re_out
259
260 
                                                        0
261 
                                                        0
262
263
264
265
266
267 
                                                rx_len_out
268
269 
                                                        10
270 
                                                        0
271
272
273
274 
                                                rx_len_in
275
276 
                                                        10
277 
                                                        0
278
279
280
281
282
283 
                                                rx_erroneous_out
284
285 
                                                        0
286 
                                                        0
287
288
289
290 
                                                rx_erroneous_in
291
292 
                                                        0
293 
                                                        0
294
295
296
297
298
299 
                                                rx_data_valid_out
300
301 
                                                        0
302 
                                                        0
303
304
305
306 
                                                rx_data_valid_in
307
308 
                                                        0
309 
                                                        0
310
311
312
313
314
315 
                                                new_rx_out
316
317 
                                                        0
318 
                                                        0
319
320
321
322 
                                                new_rx_in
323
324 
                                                        0
325 
                                                        0
326
327
328
329
330
331 
                                                rx_data_out
332
333 
                                                        15
334 
                                                        0
335
336
337
338 
                                                rx_data_in
339
340 
                                                        15
341 
                                                        0
342
343
344
345
346
347 
                                                link_up_out
348
349 
                                                        0
350 
                                                        0
351
352
353
354 
                                                eth_link_up_in
355
356 
                                                        0
357 
                                                        0
358
359
360
361
362 
                        8
363 
                        little
364
365
366 
                        udp_ip_tx
367 
                        udp_ip_tx
368
369
370
371 
                        false
372
373
374
375 
                                                tx_data_in
376
377 
                                                        15
378 
                                                        0
379
380
381
382 
                                                tx_data_out
383
384 
                                                        15
385 
                                                        0
386
387
388
389
390
391 
                                                tx_len_in
392
393 
                                                        10
394 
                                                        0
395
396
397
398 
                                                tx_len_out
399
400 
                                                        10
401 
                                                        0
402
403
404
405
406
407 
                                                tx_re_out
408
409 
                                                        0
410 
                                                        0
411
412
413
414 
                                                tx_re_in
415
416 
                                                        0
417 
                                                        0
418
419
420
421
422
423 
                                                tx_data_valid_in
424
425 
                                                        0
426 
                                                        0
427
428
429
430 
                                                tx_data_valid_out
431
432 
                                                        0
433 
                                                        0
434
435
436
437
438
439 
                                                new_tx_in
440
441 
                                                        0
442 
                                                        0
443
444
445
446 
                                                new_tx_out
447
448 
                                                        0
449 
                                                        0
450
451
452
453
454
455 
                                                target_addr_in
456
457 
                                                        31
458 
                                                        0
459
460
461
462 
                                                dest_ip_out
463
464 
                                                        31
465 
                                                        0
466
467
468
469
470
471 
                                                target_port_in
472
473 
                                                        15
474 
                                                        0
475
476
477
478 
                                                dest_port_out
479
480 
                                                        15
481 
                                                        0
482
483
484
485
486
487 
                                                source_port_in
488
489 
                                                        15
490 
                                                        0
491
492
493
494 
                                                source_port_out
495
496 
                                                        15
497 
                                                        0
498
499
500
501
502 
                        8
503 
                        little
504
505
506 
                        hibi_slave
507 
                        HIBI slave interface
508
509
510 157 lanttu
511
512
513 145 lanttu 
                        false
514
515
516
517 
                                                AV
518
519 
                                                        0
520 
                                                        0
521
522
523
524 
                                                hibi_av_in
525
526 
                                                        0
527 
                                                        0
528
529
530
531
532
533 
                                                COMM
534
535 
                                                        4
536 
                                                        0
537
538
539
540 
                                                hibi_comm_in
541
542 
                                                        4
543 
                                                        0
544
545
546
547
548
549 
                                                DATA
550
551 
                                                        31
552 
                                                        0
553
554
555
556 
                                                hibi_data_in
557
558 
                                                        31
559 
                                                        0
560
561
562
563
564
565 
                                                EMPTY
566
567 
                                                        0
568 
                                                        0
569
570
571
572 
                                                hibi_empty_in
573
574 
                                                        0
575 
                                                        0
576
577
578
579
580
581 
                                                FULL
582
583 
                                                        0
584 
                                                        0
585
586
587
588 
                                                hibi_full_in
589
590 
                                                        0
591 
                                                        0
592
593
594
595
596 
                        8
597 
                        little
598
599
600 157 lanttu
601
602 
                        udp2hibi_memmap
603 183 lanttu 
                        hibi memory map
604 157 lanttu
605 
                                registers
606 
                                0x0
607 
                                4
608 
                                32
609 
                                register
610
611 
                                        TX_cntrl
612 
                                        0
613 
                                        0x0
614 
                                        32
615
616
617 
                                        RX_cntrl
618 
                                        0
619 183 lanttu 
                                        0x1
620 157 lanttu 
                                        32
621
622 183 lanttu
623 
                                        lock_state
624 
                                        0
625 
                                        0x3
626 
                                        32
627
628 157 lanttu
629 
                        32
630
631
632 145 lanttu
633
634
635 
                                rtl
636 
                                ::
637
638 
                                        hdlSources
639
640
641
642
643
644 
                                clk
645
646 
                                        in
647
648 
                                                0
649 
                                                0
650
651
652
653 
                                                        std_logic
654 
                                                        IEEE.std_logic_1164.all
655 
                                                        rtl
656
657
658
659
660
661
662 
                                clk_udp
663
664 
                                        in
665
666 
                                                0
667 
                                                0
668
669
670
671 
                                                        std_logic
672 
                                                        IEEE.std_logic_1164.all
673 
                                                        rtl
674
675
676
677
678
679
680 
                                dest_ip_out
681
682 
                                        out
683
684 
                                                31
685 
                                                0
686
687
688
689 
                                                        std_logic_vector
690 
                                                        IEEE.std_logic_1164.all
691 
                                                        rtl
692
693
694
695
696
697
698 
                                dest_port_in
699
700 
                                        in
701
702 
                                                15
703 
                                                0
704
705
706
707 
                                                        std_logic_vector
708 
                                                        IEEE.std_logic_1164.all
709 
                                                        rtl
710
711
712
713
714
715
716 
                                dest_port_out
717
718 
                                        out
719
720 
                                                15
721 
                                                0
722
723
724
725 
                                                        std_logic_vector
726 
                                                        IEEE.std_logic_1164.all
727 
                                                        rtl
728
729
730
731
732
733
734 
                                eth_link_up_in
735
736 
                                        in
737
738 
                                                0
739 
                                                0
740
741
742
743 
                                                        std_logic
744 
                                                        IEEE.std_logic_1164.all
745 
                                                        rtl
746
747
748
749
750
751
752 
                                hibi_av_in
753
754 
                                        in
755
756 
                                                0
757 
                                                0
758
759
760
761 
                                                        std_logic
762 
                                                        IEEE.std_logic_1164.all
763 
                                                        rtl
764
765
766
767
768
769
770 
                                hibi_av_out
771
772 
                                        out
773
774 
                                                0
775 
                                                0
776
777
778
779 
                                                        std_logic
780 
                                                        IEEE.std_logic_1164.all
781 
                                                        rtl
782
783
784
785
786
787
788 
                                hibi_comm_in
789
790 
                                        in
791
792 
                                                4
793 
                                                0
794
795
796
797 
                                                        std_logic_vector
798 
                                                        IEEE.std_logic_1164.all
799 
                                                        rtl
800
801
802
803
804
805
806 
                                hibi_comm_out
807
808 
                                        out
809
810 
                                                4
811 
                                                0
812
813
814
815 
                                                        std_logic_vector
816 
                                                        IEEE.std_logic_1164.all
817 
                                                        rtl
818
819
820
821
822
823
824 
                                hibi_data_in
825
826 
                                        in
827
828 
                                                31
829 
                                                0
830
831
832
833 
                                                        std_logic_vector
834 
                                                        IEEE.std_logic_1164.all
835 
                                                        rtl
836
837
838
839
840
841
842 
                                hibi_data_out
843
844 
                                        out
845
846 
                                                31
847 
                                                0
848
849
850
851 
                                                        std_logic_vector
852 
                                                        IEEE.std_logic_1164.all
853 
                                                        rtl
854
855
856
857
858
859
860 
                                hibi_empty_in
861
862 
                                        in
863
864 
                                                0
865 
                                                0
866
867
868
869 
                                                        std_logic
870 
                                                        IEEE.std_logic_1164.all
871 
                                                        rtl
872
873
874
875
876
877
878 
                                hibi_full_in
879
880 
                                        in
881
882 
                                                0
883 
                                                0
884
885
886
887 
                                                        std_logic
888 
                                                        IEEE.std_logic_1164.all
889 
                                                        rtl
890
891
892
893
894
895
896 
                                hibi_re_out
897
898 
                                        out
899
900 
                                                0
901 
                                                0
902
903
904
905 
                                                        std_logic
906 
                                                        IEEE.std_logic_1164.all
907 
                                                        rtl
908
909
910
911
912
913
914 
                                hibi_we_out
915
916 
                                        out
917
918 
                                                0
919 
                                                0
920
921
922
923 
                                                        std_logic
924 
                                                        IEEE.std_logic_1164.all
925 
                                                        rtl
926
927
928
929
930
931
932 
                                new_rx_in
933
934 
                                        in
935
936 
                                                0
937 
                                                0
938
939
940
941 
                                                        std_logic
942 
                                                        IEEE.std_logic_1164.all
943 
                                                        rtl
944
945
946
947
948
949
950 
                                new_tx_out
951
952 
                                        out
953
954 
                                                0
955 
                                                0
956
957
958
959 
                                                        std_logic
960 
                                                        IEEE.std_logic_1164.all
961 
                                                        rtl
962
963
964
965
966
967
968 
                                rst_n
969
970 
                                        in
971
972 
                                                0
973 
                                                0
974
975
976
977 
                                                        std_logic
978 
                                                        IEEE.std_logic_1164.all
979 
                                                        rtl
980
981
982
983
984
985
986 
                                rx_data_in
987
988 
                                        in
989
990 
                                                15
991 
                                                0
992
993
994
995 
                                                        std_logic_vector
996 
                                                        IEEE.std_logic_1164.all
997 
                                                        rtl
998
999
1000
1001
1002
1003
1004 
                                rx_data_valid_in
1005
1006 
                                        in
1007
1008 
                                                0
1009 
                                                0
1010
1011
1012
1013 
                                                        std_logic
1014 
                                                        IEEE.std_logic_1164.all
1015 
                                                        rtl
1016
1017
1018
1019
1020
1021
1022 
                                rx_erroneous_in
1023
1024 
                                        in
1025
1026 
                                                0
1027 
                                                0
1028
1029
1030
1031 
                                                        std_logic
1032 
                                                        IEEE.std_logic_1164.all
1033 
                                                        rtl
1034
1035
1036
1037
1038
1039
1040 
                                rx_len_in
1041
1042 
                                        in
1043
1044 
                                                10
1045 
                                                0
1046
1047
1048
1049 
                                                        std_logic_vector
1050 
                                                        IEEE.std_logic_1164.all
1051 
                                                        rtl
1052
1053
1054
1055
1056
1057
1058 
                                rx_re_out
1059
1060 
                                        out
1061
1062 
                                                0
1063 
                                                0
1064
1065
1066
1067 
                                                        std_logic
1068 
                                                        IEEE.std_logic_1164.all
1069 
                                                        rtl
1070
1071
1072
1073
1074
1075
1076 
                                source_ip_in
1077
1078 
                                        in
1079
1080 
                                                31
1081 
                                                0
1082
1083
1084
1085 
                                                        std_logic_vector
1086 
                                                        IEEE.std_logic_1164.all
1087 
                                                        rtl
1088
1089
1090
1091
1092
1093
1094 
                                source_port_in
1095
1096 
                                        in
1097
1098 
                                                15
1099 
                                                0
1100
1101
1102
1103 
                                                        std_logic_vector
1104 
                                                        IEEE.std_logic_1164.all
1105 
                                                        rtl
1106
1107
1108
1109
1110
1111
1112 
                                source_port_out
1113
1114 
                                        out
1115
1116 
                                                15
1117 
                                                0
1118
1119
1120
1121 
                                                        std_logic_vector
1122 
                                                        IEEE.std_logic_1164.all
1123 
                                                        rtl
1124
1125
1126
1127
1128
1129
1130 
                                tx_data_out
1131
1132 
                                        out
1133
1134 
                                                15
1135 
                                                0
1136
1137
1138
1139 
                                                        std_logic_vector
1140 
                                                        IEEE.std_logic_1164.all
1141 
                                                        rtl
1142
1143
1144
1145
1146
1147
1148 
                                tx_data_valid_out
1149
1150 
                                        out
1151
1152 
                                                0
1153 
                                                0
1154
1155
1156
1157 
                                                        std_logic
1158 
                                                        IEEE.std_logic_1164.all
1159 
                                                        rtl
1160
1161
1162
1163
1164
1165
1166 
                                tx_len_out
1167
1168 
                                        out
1169
1170 
                                                10
1171 
                                                0
1172
1173
1174
1175 
                                                        std_logic_vector
1176 
                                                        IEEE.std_logic_1164.all
1177 
                                                        rtl
1178
1179
1180
1181
1182
1183
1184 
                                tx_re_in
1185
1186 
                                        in
1187
1188 
                                                0
1189 
                                                0
1190
1191
1192
1193 
                                                        std_logic
1194 
                                                        IEEE.std_logic_1164.all
1195 
                                                        rtl
1196
1197
1198
1199
1200
1201
1202
1203
1204 
                                ack_fifo_depth_g
1205 
                                4
1206
1207
1208 
                                frequency_g
1209 
                                50000000
1210
1211
1212 
                                hibi_addr_width_g
1213 
                                32
1214
1215
1216 
                                hibi_comm_width_g
1217 
                                5
1218
1219
1220 
                                hibi_data_width_g
1221 
                                32
1222
1223
1224 
                                hibi_tx_fifo_depth_g
1225 
                                10
1226
1227
1228 
                                receiver_table_size_g
1229 
                                4
1230
1231
1232 
                                rx_multiclk_fifo_depth_g
1233 
                                10
1234
1235
1236 
                                tx_multiclk_fifo_depth_g
1237 
                                10
1238
1239
1240
1241
1242
1243 
                        hdlSources
1244
1245 
                                vhd/udp2hibi_pkg.vhd
1246 
                                vhdlSource
1247 
                                false
1248 
                                udp2hibi
1249
1250
1251 
                                vhd/ctrl_regs.vhd
1252 
                                vhdlSource
1253 
                                false
1254 
                                udp2hibi
1255
1256
1257 
                                vhd/hibi_receiver.vhd
1258 
                                vhdlSource
1259 
                                false
1260 
                                udp2hibi
1261
1262
1263 
                                vhd/hibi_transmitter.vhd
1264 
                                vhdlSource
1265 
                                false
1266 
                                udp2hibi
1267
1268
1269 
                                vhd/rx_ctrl.vhd
1270 
                                vhdlSource
1271 
                                false
1272 
                                udp2hibi
1273
1274
1275 
                                vhd/tx_ctrl.vhd
1276 
                                vhdlSource
1277 
                                false
1278 
                                udp2hibi
1279
1280
1281 
                                vhd/udp2hibi.vhd
1282 
                                vhdlSource
1283 
                                false
1284 
                                udp2hibi
1285
1286
1287
1288 
                        Documentation
1289
1290 
                                doc/HIBI UDP v1.pptx
1291 
                                Documentation
1292 
                                false
1293
1294
1295
1296 
                        testbench
1297
1298 
                                tb/tb_ctrl_regs.vhd
1299 
                                vhdlSource
1300 
                                false
1301
1302
1303 
                                tb/tb_hibi_receiver.vhd
1304 
                                vhdlSource
1305 
                                false
1306
1307
1308 
                                tb/tb_hibi_test.vhd
1309 
                                vhdlSource
1310 
                                false
1311
1312
1313 
                                tb/tb_hibi_transmitter.vhd
1314 
                                vhdlSource
1315 
                                false
1316
1317
1318 
                                tb/tb_rx_ctrl.vhd
1319 
                                vhdlSource
1320 
                                false
1321
1322
1323 
                                tb/tb_tx_ctrl.vhd
1324 
                                vhdlSource
1325 
                                false
1326
1327
1328 
                                tb/tb_udp2hibi.vhd
1329 
                                vhdlSource
1330 
                                false
1331
1332
1333
1334
1335
1336
1337 
                                IP
1338 
                                HW
1339 
                                Mutable
1340
1341
1342
1343

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