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[/] [g729a_codec/] [trunk/] [SYN/] [XILINX/] [g729a_syn.tcl] - Blame information for rev 2

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1 2 madsilicon
# 
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# Project automation script for g729a_syn 
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# 
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# Created for ISE version 14.1
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# 
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# This file contains several Tcl procedures (procs) that you can use to automate
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# your project by running from xtclsh or the Project Navigator Tcl console.
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# If you load this file (using the Tcl command: source g729a_syn.tcl), then you can
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# run any of the procs included here.
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# 
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# This script is generated assuming your project has HDL sources.
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# Several of the defined procs won't apply to an EDIF or NGC based project.
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# If that is the case, simply remove them from this script.
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# 
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# You may also edit any of these procs to customize them. See comments in each
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# proc for more instructions.
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# 
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# This file contains the following procedures:
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# 
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# Top Level procs (meant to be called directly by the user):
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#    run_process: you can use this top-level procedure to run any processes
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#        that you choose to by adding and removing comments, or by
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#        adding new entries.
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#    rebuild_project: you can alternatively use this top-level procedure
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#        to recreate your entire project, and the run selected processes.
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# 
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# Lower Level (helper) procs (called under in various cases by the top level procs):
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#    show_help: print some basic information describing how this script works
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#    add_source_files: adds the listed source files to your project.
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#    set_project_props: sets the project properties that were in effect when this
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#        script was generated.
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#    create_libraries: creates and adds file to VHDL libraries that were defined when
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#        this script was generated.
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#    set_process_props: set the process properties as they were set for your project
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#        when this script was generated.
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# 
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set myProject "g729a_syn"
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set myScript "g729a_syn.tcl"
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# 
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# Main (top-level) routines
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# 
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# run_process
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# This procedure is used to run processes on an existing project. You may comment or
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# uncomment lines to control which processes are run. This routine is set up to run
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# the Implement Design and Generate Programming File processes by default. This proc
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# also sets process properties as specified in the "set_process_props" proc. Only
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# those properties which have values different from their current settings in the project
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# file will be modified in the project.
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# 
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proc run_process {} {
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   global myScript
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   global myProject
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   ## put out a 'heartbeat' - so we know something's happening.
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   puts "\n$myScript: running ($myProject)...\n"
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   if { ! [ open_project ] } {
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      return false
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   }
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   set_process_props
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   #
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   # Remove the comment characters (#'s) to enable the following commands 
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   # process run "Synthesize"
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   # process run "Translate"
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   # process run "Map"
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   # process run "Place & Route"
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   #
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   set task "Implement Design"
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   if { ! [run_task $task] } {
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      puts "$myScript: $task run failed, check run output for details."
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      project close
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      return
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   }
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   set task "Generate Programming File"
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   if { ! [run_task $task] } {
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      puts "$myScript: $task run failed, check run output for details."
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      project close
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      return
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   }
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   puts "Run completed (successfully)."
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   project close
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}
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# 
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# rebuild_project
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# 
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# This procedure renames the project file (if it exists) and recreates the project.
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# It then sets project properties and adds project sources as specified by the
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# set_project_props and add_source_files support procs. It recreates VHDL Libraries
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# as they existed at the time this script was generated.
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# 
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# It then calls run_process to set process properties and run selected processes.
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# 
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proc rebuild_project {} {
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   global myScript
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   global myProject
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   project close
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   ## put out a 'heartbeat' - so we know something's happening.
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   puts "\n$myScript: Rebuilding ($myProject)...\n"
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   set proj_exts [ list ise xise gise ]
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   foreach ext $proj_exts {
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      set proj_name "${myProject}.$ext"
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      if { [ file exists $proj_name ] } {
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         file delete $proj_name
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      }
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   }
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   project new $myProject
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   set_project_props
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   add_source_files
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   create_libraries
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   puts "$myScript: project rebuild completed."
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   run_process
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}
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# 
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# Support Routines
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# 
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# 
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proc run_task { task } {
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   # helper proc for run_process
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   puts "Running '$task'"
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   set result [ process run "$task" ]
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   #
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   # check process status (and result)
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   set status [ process get $task status ]
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   if { ( ( $status != "up_to_date" ) && \
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            ( $status != "warnings" ) ) || \
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         ! $result } {
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      return false
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   }
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   return true
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}
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# 
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# show_help: print information to help users understand the options available when
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#            running this script.
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# 
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proc show_help {} {
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   global myScript
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   puts ""
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   puts "usage: xtclsh $myScript <options>"
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   puts "       or you can run xtclsh and then enter 'source $myScript'."
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   puts ""
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   puts "options:"
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   puts "   run_process       - set properties and run processes."
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   puts "   rebuild_project   - rebuild the project from scratch and run processes."
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   puts "   set_project_props - set project properties (device, speed, etc.)"
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   puts "   add_source_files  - add source files"
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   puts "   create_libraries  - create vhdl libraries"
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   puts "   set_process_props - set process property values"
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   puts "   show_help         - print this message"
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   puts ""
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}
172
 
173
proc open_project {} {
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175
   global myScript
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   global myProject
177
 
178
   if { ! [ file exists ${myProject}.xise ] } {
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      ## project file isn't there, rebuild it.
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      puts "Project $myProject not found. Use project_rebuild to recreate it."
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      return false
182
   }
183
 
184
   project open $myProject
185
 
186
   return true
187
 
188
}
189
# 
190
# set_project_props
191
# 
192
# This procedure sets the project properties as they were set in the project
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# at the time this script was generated.
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# 
195
proc set_project_props {} {
196
 
197
   global myScript
198
 
199
   if { ! [ open_project ] } {
200
      return false
201
   }
202
 
203
   puts "$myScript: Setting project properties..."
204
 
205
   project set family "Virtex6"
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   project set device "xc6vlx75t"
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   project set package "ff484"
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   project set speed "-2"
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   project set top_level_module_type "HDL"
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   project set synthesis_tool "XST (VHDL/Verilog)"
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   project set simulator "Modelsim-SE Mixed"
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   project set "Preferred Language" "VHDL"
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   project set "Enable Message Filtering" "false"
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215
}
216
 
217
 
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# 
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# add_source_files
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# 
221
# This procedure add the source files that were known to the project at the
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# time this script was generated.
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# 
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proc add_source_files {} {
225
 
226
   global myScript
227
 
228
   if { ! [ open_project ] } {
229
      return false
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   }
231
 
232
   puts "$myScript: Adding sources to project..."
233
 
234
   xfile add "../../VHDL/G729A_asip_adder_f.vhd"
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   xfile add "../../VHDL/G729A_asip_addsub_pipeb.vhd"
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   xfile add "../../VHDL/G729A_asip_arith_pkg.vhd"
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   xfile add "../../VHDL/G729A_asip_basic_pkg.vhd"
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   xfile add "../../VHDL/G729A_asip_bjxlog.vhd"
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   xfile add "../../VHDL/G729A_asip_cfg_pkg.vhd"
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   xfile add "../../VHDL/G729A_asip_cpu_2w_p6.vhd"
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   xfile add "../../VHDL/G729A_asip_ftchlog_2w.vhd"
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   xfile add "../../VHDL/G729A_asip_fwdlog_2w_p6.vhd"
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   xfile add "../../VHDL/G729A_asip_idec.vhd"
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   xfile add "../../VHDL/G729A_asip_idec_2w.vhd"
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   xfile add "../../VHDL/G729A_asip_idec_2w_pkg.vhd"
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   xfile add "../../VHDL/G729A_asip_idec_pkg.vhd"
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   xfile add "../../VHDL/G729A_asip_ifq.vhd"
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   xfile add "../../VHDL/G729A_asip_lcstk.vhd"
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   xfile add "../../VHDL/G729A_asip_lcstklog_2w.vhd"
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   xfile add "../../VHDL/G729A_asip_lcstklog_ix.vhd"
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   xfile add "../../VHDL/G729A_asip_logic.vhd"
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   xfile add "../../VHDL/G729A_asip_lsu.vhd"
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   xfile add "../../VHDL/G729A_asip_lu.vhd"
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   xfile add "../../VHDL/G729A_asip_mulu_pipeb.vhd"
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   xfile add "../../VHDL/G729A_asip_op_pkg.vhd"
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   xfile add "../../VHDL/G729A_asip_pipe_a_2w.vhd"
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   xfile add "../../VHDL/G729A_asip_pipe_b.vhd"
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   xfile add "../../VHDL/G729A_asip_pkg.vhd"
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   xfile add "../../VHDL/G729A_asip_pstllog_2w_p6.vhd"
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   xfile add "../../VHDL/G729A_asip_pxlog.vhd"
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   xfile add "../../VHDL/G729A_asip_rams.vhd"
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   xfile add "../../VHDL/G729A_asip_regfile_16x16_2w.vhd"
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   xfile add "../../VHDL/G729A_asip_romd_pkg.vhd"
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   xfile add "../../VHDL/G729A_asip_romi_pkg.vhd"
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   xfile add "../../VHDL/G729A_asip_roms.vhd"
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   xfile add "../../VHDL/G729A_asip_shftu.vhd"
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   xfile add "../../VHDL/G729A_asip_spc.vhd"
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   xfile add "../../VHDL/G729A_asip_top_2w.vhd"
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   xfile add "../../VHDL/G729A_codec_intf_pkg.vhd"
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   xfile add "../../VHDL/G729A_codec_sdp.vhd"
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   xfile add "../../VHDL/G729A_codec_sdp_SYN.vhd"
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   xfile add "../../VHDL/SELF_TEST/G729A_codec_st_rom_pkg.vhd"
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   xfile add "../../VHDL/SELF_TEST/G729A_codec_st_roms.vhd"
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   xfile add "../../VHDL/SELF_TEST/G729A_codec_selftest.vhd"
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   xfile add "./g729a_syn.ucf"
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277
   # Set the Top Module as well...
278
   project set top "ARC" "G729A_CODEC_SDP_SYN"
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280
   puts "$myScript: project sources reloaded."
281
 
282
} ; # end add_source_files
283
 
284
# 
285
# create_libraries
286
# 
287
# This procedure defines VHDL libraries and associates files with those libraries.
288
# It is expected to be used when recreating the project. Any libraries defined
289
# when this script was generated are recreated by this procedure.
290
# 
291
proc create_libraries {} {
292
 
293
   global myScript
294
 
295
   if { ! [ open_project ] } {
296
      return false
297
   }
298
 
299
   puts "$myScript: Creating libraries..."
300
 
301
 
302
   # must close the project or library definitions aren't saved.
303
   project save
304
 
305
} ; # end create_libraries
306
 
307
# 
308
# set_process_props
309
# 
310
# This procedure sets properties as requested during script generation (either
311
# all of the properties, or only those modified from their defaults).
312
# 
313
proc set_process_props {} {
314
 
315
   global myScript
316
 
317
   if { ! [ open_project ] } {
318
      return false
319
   }
320
 
321
   puts "$myScript: setting process properties..."
322
 
323
   project set "Number of Clock Buffers" "16" -process "Synthesize - XST"
324
   project set "Target UCF File Name" "./g729a_syn.ucf" -process "Back-annotate Pin Locations"
325
   #project set "Synthesis Constraints File" "./g729a_syn.xcf" -process "Synthesize - XST"
326
 
327
   puts "$myScript: project property values set."
328
 
329
} ; # end set_process_props
330
 
331
proc main {} {
332
 
333
   if { [llength $::argv] == 0 } {
334
      show_help
335
      return true
336
   }
337
 
338
   foreach option $::argv {
339
      switch $option {
340
         "show_help"           { show_help }
341
         "run_process"         { run_process }
342
         "rebuild_project"     { rebuild_project }
343
         "set_project_props"   { set_project_props }
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         "add_source_files"    { add_source_files }
345
         "create_libraries"    { create_libraries }
346
         "set_process_props"   { set_process_props }
347
         default               { puts "unrecognized option: $option"; show_help }
348
      }
349
   }
350
}
351
 
352
if { $tcl_interactive } {
353
   show_help
354
} else {
355
   if {[catch {main} result]} {
356
      puts "$myScript failed: $result."
357
   }
358
}
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